1 /*
2 * drivers/usb/host/ehci-rcar_gen3.
3 * This file is EHCI HCD (Host Controller Driver) for USB.
4 *
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <errno.h>
12 #include <wait_bit.h>
13 #include <asm/io.h>
14 #include <usb/ehci-ci.h>
15 #include "ehci.h"
16
17 #define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
18
19 #define EHCI_USBCMD 0x120
20
21 #define CORE_SPD_RSM_TIMSET 0x30c
22 #define CORE_OC_TIMSET 0x310
23
24 /* Register offset */
25 #define AHB_OFFSET 0x200
26
27 #define BASE_HSUSB 0xE6590000
28 #define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
29 #define SUSPM 0x4000
30 #define SUSPM_NORMAL BIT(14)
31 #define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
32 #define USB0SEL 0x00000030
33 #define USB0SEL_EHCI 0x00000010
34
35 #define SMSTPCR7 0xE615014C
36 #define SMSTPCR700 BIT(0) /* EHCI3 */
37 #define SMSTPCR701 BIT(1) /* EHCI2 */
38 #define SMSTPCR702 BIT(2) /* EHCI1 */
39 #define SMSTPCR703 BIT(3) /* EHCI0 */
40 #define SMSTPCR704 BIT(4) /* HSUSB */
41
42 #define AHB_PLL_RST BIT(1)
43
44 #define USBH_INTBEN BIT(2)
45 #define USBH_INTAEN BIT(1)
46
47 #define AHB_INT_ENABLE 0x200
48 #define AHB_USBCTR 0x20c
49
ehci_hcd_stop(int index)50 int ehci_hcd_stop(int index)
51 {
52 #if defined(CONFIG_R8A7795)
53 const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
54 #else
55 const u32 mask = SMSTPCR703 | SMSTPCR702;
56 #endif
57 const u32 base = RCAR_GEN3_USB_BASE(index);
58 int ret;
59
60 /* Reset EHCI */
61 setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
62 ret = wait_for_bit_le32((void *)(uintptr_t)base + EHCI_USBCMD,
63 CMD_RESET, false, 10, true);
64 if (ret) {
65 printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
66 index, ret);
67 }
68
69 setbits_le32(SMSTPCR7, BIT(3 - index));
70
71 if ((readl(SMSTPCR7) & mask) == mask)
72 setbits_le32(SMSTPCR7, SMSTPCR704);
73
74 return 0;
75 }
76
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)77 int ehci_hcd_init(int index, enum usb_init_type init,
78 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
79 {
80 const void __iomem *base =
81 (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
82 struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
83
84 clrbits_le32(SMSTPCR7, BIT(3 - index));
85 clrbits_le32(SMSTPCR7, SMSTPCR704);
86
87 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
88 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
89 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
90
91 /* Enable interrupt */
92 setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
93 writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
94 writel(0x000209ab, base + CORE_OC_TIMSET);
95
96 /* Choice USB0SEL */
97 clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
98
99 /* Clock & Reset */
100 clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
101
102 /* low power status */
103 clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
104
105 return 0;
106 }
107