1 /* 2 * Copyright (c) 2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP21_RCC_H 8 #define STM32MP21_RCC_H 9 10 #include <lib/utils_def.h> 11 12 #define RCC_SECCFGR0 U(0x0) 13 #define RCC_SECCFGR1 U(0x4) 14 #define RCC_SECCFGR2 U(0x8) 15 #define RCC_SECCFGR3 U(0xC) 16 #define RCC_PRIVCFGR0 U(0x10) 17 #define RCC_PRIVCFGR1 U(0x14) 18 #define RCC_PRIVCFGR2 U(0x18) 19 #define RCC_PRIVCFGR3 U(0x1C) 20 #define RCC_RCFGLOCKR0 U(0x20) 21 #define RCC_RCFGLOCKR1 U(0x24) 22 #define RCC_RCFGLOCKR2 U(0x28) 23 #define RCC_RCFGLOCKR3 U(0x2C) 24 #define RCC_R0CIDCFGR U(0x30) 25 #define RCC_R0SEMCR U(0x34) 26 #define RCC_R1CIDCFGR U(0x38) 27 #define RCC_R1SEMCR U(0x3C) 28 #define RCC_R2CIDCFGR U(0x40) 29 #define RCC_R2SEMCR U(0x44) 30 #define RCC_R3CIDCFGR U(0x48) 31 #define RCC_R3SEMCR U(0x4C) 32 #define RCC_R4CIDCFGR U(0x50) 33 #define RCC_R4SEMCR U(0x54) 34 #define RCC_R5CIDCFGR U(0x58) 35 #define RCC_R5SEMCR U(0x5C) 36 #define RCC_R6CIDCFGR U(0x60) 37 #define RCC_R6SEMCR U(0x64) 38 #define RCC_R7CIDCFGR U(0x68) 39 #define RCC_R7SEMCR U(0x6C) 40 #define RCC_R8CIDCFGR U(0x70) 41 #define RCC_R8SEMCR U(0x74) 42 #define RCC_R9CIDCFGR U(0x78) 43 #define RCC_R9SEMCR U(0x7C) 44 #define RCC_R10CIDCFGR U(0x80) 45 #define RCC_R10SEMCR U(0x84) 46 #define RCC_R11CIDCFGR U(0x88) 47 #define RCC_R11SEMCR U(0x8C) 48 #define RCC_R12CIDCFGR U(0x90) 49 #define RCC_R12SEMCR U(0x94) 50 #define RCC_R13CIDCFGR U(0x98) 51 #define RCC_R13SEMCR U(0x9C) 52 #define RCC_R14CIDCFGR U(0xA0) 53 #define RCC_R14SEMCR U(0xA4) 54 #define RCC_R15CIDCFGR U(0xA8) 55 #define RCC_R15SEMCR U(0xAC) 56 #define RCC_R16CIDCFGR U(0xB0) 57 #define RCC_R16SEMCR U(0xB4) 58 #define RCC_R17CIDCFGR U(0xB8) 59 #define RCC_R17SEMCR U(0xBC) 60 #define RCC_R18CIDCFGR U(0xC0) 61 #define RCC_R18SEMCR U(0xC4) 62 #define RCC_R19CIDCFGR U(0xC8) 63 #define RCC_R19SEMCR U(0xCC) 64 #define RCC_R20CIDCFGR U(0xD0) 65 #define RCC_R20SEMCR U(0xD4) 66 #define RCC_R21CIDCFGR U(0xD8) 67 #define RCC_R21SEMCR U(0xDC) 68 #define RCC_R22CIDCFGR U(0xE0) 69 #define RCC_R22SEMCR U(0xE4) 70 #define RCC_R23CIDCFGR U(0xE8) 71 #define RCC_R23SEMCR U(0xEC) 72 #define RCC_R24CIDCFGR U(0xF0) 73 #define RCC_R24SEMCR U(0xF4) 74 #define RCC_R25CIDCFGR U(0xF8) 75 #define RCC_R25SEMCR U(0xFC) 76 #define RCC_R26CIDCFGR U(0x100) 77 #define RCC_R26SEMCR U(0x104) 78 #define RCC_R27CIDCFGR U(0x108) 79 #define RCC_R27SEMCR U(0x10C) 80 #define RCC_R28CIDCFGR U(0x110) 81 #define RCC_R28SEMCR U(0x114) 82 #define RCC_R29CIDCFGR U(0x118) 83 #define RCC_R29SEMCR U(0x11C) 84 #define RCC_R30CIDCFGR U(0x120) 85 #define RCC_R30SEMCR U(0x124) 86 #define RCC_R31CIDCFGR U(0x128) 87 #define RCC_R31SEMCR U(0x12C) 88 #define RCC_R32CIDCFGR U(0x130) 89 #define RCC_R32SEMCR U(0x134) 90 #define RCC_R33CIDCFGR U(0x138) 91 #define RCC_R33SEMCR U(0x13C) 92 #define RCC_R34CIDCFGR U(0x140) 93 #define RCC_R34SEMCR U(0x144) 94 #define RCC_R35CIDCFGR U(0x148) 95 #define RCC_R35SEMCR U(0x14C) 96 #define RCC_R36CIDCFGR U(0x150) 97 #define RCC_R36SEMCR U(0x154) 98 #define RCC_R37CIDCFGR U(0x158) 99 #define RCC_R37SEMCR U(0x15C) 100 #define RCC_R38CIDCFGR U(0x160) 101 #define RCC_R38SEMCR U(0x164) 102 #define RCC_R39CIDCFGR U(0x168) 103 #define RCC_R39SEMCR U(0x16C) 104 #define RCC_R40CIDCFGR U(0x170) 105 #define RCC_R40SEMCR U(0x174) 106 #define RCC_R41CIDCFGR U(0x178) 107 #define RCC_R41SEMCR U(0x17C) 108 #define RCC_R42CIDCFGR U(0x180) 109 #define RCC_R42SEMCR U(0x184) 110 #define RCC_R43CIDCFGR U(0x188) 111 #define RCC_R43SEMCR U(0x18C) 112 #define RCC_R44CIDCFGR U(0x190) 113 #define RCC_R44SEMCR U(0x194) 114 #define RCC_R45CIDCFGR U(0x198) 115 #define RCC_R45SEMCR U(0x19C) 116 #define RCC_R46CIDCFGR U(0x1A0) 117 #define RCC_R46SEMCR U(0x1A4) 118 #define RCC_R47CIDCFGR U(0x1A8) 119 #define RCC_R47SEMCR U(0x1AC) 120 #define RCC_R48CIDCFGR U(0x1B0) 121 #define RCC_R48SEMCR U(0x1B4) 122 #define RCC_R49CIDCFGR U(0x1B8) 123 #define RCC_R49SEMCR U(0x1BC) 124 #define RCC_R50CIDCFGR U(0x1C0) 125 #define RCC_R50SEMCR U(0x1C4) 126 #define RCC_R51CIDCFGR U(0x1C8) 127 #define RCC_R51SEMCR U(0x1CC) 128 #define RCC_R52CIDCFGR U(0x1D0) 129 #define RCC_R52SEMCR U(0x1D4) 130 #define RCC_R53CIDCFGR U(0x1D8) 131 #define RCC_R53SEMCR U(0x1DC) 132 #define RCC_R54CIDCFGR U(0x1E0) 133 #define RCC_R54SEMCR U(0x1E4) 134 #define RCC_R55CIDCFGR U(0x1E8) 135 #define RCC_R55SEMCR U(0x1EC) 136 #define RCC_R56CIDCFGR U(0x1F0) 137 #define RCC_R56SEMCR U(0x1F4) 138 #define RCC_R57CIDCFGR U(0x1F8) 139 #define RCC_R57SEMCR U(0x1FC) 140 #define RCC_R58CIDCFGR U(0x200) 141 #define RCC_R58SEMCR U(0x204) 142 #define RCC_R59CIDCFGR U(0x208) 143 #define RCC_R59SEMCR U(0x20C) 144 #define RCC_R60CIDCFGR U(0x210) 145 #define RCC_R60SEMCR U(0x214) 146 #define RCC_R61CIDCFGR U(0x218) 147 #define RCC_R61SEMCR U(0x21C) 148 #define RCC_R62CIDCFGR U(0x220) 149 #define RCC_R62SEMCR U(0x224) 150 #define RCC_R63CIDCFGR U(0x228) 151 #define RCC_R63SEMCR U(0x22C) 152 #define RCC_R64CIDCFGR U(0x230) 153 #define RCC_R64SEMCR U(0x234) 154 #define RCC_R65CIDCFGR U(0x238) 155 #define RCC_R65SEMCR U(0x23C) 156 #define RCC_R66CIDCFGR U(0x240) 157 #define RCC_R66SEMCR U(0x244) 158 #define RCC_R67CIDCFGR U(0x248) 159 #define RCC_R67SEMCR U(0x24C) 160 #define RCC_R68CIDCFGR U(0x250) 161 #define RCC_R68SEMCR U(0x254) 162 #define RCC_R69CIDCFGR U(0x258) 163 #define RCC_R69SEMCR U(0x25C) 164 #define RCC_R70CIDCFGR U(0x260) 165 #define RCC_R70SEMCR U(0x264) 166 #define RCC_R71CIDCFGR U(0x268) 167 #define RCC_R71SEMCR U(0x26C) 168 #define RCC_R72CIDCFGR U(0x270) 169 #define RCC_R72SEMCR U(0x274) 170 #define RCC_R73CIDCFGR U(0x278) 171 #define RCC_R73SEMCR U(0x27C) 172 #define RCC_R74CIDCFGR U(0x280) 173 #define RCC_R74SEMCR U(0x284) 174 #define RCC_R75CIDCFGR U(0x288) 175 #define RCC_R75SEMCR U(0x28C) 176 #define RCC_R76CIDCFGR U(0x290) 177 #define RCC_R76SEMCR U(0x294) 178 #define RCC_R77CIDCFGR U(0x298) 179 #define RCC_R77SEMCR U(0x29C) 180 #define RCC_R78CIDCFGR U(0x2A0) 181 #define RCC_R78SEMCR U(0x2A4) 182 #define RCC_R79CIDCFGR U(0x2A8) 183 #define RCC_R79SEMCR U(0x2AC) 184 #define RCC_R80CIDCFGR U(0x2B0) 185 #define RCC_R80SEMCR U(0x2B4) 186 #define RCC_R81CIDCFGR U(0x2B8) 187 #define RCC_R81SEMCR U(0x2BC) 188 #define RCC_R82CIDCFGR U(0x2C0) 189 #define RCC_R82SEMCR U(0x2C4) 190 #define RCC_R83CIDCFGR U(0x2C8) 191 #define RCC_R83SEMCR U(0x2CC) 192 #define RCC_R84CIDCFGR U(0x2D0) 193 #define RCC_R84SEMCR U(0x2D4) 194 #define RCC_R85CIDCFGR U(0x2D8) 195 #define RCC_R85SEMCR U(0x2DC) 196 #define RCC_R86CIDCFGR U(0x2E0) 197 #define RCC_R86SEMCR U(0x2E4) 198 #define RCC_R87CIDCFGR U(0x2E8) 199 #define RCC_R87SEMCR U(0x2EC) 200 #define RCC_R88CIDCFGR U(0x2F0) 201 #define RCC_R88SEMCR U(0x2F4) 202 #define RCC_R89CIDCFGR U(0x2F8) 203 #define RCC_R89SEMCR U(0x2FC) 204 #define RCC_R90CIDCFGR U(0x300) 205 #define RCC_R90SEMCR U(0x304) 206 #define RCC_R91CIDCFGR U(0x308) 207 #define RCC_R91SEMCR U(0x30C) 208 #define RCC_R92CIDCFGR U(0x310) 209 #define RCC_R92SEMCR U(0x314) 210 #define RCC_R93CIDCFGR U(0x318) 211 #define RCC_R93SEMCR U(0x31C) 212 #define RCC_R94CIDCFGR U(0x320) 213 #define RCC_R94SEMCR U(0x324) 214 #define RCC_R95CIDCFGR U(0x328) 215 #define RCC_R95SEMCR U(0x32C) 216 #define RCC_R96CIDCFGR U(0x330) 217 #define RCC_R96SEMCR U(0x334) 218 #define RCC_R97CIDCFGR U(0x338) 219 #define RCC_R97SEMCR U(0x33C) 220 #define RCC_R98CIDCFGR U(0x340) 221 #define RCC_R98SEMCR U(0x344) 222 #define RCC_R99CIDCFGR U(0x348) 223 #define RCC_R99SEMCR U(0x34C) 224 #define RCC_R100CIDCFGR U(0x350) 225 #define RCC_R100SEMCR U(0x354) 226 #define RCC_R101CIDCFGR U(0x358) 227 #define RCC_R101SEMCR U(0x35C) 228 #define RCC_R102CIDCFGR U(0x360) 229 #define RCC_R102SEMCR U(0x364) 230 #define RCC_R103CIDCFGR U(0x368) 231 #define RCC_R103SEMCR U(0x36C) 232 #define RCC_R104CIDCFGR U(0x370) 233 #define RCC_R104SEMCR U(0x374) 234 #define RCC_R105CIDCFGR U(0x378) 235 #define RCC_R105SEMCR U(0x37C) 236 #define RCC_R106CIDCFGR U(0x380) 237 #define RCC_R106SEMCR U(0x384) 238 #define RCC_R107CIDCFGR U(0x388) 239 #define RCC_R107SEMCR U(0x38C) 240 #define RCC_R108CIDCFGR U(0x390) 241 #define RCC_R108SEMCR U(0x394) 242 #define RCC_R109CIDCFGR U(0x398) 243 #define RCC_R109SEMCR U(0x39C) 244 #define RCC_R110CIDCFGR U(0x3A0) 245 #define RCC_R110SEMCR U(0x3A4) 246 #define RCC_R111CIDCFGR U(0x3A8) 247 #define RCC_R111SEMCR U(0x3AC) 248 #define RCC_R112CIDCFGR U(0x3B0) 249 #define RCC_R112SEMCR U(0x3B4) 250 #define RCC_R113CIDCFGR U(0x3B8) 251 #define RCC_R113SEMCR U(0x3BC) 252 #define RCC_GRSTCSETR U(0x400) 253 #define RCC_C1RSTCSETR U(0x404) 254 #define RCC_C2RSTCSETR U(0x40C) 255 #define RCC_HWRSTSCLRR U(0x410) 256 #define RCC_C1HWRSTSCLRR U(0x414) 257 #define RCC_C2HWRSTSCLRR U(0x418) 258 #define RCC_C1BOOTRSTSSETR U(0x41C) 259 #define RCC_C1BOOTRSTSCLRR U(0x420) 260 #define RCC_C2BOOTRSTSSETR U(0x424) 261 #define RCC_C2BOOTRSTSCLRR U(0x428) 262 #define RCC_C1SREQSETR U(0x42C) 263 #define RCC_C1SREQCLRR U(0x430) 264 #define RCC_CPUBOOTCR U(0x434) 265 #define RCC_STBYBOOTCR U(0x438) 266 #define RCC_LEGBOOTCR U(0x43C) 267 #define RCC_BDCR U(0x440) 268 #define RCC_RDCR U(0x44C) 269 #define RCC_C1MSRDCR U(0x450) 270 #define RCC_PWRLPDLYCR U(0x454) 271 #define RCC_C1CIESETR U(0x458) 272 #define RCC_C1CIFCLRR U(0x45C) 273 #define RCC_C2CIESETR U(0x460) 274 #define RCC_C2CIFCLRR U(0x464) 275 #define RCC_IWDGC1FZSETR U(0x468) 276 #define RCC_IWDGC1FZCLRR U(0x46C) 277 #define RCC_IWDGC1CFGSETR U(0x470) 278 #define RCC_IWDGC1CFGCLRR U(0x474) 279 #define RCC_IWDGC2FZSETR U(0x478) 280 #define RCC_IWDGC2FZCLRR U(0x47C) 281 #define RCC_IWDGC2CFGSETR U(0x480) 282 #define RCC_IWDGC2CFGCLRR U(0x484) 283 #define RCC_MCO1CFGR U(0x488) 284 #define RCC_MCO2CFGR U(0x48C) 285 #define RCC_OCENSETR U(0x490) 286 #define RCC_OCENCLRR U(0x494) 287 #define RCC_OCRDYR U(0x498) 288 #define RCC_HSICFGR U(0x49C) 289 #define RCC_MSICFGR U(0x4A0) 290 #define RCC_LSICR U(0x4A4) 291 #define RCC_RTCDIVR U(0x4A8) 292 #define RCC_APB1DIVR U(0x4AC) 293 #define RCC_APB2DIVR U(0x4B0) 294 #define RCC_APB3DIVR U(0x4B4) 295 #define RCC_APB4DIVR U(0x4B8) 296 #define RCC_APB5DIVR U(0x4BC) 297 #define RCC_APBDBGDIVR U(0x4C0) 298 #define RCC_TIMG1PRER U(0x4C8) 299 #define RCC_TIMG2PRER U(0x4CC) 300 #define RCC_LSMCUDIVR U(0x4D0) 301 #define RCC_DDRCPCFGR U(0x4D4) 302 #define RCC_DDRCAPBCFGR U(0x4D8) 303 #define RCC_DDRPHYCAPBCFGR U(0x4DC) 304 #define RCC_DDRPHYCCFGR U(0x4E0) 305 #define RCC_DDRCFGR U(0x4E4) 306 #define RCC_DDRITFCFGR U(0x4E8) 307 #define RCC_SYSRAMCFGR U(0x4F0) 308 #define RCC_SRAM1CFGR U(0x4F8) 309 #define RCC_RETRAMCFGR U(0x500) 310 #define RCC_BKPSRAMCFGR U(0x504) 311 #define RCC_OSPI1CFGR U(0x514) 312 #define RCC_FMCCFGR U(0x51C) 313 #define RCC_DBGCFGR U(0x520) 314 #define RCC_STMCFGR U(0x524) 315 #define RCC_ETRCFGR U(0x528) 316 #define RCC_GPIOACFGR U(0x52C) 317 #define RCC_GPIOBCFGR U(0x530) 318 #define RCC_GPIOCCFGR U(0x534) 319 #define RCC_GPIODCFGR U(0x538) 320 #define RCC_GPIOECFGR U(0x53C) 321 #define RCC_GPIOFCFGR U(0x540) 322 #define RCC_GPIOGCFGR U(0x544) 323 #define RCC_GPIOHCFGR U(0x548) 324 #define RCC_GPIOICFGR U(0x54C) 325 #define RCC_GPIOZCFGR U(0x558) 326 #define RCC_HPDMA1CFGR U(0x55C) 327 #define RCC_HPDMA2CFGR U(0x560) 328 #define RCC_HPDMA3CFGR U(0x564) 329 #define RCC_IPCC1CFGR U(0x570) 330 #define RCC_RTCCFGR U(0x578) 331 #define RCC_SYSCPU1CFGR U(0x580) 332 #define RCC_BSECCFGR U(0x584) 333 #define RCC_PLL2CFGR1 U(0x590) 334 #define RCC_PLL2CFGR2 U(0x594) 335 #define RCC_PLL2CFGR3 U(0x598) 336 #define RCC_PLL2CFGR4 U(0x59C) 337 #define RCC_PLL2CFGR5 U(0x5A0) 338 #define RCC_PLL2CFGR6 U(0x5A8) 339 #define RCC_PLL2CFGR7 U(0x5AC) 340 #define RCC_HSIFMONCR U(0x5E0) 341 #define RCC_HSIFVALR U(0x5E4) 342 #define RCC_MSIFMONCR U(0x5E8) 343 #define RCC_MSIFVALR U(0x5EC) 344 #define RCC_TIM1CFGR U(0x700) 345 #define RCC_TIM2CFGR U(0x704) 346 #define RCC_TIM3CFGR U(0x708) 347 #define RCC_TIM4CFGR U(0x70C) 348 #define RCC_TIM5CFGR U(0x710) 349 #define RCC_TIM6CFGR U(0x714) 350 #define RCC_TIM7CFGR U(0x718) 351 #define RCC_TIM8CFGR U(0x71C) 352 #define RCC_TIM10CFGR U(0x720) 353 #define RCC_TIM11CFGR U(0x724) 354 #define RCC_TIM12CFGR U(0x728) 355 #define RCC_TIM13CFGR U(0x72C) 356 #define RCC_TIM14CFGR U(0x730) 357 #define RCC_TIM15CFGR U(0x734) 358 #define RCC_TIM16CFGR U(0x738) 359 #define RCC_TIM17CFGR U(0x73C) 360 #define RCC_LPTIM1CFGR U(0x744) 361 #define RCC_LPTIM2CFGR U(0x748) 362 #define RCC_LPTIM3CFGR U(0x74C) 363 #define RCC_LPTIM4CFGR U(0x750) 364 #define RCC_LPTIM5CFGR U(0x754) 365 #define RCC_SPI1CFGR U(0x758) 366 #define RCC_SPI2CFGR U(0x75C) 367 #define RCC_SPI3CFGR U(0x760) 368 #define RCC_SPI4CFGR U(0x764) 369 #define RCC_SPI5CFGR U(0x768) 370 #define RCC_SPI6CFGR U(0x76C) 371 #define RCC_SPDIFRXCFGR U(0x778) 372 #define RCC_USART1CFGR U(0x77C) 373 #define RCC_USART2CFGR U(0x780) 374 #define RCC_USART3CFGR U(0x784) 375 #define RCC_UART4CFGR U(0x788) 376 #define RCC_UART5CFGR U(0x78C) 377 #define RCC_USART6CFGR U(0x790) 378 #define RCC_UART7CFGR U(0x794) 379 #define RCC_LPUART1CFGR U(0x7A0) 380 #define RCC_I2C1CFGR U(0x7A4) 381 #define RCC_I2C2CFGR U(0x7A8) 382 #define RCC_I2C3CFGR U(0x7AC) 383 #define RCC_SAI1CFGR U(0x7C4) 384 #define RCC_SAI2CFGR U(0x7C8) 385 #define RCC_SAI3CFGR U(0x7CC) 386 #define RCC_SAI4CFGR U(0x7D0) 387 #define RCC_MDF1CFGR U(0x7D8) 388 #define RCC_FDCANCFGR U(0x7E0) 389 #define RCC_HDPCFGR U(0x7E4) 390 #define RCC_ADC1CFGR U(0x7E8) 391 #define RCC_ADC2CFGR U(0x7EC) 392 #define RCC_ETH1CFGR U(0x7F0) 393 #define RCC_ETH2CFGR U(0x7F4) 394 #define RCC_USBHCFGR U(0x7FC) 395 #define RCC_USB2PHY1CFGR U(0x800) 396 #define RCC_OTGCFGR U(0x808) 397 #define RCC_USB2PHY2CFGR U(0x80C) 398 #define RCC_STGENCFGR U(0x824) 399 #define RCC_SDMMC1CFGR U(0x830) 400 #define RCC_SDMMC2CFGR U(0x834) 401 #define RCC_SDMMC3CFGR U(0x838) 402 #define RCC_LTDCCFGR U(0x840) 403 #define RCC_CSICFGR U(0x858) 404 #define RCC_DCMIPPCFGR U(0x85C) 405 #define RCC_DCMIPSSICFGR U(0x860) 406 #define RCC_RNG1CFGR U(0x870) 407 #define RCC_RNG2CFGR U(0x874) 408 #define RCC_PKACFGR U(0x878) 409 #define RCC_SAESCFGR U(0x87C) 410 #define RCC_HASH1CFGR U(0x880) 411 #define RCC_HASH2CFGR U(0x884) 412 #define RCC_CRYP1CFGR U(0x888) 413 #define RCC_CRYP2CFGR U(0x88C) 414 #define RCC_IWDG1CFGR U(0x894) 415 #define RCC_IWDG2CFGR U(0x898) 416 #define RCC_IWDG3CFGR U(0x89C) 417 #define RCC_IWDG4CFGR U(0x8A0) 418 #define RCC_WWDG1CFGR U(0x8A4) 419 #define RCC_VREFCFGR U(0x8AC) 420 #define RCC_DTSCFGR U(0x8B0) 421 #define RCC_CRCCFGR U(0x8B4) 422 #define RCC_SERCCFGR U(0x8B8) 423 #define RCC_DDRPERFMCFGR U(0x8C0) 424 #define RCC_I3C1CFGR U(0x8C8) 425 #define RCC_I3C2CFGR U(0x8CC) 426 #define RCC_I3C3CFGR U(0x8D0) 427 #define RCC_MUXSELCFGR U(0x1000) 428 #define RCC_XBAR0CFGR U(0x1018) 429 #define RCC_XBAR1CFGR U(0x101C) 430 #define RCC_XBAR2CFGR U(0x1020) 431 #define RCC_XBAR3CFGR U(0x1024) 432 #define RCC_XBAR4CFGR U(0x1028) 433 #define RCC_XBAR5CFGR U(0x102C) 434 #define RCC_XBAR6CFGR U(0x1030) 435 #define RCC_XBAR7CFGR U(0x1034) 436 #define RCC_XBAR8CFGR U(0x1038) 437 #define RCC_XBAR9CFGR U(0x103C) 438 #define RCC_XBAR10CFGR U(0x1040) 439 #define RCC_XBAR11CFGR U(0x1044) 440 #define RCC_XBAR12CFGR U(0x1048) 441 #define RCC_XBAR13CFGR U(0x104C) 442 #define RCC_XBAR14CFGR U(0x1050) 443 #define RCC_XBAR15CFGR U(0x1054) 444 #define RCC_XBAR16CFGR U(0x1058) 445 #define RCC_XBAR17CFGR U(0x105C) 446 #define RCC_XBAR18CFGR U(0x1060) 447 #define RCC_XBAR19CFGR U(0x1064) 448 #define RCC_XBAR20CFGR U(0x1068) 449 #define RCC_XBAR21CFGR U(0x106C) 450 #define RCC_XBAR22CFGR U(0x1070) 451 #define RCC_XBAR23CFGR U(0x1074) 452 #define RCC_XBAR24CFGR U(0x1078) 453 #define RCC_XBAR25CFGR U(0x107C) 454 #define RCC_XBAR26CFGR U(0x1080) 455 #define RCC_XBAR27CFGR U(0x1084) 456 #define RCC_XBAR28CFGR U(0x1088) 457 #define RCC_XBAR29CFGR U(0x108C) 458 #define RCC_XBAR30CFGR U(0x1090) 459 #define RCC_XBAR31CFGR U(0x1094) 460 #define RCC_XBAR32CFGR U(0x1098) 461 #define RCC_XBAR33CFGR U(0x109C) 462 #define RCC_XBAR34CFGR U(0x10A0) 463 #define RCC_XBAR35CFGR U(0x10A4) 464 #define RCC_XBAR36CFGR U(0x10A8) 465 #define RCC_XBAR37CFGR U(0x10AC) 466 #define RCC_XBAR38CFGR U(0x10B0) 467 #define RCC_XBAR39CFGR U(0x10B4) 468 #define RCC_XBAR40CFGR U(0x10B8) 469 #define RCC_XBAR41CFGR U(0x10BC) 470 #define RCC_XBAR42CFGR U(0x10C0) 471 #define RCC_XBAR43CFGR U(0x10C4) 472 #define RCC_XBAR44CFGR U(0x10C8) 473 #define RCC_XBAR45CFGR U(0x10CC) 474 #define RCC_XBAR46CFGR U(0x10D0) 475 #define RCC_XBAR47CFGR U(0x10D4) 476 #define RCC_XBAR48CFGR U(0x10D8) 477 #define RCC_XBAR49CFGR U(0x10DC) 478 #define RCC_XBAR50CFGR U(0x10E0) 479 #define RCC_XBAR51CFGR U(0x10E4) 480 #define RCC_XBAR52CFGR U(0x10E8) 481 #define RCC_XBAR53CFGR U(0x10EC) 482 #define RCC_XBAR54CFGR U(0x10F0) 483 #define RCC_XBAR55CFGR U(0x10F4) 484 #define RCC_XBAR56CFGR U(0x10F8) 485 #define RCC_XBAR57CFGR U(0x10FC) 486 #define RCC_XBAR58CFGR U(0x1100) 487 #define RCC_XBAR59CFGR U(0x1104) 488 #define RCC_XBAR60CFGR U(0x1108) 489 #define RCC_XBAR61CFGR U(0x110C) 490 #define RCC_XBAR62CFGR U(0x1110) 491 #define RCC_XBAR63CFGR U(0x1114) 492 #define RCC_PREDIV0CFGR U(0x1118) 493 #define RCC_PREDIV1CFGR U(0x111C) 494 #define RCC_PREDIV2CFGR U(0x1120) 495 #define RCC_PREDIV3CFGR U(0x1124) 496 #define RCC_PREDIV4CFGR U(0x1128) 497 #define RCC_PREDIV5CFGR U(0x112C) 498 #define RCC_PREDIV6CFGR U(0x1130) 499 #define RCC_PREDIV7CFGR U(0x1134) 500 #define RCC_PREDIV8CFGR U(0x1138) 501 #define RCC_PREDIV9CFGR U(0x113C) 502 #define RCC_PREDIV10CFGR U(0x1140) 503 #define RCC_PREDIV11CFGR U(0x1144) 504 #define RCC_PREDIV12CFGR U(0x1148) 505 #define RCC_PREDIV13CFGR U(0x114C) 506 #define RCC_PREDIV14CFGR U(0x1150) 507 #define RCC_PREDIV15CFGR U(0x1154) 508 #define RCC_PREDIV16CFGR U(0x1158) 509 #define RCC_PREDIV17CFGR U(0x115C) 510 #define RCC_PREDIV18CFGR U(0x1160) 511 #define RCC_PREDIV19CFGR U(0x1164) 512 #define RCC_PREDIV20CFGR U(0x1168) 513 #define RCC_PREDIV21CFGR U(0x116C) 514 #define RCC_PREDIV22CFGR U(0x1170) 515 #define RCC_PREDIV23CFGR U(0x1174) 516 #define RCC_PREDIV24CFGR U(0x1178) 517 #define RCC_PREDIV25CFGR U(0x117C) 518 #define RCC_PREDIV26CFGR U(0x1180) 519 #define RCC_PREDIV27CFGR U(0x1184) 520 #define RCC_PREDIV28CFGR U(0x1188) 521 #define RCC_PREDIV29CFGR U(0x118C) 522 #define RCC_PREDIV30CFGR U(0x1190) 523 #define RCC_PREDIV31CFGR U(0x1194) 524 #define RCC_PREDIV32CFGR U(0x1198) 525 #define RCC_PREDIV33CFGR U(0x119C) 526 #define RCC_PREDIV34CFGR U(0x11A0) 527 #define RCC_PREDIV35CFGR U(0x11A4) 528 #define RCC_PREDIV36CFGR U(0x11A8) 529 #define RCC_PREDIV37CFGR U(0x11AC) 530 #define RCC_PREDIV38CFGR U(0x11B0) 531 #define RCC_PREDIV39CFGR U(0x11B4) 532 #define RCC_PREDIV40CFGR U(0x11B8) 533 #define RCC_PREDIV41CFGR U(0x11BC) 534 #define RCC_PREDIV42CFGR U(0x11C0) 535 #define RCC_PREDIV43CFGR U(0x11C4) 536 #define RCC_PREDIV44CFGR U(0x11C8) 537 #define RCC_PREDIV45CFGR U(0x11CC) 538 #define RCC_PREDIV46CFGR U(0x11D0) 539 #define RCC_PREDIV47CFGR U(0x11D4) 540 #define RCC_PREDIV48CFGR U(0x11D8) 541 #define RCC_PREDIV49CFGR U(0x11DC) 542 #define RCC_PREDIV50CFGR U(0x11E0) 543 #define RCC_PREDIV51CFGR U(0x11E4) 544 #define RCC_PREDIV52CFGR U(0x11E8) 545 #define RCC_PREDIV53CFGR U(0x11EC) 546 #define RCC_PREDIV54CFGR U(0x11F0) 547 #define RCC_PREDIV55CFGR U(0x11F4) 548 #define RCC_PREDIV56CFGR U(0x11F8) 549 #define RCC_PREDIV57CFGR U(0x11FC) 550 #define RCC_PREDIV58CFGR U(0x1200) 551 #define RCC_PREDIV59CFGR U(0x1204) 552 #define RCC_PREDIV60CFGR U(0x1208) 553 #define RCC_PREDIV61CFGR U(0x120C) 554 #define RCC_PREDIV62CFGR U(0x1210) 555 #define RCC_PREDIV63CFGR U(0x1214) 556 #define RCC_PREDIVSR1 U(0x1218) 557 #define RCC_PREDIVSR2 U(0x121C) 558 #define RCC_FINDIV0CFGR U(0x1224) 559 #define RCC_FINDIV1CFGR U(0x1228) 560 #define RCC_FINDIV2CFGR U(0x122C) 561 #define RCC_FINDIV3CFGR U(0x1230) 562 #define RCC_FINDIV4CFGR U(0x1234) 563 #define RCC_FINDIV5CFGR U(0x1238) 564 #define RCC_FINDIV6CFGR U(0x123C) 565 #define RCC_FINDIV7CFGR U(0x1240) 566 #define RCC_FINDIV8CFGR U(0x1244) 567 #define RCC_FINDIV9CFGR U(0x1248) 568 #define RCC_FINDIV10CFGR U(0x124C) 569 #define RCC_FINDIV11CFGR U(0x1250) 570 #define RCC_FINDIV12CFGR U(0x1254) 571 #define RCC_FINDIV13CFGR U(0x1258) 572 #define RCC_FINDIV14CFGR U(0x125C) 573 #define RCC_FINDIV15CFGR U(0x1260) 574 #define RCC_FINDIV16CFGR U(0x1264) 575 #define RCC_FINDIV17CFGR U(0x1268) 576 #define RCC_FINDIV18CFGR U(0x126C) 577 #define RCC_FINDIV19CFGR U(0x1270) 578 #define RCC_FINDIV20CFGR U(0x1274) 579 #define RCC_FINDIV21CFGR U(0x1278) 580 #define RCC_FINDIV22CFGR U(0x127C) 581 #define RCC_FINDIV23CFGR U(0x1280) 582 #define RCC_FINDIV24CFGR U(0x1284) 583 #define RCC_FINDIV25CFGR U(0x1288) 584 #define RCC_FINDIV26CFGR U(0x128C) 585 #define RCC_FINDIV27CFGR U(0x1290) 586 #define RCC_FINDIV28CFGR U(0x1294) 587 #define RCC_FINDIV29CFGR U(0x1298) 588 #define RCC_FINDIV30CFGR U(0x129C) 589 #define RCC_FINDIV31CFGR U(0x12A0) 590 #define RCC_FINDIV32CFGR U(0x12A4) 591 #define RCC_FINDIV33CFGR U(0x12A8) 592 #define RCC_FINDIV34CFGR U(0x12AC) 593 #define RCC_FINDIV35CFGR U(0x12B0) 594 #define RCC_FINDIV36CFGR U(0x12B4) 595 #define RCC_FINDIV37CFGR U(0x12B8) 596 #define RCC_FINDIV38CFGR U(0x12BC) 597 #define RCC_FINDIV39CFGR U(0x12C0) 598 #define RCC_FINDIV40CFGR U(0x12C4) 599 #define RCC_FINDIV41CFGR U(0x12C8) 600 #define RCC_FINDIV42CFGR U(0x12CC) 601 #define RCC_FINDIV43CFGR U(0x12D0) 602 #define RCC_FINDIV44CFGR U(0x12D4) 603 #define RCC_FINDIV45CFGR U(0x12D8) 604 #define RCC_FINDIV46CFGR U(0x12DC) 605 #define RCC_FINDIV47CFGR U(0x12E0) 606 #define RCC_FINDIV48CFGR U(0x12E4) 607 #define RCC_FINDIV49CFGR U(0x12E8) 608 #define RCC_FINDIV50CFGR U(0x12EC) 609 #define RCC_FINDIV51CFGR U(0x12F0) 610 #define RCC_FINDIV52CFGR U(0x12F4) 611 #define RCC_FINDIV53CFGR U(0x12F8) 612 #define RCC_FINDIV54CFGR U(0x12FC) 613 #define RCC_FINDIV55CFGR U(0x1300) 614 #define RCC_FINDIV56CFGR U(0x1304) 615 #define RCC_FINDIV57CFGR U(0x1308) 616 #define RCC_FINDIV58CFGR U(0x130C) 617 #define RCC_FINDIV59CFGR U(0x1310) 618 #define RCC_FINDIV60CFGR U(0x1314) 619 #define RCC_FINDIV61CFGR U(0x1318) 620 #define RCC_FINDIV62CFGR U(0x131C) 621 #define RCC_FINDIV63CFGR U(0x1320) 622 #define RCC_FINDIVSR1 U(0x1324) 623 #define RCC_FINDIVSR2 U(0x1328) 624 #define RCC_FCALCOBS0CFGR U(0x1340) 625 #define RCC_FCALCOBS1CFGR U(0x1344) 626 #define RCC_FCALCREFCFGR U(0x1348) 627 #define RCC_FCALCCR1 U(0x134C) 628 #define RCC_FCALCCR2 U(0x1354) 629 #define RCC_FCALCSR U(0x1358) 630 #define RCC_PLL4CFGR1 U(0x1360) 631 #define RCC_PLL4CFGR2 U(0x1364) 632 #define RCC_PLL4CFGR3 U(0x1368) 633 #define RCC_PLL4CFGR4 U(0x136C) 634 #define RCC_PLL4CFGR5 U(0x1370) 635 #define RCC_PLL4CFGR6 U(0x1378) 636 #define RCC_PLL4CFGR7 U(0x137C) 637 #define RCC_PLL5CFGR1 U(0x1388) 638 #define RCC_PLL5CFGR2 U(0x138C) 639 #define RCC_PLL5CFGR3 U(0x1390) 640 #define RCC_PLL5CFGR4 U(0x1394) 641 #define RCC_PLL5CFGR5 U(0x1398) 642 #define RCC_PLL5CFGR6 U(0x13A0) 643 #define RCC_PLL5CFGR7 U(0x13A4) 644 #define RCC_PLL6CFGR1 U(0x13B0) 645 #define RCC_PLL6CFGR2 U(0x13B4) 646 #define RCC_PLL6CFGR3 U(0x13B8) 647 #define RCC_PLL6CFGR4 U(0x13BC) 648 #define RCC_PLL6CFGR5 U(0x13C0) 649 #define RCC_PLL6CFGR6 U(0x13C8) 650 #define RCC_PLL6CFGR7 U(0x13CC) 651 #define RCC_PLL7CFGR1 U(0x13D8) 652 #define RCC_PLL7CFGR2 U(0x13DC) 653 #define RCC_PLL7CFGR3 U(0x13E0) 654 #define RCC_PLL7CFGR4 U(0x13E4) 655 #define RCC_PLL7CFGR5 U(0x13E8) 656 #define RCC_PLL7CFGR6 U(0x13F0) 657 #define RCC_PLL7CFGR7 U(0x13F4) 658 #define RCC_PLL8CFGR1 U(0x1400) 659 #define RCC_PLL8CFGR2 U(0x1404) 660 #define RCC_PLL8CFGR3 U(0x1408) 661 #define RCC_PLL8CFGR4 U(0x140C) 662 #define RCC_PLL8CFGR5 U(0x1410) 663 #define RCC_PLL8CFGR6 U(0x1418) 664 #define RCC_PLL8CFGR7 U(0x141C) 665 #define RCC_VERR U(0xFFF4) 666 #define RCC_IDR U(0xFFF8) 667 #define RCC_SIDR U(0xFFFC) 668 669 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 670 #define RCC_MP_ENCLRR_OFFSET U(4) 671 672 /* RCC_SECCFGR3 register fields */ 673 #define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0) 674 #define RCC_SECCFGR3_SEC_SHIFT 0 675 676 /* RCC_PRIVCFGR3 register fields */ 677 #define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0) 678 #define RCC_PRIVCFGR3_PRIV_SHIFT 0 679 680 /* RCC_RCFGLOCKR3 register fields */ 681 #define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0) 682 #define RCC_RCFGLOCKR3_RLOCK_SHIFT 0 683 684 /* RCC_R0CIDCFGR register fields */ 685 #define RCC_R0CIDCFGR_CFEN BIT(0) 686 #define RCC_R0CIDCFGR_SEM_EN BIT(1) 687 #define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) 688 #define RCC_R0CIDCFGR_SCID_SHIFT 4 689 #define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 690 #define RCC_R0CIDCFGR_SEMWLC_SHIFT 16 691 692 /* RCC_R0SEMCR register fields */ 693 #define RCC_R0SEMCR_SEM_MUTEX BIT(0) 694 #define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4) 695 #define RCC_R0SEMCR_SEMCID_SHIFT 4 696 697 /* RCC_R1CIDCFGR register fields */ 698 #define RCC_R1CIDCFGR_CFEN BIT(0) 699 #define RCC_R1CIDCFGR_SEM_EN BIT(1) 700 #define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) 701 #define RCC_R1CIDCFGR_SCID_SHIFT 4 702 #define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 703 #define RCC_R1CIDCFGR_SEMWLC_SHIFT 16 704 705 /* RCC_R1SEMCR register fields */ 706 #define RCC_R1SEMCR_SEM_MUTEX BIT(0) 707 #define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4) 708 #define RCC_R1SEMCR_SEMCID_SHIFT 4 709 710 /* RCC_R2CIDCFGR register fields */ 711 #define RCC_R2CIDCFGR_CFEN BIT(0) 712 #define RCC_R2CIDCFGR_SEM_EN BIT(1) 713 #define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) 714 #define RCC_R2CIDCFGR_SCID_SHIFT 4 715 #define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 716 #define RCC_R2CIDCFGR_SEMWLC_SHIFT 16 717 718 /* RCC_R2SEMCR register fields */ 719 #define RCC_R2SEMCR_SEM_MUTEX BIT(0) 720 #define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4) 721 #define RCC_R2SEMCR_SEMCID_SHIFT 4 722 723 /* RCC_R3CIDCFGR register fields */ 724 #define RCC_R3CIDCFGR_CFEN BIT(0) 725 #define RCC_R3CIDCFGR_SEM_EN BIT(1) 726 #define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) 727 #define RCC_R3CIDCFGR_SCID_SHIFT 4 728 #define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 729 #define RCC_R3CIDCFGR_SEMWLC_SHIFT 16 730 731 /* RCC_R3SEMCR register fields */ 732 #define RCC_R3SEMCR_SEM_MUTEX BIT(0) 733 #define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4) 734 #define RCC_R3SEMCR_SEMCID_SHIFT 4 735 736 /* RCC_R4CIDCFGR register fields */ 737 #define RCC_R4CIDCFGR_CFEN BIT(0) 738 #define RCC_R4CIDCFGR_SEM_EN BIT(1) 739 #define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) 740 #define RCC_R4CIDCFGR_SCID_SHIFT 4 741 #define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 742 #define RCC_R4CIDCFGR_SEMWLC_SHIFT 16 743 744 /* RCC_R4SEMCR register fields */ 745 #define RCC_R4SEMCR_SEM_MUTEX BIT(0) 746 #define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4) 747 #define RCC_R4SEMCR_SEMCID_SHIFT 4 748 749 /* RCC_R5CIDCFGR register fields */ 750 #define RCC_R5CIDCFGR_CFEN BIT(0) 751 #define RCC_R5CIDCFGR_SEM_EN BIT(1) 752 #define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) 753 #define RCC_R5CIDCFGR_SCID_SHIFT 4 754 #define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 755 #define RCC_R5CIDCFGR_SEMWLC_SHIFT 16 756 757 /* RCC_R5SEMCR register fields */ 758 #define RCC_R5SEMCR_SEM_MUTEX BIT(0) 759 #define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4) 760 #define RCC_R5SEMCR_SEMCID_SHIFT 4 761 762 /* RCC_R6CIDCFGR register fields */ 763 #define RCC_R6CIDCFGR_CFEN BIT(0) 764 #define RCC_R6CIDCFGR_SEM_EN BIT(1) 765 #define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) 766 #define RCC_R6CIDCFGR_SCID_SHIFT 4 767 #define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 768 #define RCC_R6CIDCFGR_SEMWLC_SHIFT 16 769 770 /* RCC_R6SEMCR register fields */ 771 #define RCC_R6SEMCR_SEM_MUTEX BIT(0) 772 #define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4) 773 #define RCC_R6SEMCR_SEMCID_SHIFT 4 774 775 /* RCC_R7CIDCFGR register fields */ 776 #define RCC_R7CIDCFGR_CFEN BIT(0) 777 #define RCC_R7CIDCFGR_SEM_EN BIT(1) 778 #define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4) 779 #define RCC_R7CIDCFGR_SCID_SHIFT 4 780 #define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 781 #define RCC_R7CIDCFGR_SEMWLC_SHIFT 16 782 783 /* RCC_R7SEMCR register fields */ 784 #define RCC_R7SEMCR_SEM_MUTEX BIT(0) 785 #define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4) 786 #define RCC_R7SEMCR_SEMCID_SHIFT 4 787 788 /* RCC_R8CIDCFGR register fields */ 789 #define RCC_R8CIDCFGR_CFEN BIT(0) 790 #define RCC_R8CIDCFGR_SEM_EN BIT(1) 791 #define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4) 792 #define RCC_R8CIDCFGR_SCID_SHIFT 4 793 #define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 794 #define RCC_R8CIDCFGR_SEMWLC_SHIFT 16 795 796 /* RCC_R8SEMCR register fields */ 797 #define RCC_R8SEMCR_SEM_MUTEX BIT(0) 798 #define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4) 799 #define RCC_R8SEMCR_SEMCID_SHIFT 4 800 801 /* RCC_R9CIDCFGR register fields */ 802 #define RCC_R9CIDCFGR_CFEN BIT(0) 803 #define RCC_R9CIDCFGR_SEM_EN BIT(1) 804 #define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4) 805 #define RCC_R9CIDCFGR_SCID_SHIFT 4 806 #define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 807 #define RCC_R9CIDCFGR_SEMWLC_SHIFT 16 808 809 /* RCC_R9SEMCR register fields */ 810 #define RCC_R9SEMCR_SEM_MUTEX BIT(0) 811 #define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4) 812 #define RCC_R9SEMCR_SEMCID_SHIFT 4 813 814 /* RCC_R10CIDCFGR register fields */ 815 #define RCC_R10CIDCFGR_CFEN BIT(0) 816 #define RCC_R10CIDCFGR_SEM_EN BIT(1) 817 #define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4) 818 #define RCC_R10CIDCFGR_SCID_SHIFT 4 819 #define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 820 #define RCC_R10CIDCFGR_SEMWLC_SHIFT 16 821 822 /* RCC_R10SEMCR register fields */ 823 #define RCC_R10SEMCR_SEM_MUTEX BIT(0) 824 #define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4) 825 #define RCC_R10SEMCR_SEMCID_SHIFT 4 826 827 /* RCC_R11CIDCFGR register fields */ 828 #define RCC_R11CIDCFGR_CFEN BIT(0) 829 #define RCC_R11CIDCFGR_SEM_EN BIT(1) 830 #define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4) 831 #define RCC_R11CIDCFGR_SCID_SHIFT 4 832 #define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 833 #define RCC_R11CIDCFGR_SEMWLC_SHIFT 16 834 835 /* RCC_R11SEMCR register fields */ 836 #define RCC_R11SEMCR_SEM_MUTEX BIT(0) 837 #define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4) 838 #define RCC_R11SEMCR_SEMCID_SHIFT 4 839 840 /* RCC_R12CIDCFGR register fields */ 841 #define RCC_R12CIDCFGR_CFEN BIT(0) 842 #define RCC_R12CIDCFGR_SEM_EN BIT(1) 843 #define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4) 844 #define RCC_R12CIDCFGR_SCID_SHIFT 4 845 #define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 846 #define RCC_R12CIDCFGR_SEMWLC_SHIFT 16 847 848 /* RCC_R12SEMCR register fields */ 849 #define RCC_R12SEMCR_SEM_MUTEX BIT(0) 850 #define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4) 851 #define RCC_R12SEMCR_SEMCID_SHIFT 4 852 853 /* RCC_R13CIDCFGR register fields */ 854 #define RCC_R13CIDCFGR_CFEN BIT(0) 855 #define RCC_R13CIDCFGR_SEM_EN BIT(1) 856 #define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4) 857 #define RCC_R13CIDCFGR_SCID_SHIFT 4 858 #define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 859 #define RCC_R13CIDCFGR_SEMWLC_SHIFT 16 860 861 /* RCC_R13SEMCR register fields */ 862 #define RCC_R13SEMCR_SEM_MUTEX BIT(0) 863 #define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4) 864 #define RCC_R13SEMCR_SEMCID_SHIFT 4 865 866 /* RCC_R14CIDCFGR register fields */ 867 #define RCC_R14CIDCFGR_CFEN BIT(0) 868 #define RCC_R14CIDCFGR_SEM_EN BIT(1) 869 #define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4) 870 #define RCC_R14CIDCFGR_SCID_SHIFT 4 871 #define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 872 #define RCC_R14CIDCFGR_SEMWLC_SHIFT 16 873 874 /* RCC_R14SEMCR register fields */ 875 #define RCC_R14SEMCR_SEM_MUTEX BIT(0) 876 #define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4) 877 #define RCC_R14SEMCR_SEMCID_SHIFT 4 878 879 /* RCC_R15CIDCFGR register fields */ 880 #define RCC_R15CIDCFGR_CFEN BIT(0) 881 #define RCC_R15CIDCFGR_SEM_EN BIT(1) 882 #define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4) 883 #define RCC_R15CIDCFGR_SCID_SHIFT 4 884 #define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 885 #define RCC_R15CIDCFGR_SEMWLC_SHIFT 16 886 887 /* RCC_R15SEMCR register fields */ 888 #define RCC_R15SEMCR_SEM_MUTEX BIT(0) 889 #define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4) 890 #define RCC_R15SEMCR_SEMCID_SHIFT 4 891 892 /* RCC_R16CIDCFGR register fields */ 893 #define RCC_R16CIDCFGR_CFEN BIT(0) 894 #define RCC_R16CIDCFGR_SEM_EN BIT(1) 895 #define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4) 896 #define RCC_R16CIDCFGR_SCID_SHIFT 4 897 #define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 898 #define RCC_R16CIDCFGR_SEMWLC_SHIFT 16 899 900 /* RCC_R16SEMCR register fields */ 901 #define RCC_R16SEMCR_SEM_MUTEX BIT(0) 902 #define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4) 903 #define RCC_R16SEMCR_SEMCID_SHIFT 4 904 905 /* RCC_R17CIDCFGR register fields */ 906 #define RCC_R17CIDCFGR_CFEN BIT(0) 907 #define RCC_R17CIDCFGR_SEM_EN BIT(1) 908 #define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4) 909 #define RCC_R17CIDCFGR_SCID_SHIFT 4 910 #define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 911 #define RCC_R17CIDCFGR_SEMWLC_SHIFT 16 912 913 /* RCC_R17SEMCR register fields */ 914 #define RCC_R17SEMCR_SEM_MUTEX BIT(0) 915 #define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4) 916 #define RCC_R17SEMCR_SEMCID_SHIFT 4 917 918 /* RCC_R18CIDCFGR register fields */ 919 #define RCC_R18CIDCFGR_CFEN BIT(0) 920 #define RCC_R18CIDCFGR_SEM_EN BIT(1) 921 #define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4) 922 #define RCC_R18CIDCFGR_SCID_SHIFT 4 923 #define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 924 #define RCC_R18CIDCFGR_SEMWLC_SHIFT 16 925 926 /* RCC_R18SEMCR register fields */ 927 #define RCC_R18SEMCR_SEM_MUTEX BIT(0) 928 #define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4) 929 #define RCC_R18SEMCR_SEMCID_SHIFT 4 930 931 /* RCC_R19CIDCFGR register fields */ 932 #define RCC_R19CIDCFGR_CFEN BIT(0) 933 #define RCC_R19CIDCFGR_SEM_EN BIT(1) 934 #define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4) 935 #define RCC_R19CIDCFGR_SCID_SHIFT 4 936 #define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 937 #define RCC_R19CIDCFGR_SEMWLC_SHIFT 16 938 939 /* RCC_R19SEMCR register fields */ 940 #define RCC_R19SEMCR_SEM_MUTEX BIT(0) 941 #define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4) 942 #define RCC_R19SEMCR_SEMCID_SHIFT 4 943 944 /* RCC_R20CIDCFGR register fields */ 945 #define RCC_R20CIDCFGR_CFEN BIT(0) 946 #define RCC_R20CIDCFGR_SEM_EN BIT(1) 947 #define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4) 948 #define RCC_R20CIDCFGR_SCID_SHIFT 4 949 #define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 950 #define RCC_R20CIDCFGR_SEMWLC_SHIFT 16 951 952 /* RCC_R20SEMCR register fields */ 953 #define RCC_R20SEMCR_SEM_MUTEX BIT(0) 954 #define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4) 955 #define RCC_R20SEMCR_SEMCID_SHIFT 4 956 957 /* RCC_R21CIDCFGR register fields */ 958 #define RCC_R21CIDCFGR_CFEN BIT(0) 959 #define RCC_R21CIDCFGR_SEM_EN BIT(1) 960 #define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4) 961 #define RCC_R21CIDCFGR_SCID_SHIFT 4 962 #define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 963 #define RCC_R21CIDCFGR_SEMWLC_SHIFT 16 964 965 /* RCC_R21SEMCR register fields */ 966 #define RCC_R21SEMCR_SEM_MUTEX BIT(0) 967 #define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4) 968 #define RCC_R21SEMCR_SEMCID_SHIFT 4 969 970 /* RCC_R22CIDCFGR register fields */ 971 #define RCC_R22CIDCFGR_CFEN BIT(0) 972 #define RCC_R22CIDCFGR_SEM_EN BIT(1) 973 #define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4) 974 #define RCC_R22CIDCFGR_SCID_SHIFT 4 975 #define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 976 #define RCC_R22CIDCFGR_SEMWLC_SHIFT 16 977 978 /* RCC_R22SEMCR register fields */ 979 #define RCC_R22SEMCR_SEM_MUTEX BIT(0) 980 #define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4) 981 #define RCC_R22SEMCR_SEMCID_SHIFT 4 982 983 /* RCC_R23CIDCFGR register fields */ 984 #define RCC_R23CIDCFGR_CFEN BIT(0) 985 #define RCC_R23CIDCFGR_SEM_EN BIT(1) 986 #define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4) 987 #define RCC_R23CIDCFGR_SCID_SHIFT 4 988 #define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 989 #define RCC_R23CIDCFGR_SEMWLC_SHIFT 16 990 991 /* RCC_R23SEMCR register fields */ 992 #define RCC_R23SEMCR_SEM_MUTEX BIT(0) 993 #define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4) 994 #define RCC_R23SEMCR_SEMCID_SHIFT 4 995 996 /* RCC_R24CIDCFGR register fields */ 997 #define RCC_R24CIDCFGR_CFEN BIT(0) 998 #define RCC_R24CIDCFGR_SEM_EN BIT(1) 999 #define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1000 #define RCC_R24CIDCFGR_SCID_SHIFT 4 1001 #define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1002 #define RCC_R24CIDCFGR_SEMWLC_SHIFT 16 1003 1004 /* RCC_R24SEMCR register fields */ 1005 #define RCC_R24SEMCR_SEM_MUTEX BIT(0) 1006 #define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1007 #define RCC_R24SEMCR_SEMCID_SHIFT 4 1008 1009 /* RCC_R25CIDCFGR register fields */ 1010 #define RCC_R25CIDCFGR_CFEN BIT(0) 1011 #define RCC_R25CIDCFGR_SEM_EN BIT(1) 1012 #define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1013 #define RCC_R25CIDCFGR_SCID_SHIFT 4 1014 #define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1015 #define RCC_R25CIDCFGR_SEMWLC_SHIFT 16 1016 1017 /* RCC_R25SEMCR register fields */ 1018 #define RCC_R25SEMCR_SEM_MUTEX BIT(0) 1019 #define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1020 #define RCC_R25SEMCR_SEMCID_SHIFT 4 1021 1022 /* RCC_R26CIDCFGR register fields */ 1023 #define RCC_R26CIDCFGR_CFEN BIT(0) 1024 #define RCC_R26CIDCFGR_SEM_EN BIT(1) 1025 #define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1026 #define RCC_R26CIDCFGR_SCID_SHIFT 4 1027 #define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1028 #define RCC_R26CIDCFGR_SEMWLC_SHIFT 16 1029 1030 /* RCC_R26SEMCR register fields */ 1031 #define RCC_R26SEMCR_SEM_MUTEX BIT(0) 1032 #define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1033 #define RCC_R26SEMCR_SEMCID_SHIFT 4 1034 1035 /* RCC_R27CIDCFGR register fields */ 1036 #define RCC_R27CIDCFGR_CFEN BIT(0) 1037 #define RCC_R27CIDCFGR_SEM_EN BIT(1) 1038 #define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1039 #define RCC_R27CIDCFGR_SCID_SHIFT 4 1040 #define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1041 #define RCC_R27CIDCFGR_SEMWLC_SHIFT 16 1042 1043 /* RCC_R27SEMCR register fields */ 1044 #define RCC_R27SEMCR_SEM_MUTEX BIT(0) 1045 #define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1046 #define RCC_R27SEMCR_SEMCID_SHIFT 4 1047 1048 /* RCC_R28CIDCFGR register fields */ 1049 #define RCC_R28CIDCFGR_CFEN BIT(0) 1050 #define RCC_R28CIDCFGR_SEM_EN BIT(1) 1051 #define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1052 #define RCC_R28CIDCFGR_SCID_SHIFT 4 1053 #define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1054 #define RCC_R28CIDCFGR_SEMWLC_SHIFT 16 1055 1056 /* RCC_R28SEMCR register fields */ 1057 #define RCC_R28SEMCR_SEM_MUTEX BIT(0) 1058 #define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1059 #define RCC_R28SEMCR_SEMCID_SHIFT 4 1060 1061 /* RCC_R29CIDCFGR register fields */ 1062 #define RCC_R29CIDCFGR_CFEN BIT(0) 1063 #define RCC_R29CIDCFGR_SEM_EN BIT(1) 1064 #define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1065 #define RCC_R29CIDCFGR_SCID_SHIFT 4 1066 #define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1067 #define RCC_R29CIDCFGR_SEMWLC_SHIFT 16 1068 1069 /* RCC_R29SEMCR register fields */ 1070 #define RCC_R29SEMCR_SEM_MUTEX BIT(0) 1071 #define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1072 #define RCC_R29SEMCR_SEMCID_SHIFT 4 1073 1074 /* RCC_R30CIDCFGR register fields */ 1075 #define RCC_R30CIDCFGR_CFEN BIT(0) 1076 #define RCC_R30CIDCFGR_SEM_EN BIT(1) 1077 #define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1078 #define RCC_R30CIDCFGR_SCID_SHIFT 4 1079 #define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1080 #define RCC_R30CIDCFGR_SEMWLC_SHIFT 16 1081 1082 /* RCC_R30SEMCR register fields */ 1083 #define RCC_R30SEMCR_SEM_MUTEX BIT(0) 1084 #define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1085 #define RCC_R30SEMCR_SEMCID_SHIFT 4 1086 1087 /* RCC_R31CIDCFGR register fields */ 1088 #define RCC_R31CIDCFGR_CFEN BIT(0) 1089 #define RCC_R31CIDCFGR_SEM_EN BIT(1) 1090 #define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1091 #define RCC_R31CIDCFGR_SCID_SHIFT 4 1092 #define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1093 #define RCC_R31CIDCFGR_SEMWLC_SHIFT 16 1094 1095 /* RCC_R31SEMCR register fields */ 1096 #define RCC_R31SEMCR_SEM_MUTEX BIT(0) 1097 #define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1098 #define RCC_R31SEMCR_SEMCID_SHIFT 4 1099 1100 /* RCC_R32CIDCFGR register fields */ 1101 #define RCC_R32CIDCFGR_CFEN BIT(0) 1102 #define RCC_R32CIDCFGR_SEM_EN BIT(1) 1103 #define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1104 #define RCC_R32CIDCFGR_SCID_SHIFT 4 1105 #define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1106 #define RCC_R32CIDCFGR_SEMWLC_SHIFT 16 1107 1108 /* RCC_R32SEMCR register fields */ 1109 #define RCC_R32SEMCR_SEM_MUTEX BIT(0) 1110 #define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1111 #define RCC_R32SEMCR_SEMCID_SHIFT 4 1112 1113 /* RCC_R33CIDCFGR register fields */ 1114 #define RCC_R33CIDCFGR_CFEN BIT(0) 1115 #define RCC_R33CIDCFGR_SEM_EN BIT(1) 1116 #define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1117 #define RCC_R33CIDCFGR_SCID_SHIFT 4 1118 #define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1119 #define RCC_R33CIDCFGR_SEMWLC_SHIFT 16 1120 1121 /* RCC_R33SEMCR register fields */ 1122 #define RCC_R33SEMCR_SEM_MUTEX BIT(0) 1123 #define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1124 #define RCC_R33SEMCR_SEMCID_SHIFT 4 1125 1126 /* RCC_R34CIDCFGR register fields */ 1127 #define RCC_R34CIDCFGR_CFEN BIT(0) 1128 #define RCC_R34CIDCFGR_SEM_EN BIT(1) 1129 #define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1130 #define RCC_R34CIDCFGR_SCID_SHIFT 4 1131 #define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1132 #define RCC_R34CIDCFGR_SEMWLC_SHIFT 16 1133 1134 /* RCC_R34SEMCR register fields */ 1135 #define RCC_R34SEMCR_SEM_MUTEX BIT(0) 1136 #define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1137 #define RCC_R34SEMCR_SEMCID_SHIFT 4 1138 1139 /* RCC_R35CIDCFGR register fields */ 1140 #define RCC_R35CIDCFGR_CFEN BIT(0) 1141 #define RCC_R35CIDCFGR_SEM_EN BIT(1) 1142 #define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1143 #define RCC_R35CIDCFGR_SCID_SHIFT 4 1144 #define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1145 #define RCC_R35CIDCFGR_SEMWLC_SHIFT 16 1146 1147 /* RCC_R35SEMCR register fields */ 1148 #define RCC_R35SEMCR_SEM_MUTEX BIT(0) 1149 #define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1150 #define RCC_R35SEMCR_SEMCID_SHIFT 4 1151 1152 /* RCC_R36CIDCFGR register fields */ 1153 #define RCC_R36CIDCFGR_CFEN BIT(0) 1154 #define RCC_R36CIDCFGR_SEM_EN BIT(1) 1155 #define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1156 #define RCC_R36CIDCFGR_SCID_SHIFT 4 1157 #define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1158 #define RCC_R36CIDCFGR_SEMWLC_SHIFT 16 1159 1160 /* RCC_R36SEMCR register fields */ 1161 #define RCC_R36SEMCR_SEM_MUTEX BIT(0) 1162 #define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1163 #define RCC_R36SEMCR_SEMCID_SHIFT 4 1164 1165 /* RCC_R37CIDCFGR register fields */ 1166 #define RCC_R37CIDCFGR_CFEN BIT(0) 1167 #define RCC_R37CIDCFGR_SEM_EN BIT(1) 1168 #define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1169 #define RCC_R37CIDCFGR_SCID_SHIFT 4 1170 #define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1171 #define RCC_R37CIDCFGR_SEMWLC_SHIFT 16 1172 1173 /* RCC_R37SEMCR register fields */ 1174 #define RCC_R37SEMCR_SEM_MUTEX BIT(0) 1175 #define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1176 #define RCC_R37SEMCR_SEMCID_SHIFT 4 1177 1178 /* RCC_R38CIDCFGR register fields */ 1179 #define RCC_R38CIDCFGR_CFEN BIT(0) 1180 #define RCC_R38CIDCFGR_SEM_EN BIT(1) 1181 #define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1182 #define RCC_R38CIDCFGR_SCID_SHIFT 4 1183 #define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1184 #define RCC_R38CIDCFGR_SEMWLC_SHIFT 16 1185 1186 /* RCC_R38SEMCR register fields */ 1187 #define RCC_R38SEMCR_SEM_MUTEX BIT(0) 1188 #define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1189 #define RCC_R38SEMCR_SEMCID_SHIFT 4 1190 1191 /* RCC_R39CIDCFGR register fields */ 1192 #define RCC_R39CIDCFGR_CFEN BIT(0) 1193 #define RCC_R39CIDCFGR_SEM_EN BIT(1) 1194 #define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1195 #define RCC_R39CIDCFGR_SCID_SHIFT 4 1196 #define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1197 #define RCC_R39CIDCFGR_SEMWLC_SHIFT 16 1198 1199 /* RCC_R39SEMCR register fields */ 1200 #define RCC_R39SEMCR_SEM_MUTEX BIT(0) 1201 #define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1202 #define RCC_R39SEMCR_SEMCID_SHIFT 4 1203 1204 /* RCC_R40CIDCFGR register fields */ 1205 #define RCC_R40CIDCFGR_CFEN BIT(0) 1206 #define RCC_R40CIDCFGR_SEM_EN BIT(1) 1207 #define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1208 #define RCC_R40CIDCFGR_SCID_SHIFT 4 1209 #define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1210 #define RCC_R40CIDCFGR_SEMWLC_SHIFT 16 1211 1212 /* RCC_R40SEMCR register fields */ 1213 #define RCC_R40SEMCR_SEM_MUTEX BIT(0) 1214 #define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1215 #define RCC_R40SEMCR_SEMCID_SHIFT 4 1216 1217 /* RCC_R41CIDCFGR register fields */ 1218 #define RCC_R41CIDCFGR_CFEN BIT(0) 1219 #define RCC_R41CIDCFGR_SEM_EN BIT(1) 1220 #define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1221 #define RCC_R41CIDCFGR_SCID_SHIFT 4 1222 #define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1223 #define RCC_R41CIDCFGR_SEMWLC_SHIFT 16 1224 1225 /* RCC_R41SEMCR register fields */ 1226 #define RCC_R41SEMCR_SEM_MUTEX BIT(0) 1227 #define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1228 #define RCC_R41SEMCR_SEMCID_SHIFT 4 1229 1230 /* RCC_R42CIDCFGR register fields */ 1231 #define RCC_R42CIDCFGR_CFEN BIT(0) 1232 #define RCC_R42CIDCFGR_SEM_EN BIT(1) 1233 #define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1234 #define RCC_R42CIDCFGR_SCID_SHIFT 4 1235 #define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1236 #define RCC_R42CIDCFGR_SEMWLC_SHIFT 16 1237 1238 /* RCC_R42SEMCR register fields */ 1239 #define RCC_R42SEMCR_SEM_MUTEX BIT(0) 1240 #define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1241 #define RCC_R42SEMCR_SEMCID_SHIFT 4 1242 1243 /* RCC_R43CIDCFGR register fields */ 1244 #define RCC_R43CIDCFGR_CFEN BIT(0) 1245 #define RCC_R43CIDCFGR_SEM_EN BIT(1) 1246 #define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1247 #define RCC_R43CIDCFGR_SCID_SHIFT 4 1248 #define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1249 #define RCC_R43CIDCFGR_SEMWLC_SHIFT 16 1250 1251 /* RCC_R43SEMCR register fields */ 1252 #define RCC_R43SEMCR_SEM_MUTEX BIT(0) 1253 #define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1254 #define RCC_R43SEMCR_SEMCID_SHIFT 4 1255 1256 /* RCC_R44CIDCFGR register fields */ 1257 #define RCC_R44CIDCFGR_CFEN BIT(0) 1258 #define RCC_R44CIDCFGR_SEM_EN BIT(1) 1259 #define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1260 #define RCC_R44CIDCFGR_SCID_SHIFT 4 1261 #define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1262 #define RCC_R44CIDCFGR_SEMWLC_SHIFT 16 1263 1264 /* RCC_R44SEMCR register fields */ 1265 #define RCC_R44SEMCR_SEM_MUTEX BIT(0) 1266 #define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1267 #define RCC_R44SEMCR_SEMCID_SHIFT 4 1268 1269 /* RCC_R45CIDCFGR register fields */ 1270 #define RCC_R45CIDCFGR_CFEN BIT(0) 1271 #define RCC_R45CIDCFGR_SEM_EN BIT(1) 1272 #define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1273 #define RCC_R45CIDCFGR_SCID_SHIFT 4 1274 #define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1275 #define RCC_R45CIDCFGR_SEMWLC_SHIFT 16 1276 1277 /* RCC_R45SEMCR register fields */ 1278 #define RCC_R45SEMCR_SEM_MUTEX BIT(0) 1279 #define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1280 #define RCC_R45SEMCR_SEMCID_SHIFT 4 1281 1282 /* RCC_R46CIDCFGR register fields */ 1283 #define RCC_R46CIDCFGR_CFEN BIT(0) 1284 #define RCC_R46CIDCFGR_SEM_EN BIT(1) 1285 #define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1286 #define RCC_R46CIDCFGR_SCID_SHIFT 4 1287 #define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1288 #define RCC_R46CIDCFGR_SEMWLC_SHIFT 16 1289 1290 /* RCC_R46SEMCR register fields */ 1291 #define RCC_R46SEMCR_SEM_MUTEX BIT(0) 1292 #define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1293 #define RCC_R46SEMCR_SEMCID_SHIFT 4 1294 1295 /* RCC_R47CIDCFGR register fields */ 1296 #define RCC_R47CIDCFGR_CFEN BIT(0) 1297 #define RCC_R47CIDCFGR_SEM_EN BIT(1) 1298 #define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1299 #define RCC_R47CIDCFGR_SCID_SHIFT 4 1300 #define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1301 #define RCC_R47CIDCFGR_SEMWLC_SHIFT 16 1302 1303 /* RCC_R47SEMCR register fields */ 1304 #define RCC_R47SEMCR_SEM_MUTEX BIT(0) 1305 #define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1306 #define RCC_R47SEMCR_SEMCID_SHIFT 4 1307 1308 /* RCC_R48CIDCFGR register fields */ 1309 #define RCC_R48CIDCFGR_CFEN BIT(0) 1310 #define RCC_R48CIDCFGR_SEM_EN BIT(1) 1311 #define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1312 #define RCC_R48CIDCFGR_SCID_SHIFT 4 1313 #define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1314 #define RCC_R48CIDCFGR_SEMWLC_SHIFT 16 1315 1316 /* RCC_R48SEMCR register fields */ 1317 #define RCC_R48SEMCR_SEM_MUTEX BIT(0) 1318 #define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1319 #define RCC_R48SEMCR_SEMCID_SHIFT 4 1320 1321 /* RCC_R49CIDCFGR register fields */ 1322 #define RCC_R49CIDCFGR_CFEN BIT(0) 1323 #define RCC_R49CIDCFGR_SEM_EN BIT(1) 1324 #define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1325 #define RCC_R49CIDCFGR_SCID_SHIFT 4 1326 #define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1327 #define RCC_R49CIDCFGR_SEMWLC_SHIFT 16 1328 1329 /* RCC_R49SEMCR register fields */ 1330 #define RCC_R49SEMCR_SEM_MUTEX BIT(0) 1331 #define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1332 #define RCC_R49SEMCR_SEMCID_SHIFT 4 1333 1334 /* RCC_R50CIDCFGR register fields */ 1335 #define RCC_R50CIDCFGR_CFEN BIT(0) 1336 #define RCC_R50CIDCFGR_SEM_EN BIT(1) 1337 #define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1338 #define RCC_R50CIDCFGR_SCID_SHIFT 4 1339 #define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1340 #define RCC_R50CIDCFGR_SEMWLC_SHIFT 16 1341 1342 /* RCC_R50SEMCR register fields */ 1343 #define RCC_R50SEMCR_SEM_MUTEX BIT(0) 1344 #define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1345 #define RCC_R50SEMCR_SEMCID_SHIFT 4 1346 1347 /* RCC_R51CIDCFGR register fields */ 1348 #define RCC_R51CIDCFGR_CFEN BIT(0) 1349 #define RCC_R51CIDCFGR_SEM_EN BIT(1) 1350 #define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1351 #define RCC_R51CIDCFGR_SCID_SHIFT 4 1352 #define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1353 #define RCC_R51CIDCFGR_SEMWLC_SHIFT 16 1354 1355 /* RCC_R51SEMCR register fields */ 1356 #define RCC_R51SEMCR_SEM_MUTEX BIT(0) 1357 #define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1358 #define RCC_R51SEMCR_SEMCID_SHIFT 4 1359 1360 /* RCC_R52CIDCFGR register fields */ 1361 #define RCC_R52CIDCFGR_CFEN BIT(0) 1362 #define RCC_R52CIDCFGR_SEM_EN BIT(1) 1363 #define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1364 #define RCC_R52CIDCFGR_SCID_SHIFT 4 1365 #define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1366 #define RCC_R52CIDCFGR_SEMWLC_SHIFT 16 1367 1368 /* RCC_R52SEMCR register fields */ 1369 #define RCC_R52SEMCR_SEM_MUTEX BIT(0) 1370 #define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1371 #define RCC_R52SEMCR_SEMCID_SHIFT 4 1372 1373 /* RCC_R53CIDCFGR register fields */ 1374 #define RCC_R53CIDCFGR_CFEN BIT(0) 1375 #define RCC_R53CIDCFGR_SEM_EN BIT(1) 1376 #define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1377 #define RCC_R53CIDCFGR_SCID_SHIFT 4 1378 #define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1379 #define RCC_R53CIDCFGR_SEMWLC_SHIFT 16 1380 1381 /* RCC_R53SEMCR register fields */ 1382 #define RCC_R53SEMCR_SEM_MUTEX BIT(0) 1383 #define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1384 #define RCC_R53SEMCR_SEMCID_SHIFT 4 1385 1386 /* RCC_R54CIDCFGR register fields */ 1387 #define RCC_R54CIDCFGR_CFEN BIT(0) 1388 #define RCC_R54CIDCFGR_SEM_EN BIT(1) 1389 #define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1390 #define RCC_R54CIDCFGR_SCID_SHIFT 4 1391 #define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1392 #define RCC_R54CIDCFGR_SEMWLC_SHIFT 16 1393 1394 /* RCC_R54SEMCR register fields */ 1395 #define RCC_R54SEMCR_SEM_MUTEX BIT(0) 1396 #define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1397 #define RCC_R54SEMCR_SEMCID_SHIFT 4 1398 1399 /* RCC_R55CIDCFGR register fields */ 1400 #define RCC_R55CIDCFGR_CFEN BIT(0) 1401 #define RCC_R55CIDCFGR_SEM_EN BIT(1) 1402 #define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1403 #define RCC_R55CIDCFGR_SCID_SHIFT 4 1404 #define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1405 #define RCC_R55CIDCFGR_SEMWLC_SHIFT 16 1406 1407 /* RCC_R55SEMCR register fields */ 1408 #define RCC_R55SEMCR_SEM_MUTEX BIT(0) 1409 #define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1410 #define RCC_R55SEMCR_SEMCID_SHIFT 4 1411 1412 /* RCC_R56CIDCFGR register fields */ 1413 #define RCC_R56CIDCFGR_CFEN BIT(0) 1414 #define RCC_R56CIDCFGR_SEM_EN BIT(1) 1415 #define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1416 #define RCC_R56CIDCFGR_SCID_SHIFT 4 1417 #define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1418 #define RCC_R56CIDCFGR_SEMWLC_SHIFT 16 1419 1420 /* RCC_R56SEMCR register fields */ 1421 #define RCC_R56SEMCR_SEM_MUTEX BIT(0) 1422 #define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1423 #define RCC_R56SEMCR_SEMCID_SHIFT 4 1424 1425 /* RCC_R57CIDCFGR register fields */ 1426 #define RCC_R57CIDCFGR_CFEN BIT(0) 1427 #define RCC_R57CIDCFGR_SEM_EN BIT(1) 1428 #define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1429 #define RCC_R57CIDCFGR_SCID_SHIFT 4 1430 #define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1431 #define RCC_R57CIDCFGR_SEMWLC_SHIFT 16 1432 1433 /* RCC_R57SEMCR register fields */ 1434 #define RCC_R57SEMCR_SEM_MUTEX BIT(0) 1435 #define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1436 #define RCC_R57SEMCR_SEMCID_SHIFT 4 1437 1438 /* RCC_R58CIDCFGR register fields */ 1439 #define RCC_R58CIDCFGR_CFEN BIT(0) 1440 #define RCC_R58CIDCFGR_SEM_EN BIT(1) 1441 #define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1442 #define RCC_R58CIDCFGR_SCID_SHIFT 4 1443 #define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1444 #define RCC_R58CIDCFGR_SEMWLC_SHIFT 16 1445 1446 /* RCC_R58SEMCR register fields */ 1447 #define RCC_R58SEMCR_SEM_MUTEX BIT(0) 1448 #define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1449 #define RCC_R58SEMCR_SEMCID_SHIFT 4 1450 1451 /* RCC_R59CIDCFGR register fields */ 1452 #define RCC_R59CIDCFGR_CFEN BIT(0) 1453 #define RCC_R59CIDCFGR_SEM_EN BIT(1) 1454 #define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1455 #define RCC_R59CIDCFGR_SCID_SHIFT 4 1456 #define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1457 #define RCC_R59CIDCFGR_SEMWLC_SHIFT 16 1458 1459 /* RCC_R59SEMCR register fields */ 1460 #define RCC_R59SEMCR_SEM_MUTEX BIT(0) 1461 #define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1462 #define RCC_R59SEMCR_SEMCID_SHIFT 4 1463 1464 /* RCC_R60CIDCFGR register fields */ 1465 #define RCC_R60CIDCFGR_CFEN BIT(0) 1466 #define RCC_R60CIDCFGR_SEM_EN BIT(1) 1467 #define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1468 #define RCC_R60CIDCFGR_SCID_SHIFT 4 1469 #define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1470 #define RCC_R60CIDCFGR_SEMWLC_SHIFT 16 1471 1472 /* RCC_R60SEMCR register fields */ 1473 #define RCC_R60SEMCR_SEM_MUTEX BIT(0) 1474 #define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1475 #define RCC_R60SEMCR_SEMCID_SHIFT 4 1476 1477 /* RCC_R61CIDCFGR register fields */ 1478 #define RCC_R61CIDCFGR_CFEN BIT(0) 1479 #define RCC_R61CIDCFGR_SEM_EN BIT(1) 1480 #define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1481 #define RCC_R61CIDCFGR_SCID_SHIFT 4 1482 #define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1483 #define RCC_R61CIDCFGR_SEMWLC_SHIFT 16 1484 1485 /* RCC_R61SEMCR register fields */ 1486 #define RCC_R61SEMCR_SEM_MUTEX BIT(0) 1487 #define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1488 #define RCC_R61SEMCR_SEMCID_SHIFT 4 1489 1490 /* RCC_R62CIDCFGR register fields */ 1491 #define RCC_R62CIDCFGR_CFEN BIT(0) 1492 #define RCC_R62CIDCFGR_SEM_EN BIT(1) 1493 #define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1494 #define RCC_R62CIDCFGR_SCID_SHIFT 4 1495 #define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1496 #define RCC_R62CIDCFGR_SEMWLC_SHIFT 16 1497 1498 /* RCC_R62SEMCR register fields */ 1499 #define RCC_R62SEMCR_SEM_MUTEX BIT(0) 1500 #define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1501 #define RCC_R62SEMCR_SEMCID_SHIFT 4 1502 1503 /* RCC_R63CIDCFGR register fields */ 1504 #define RCC_R63CIDCFGR_CFEN BIT(0) 1505 #define RCC_R63CIDCFGR_SEM_EN BIT(1) 1506 #define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1507 #define RCC_R63CIDCFGR_SCID_SHIFT 4 1508 #define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1509 #define RCC_R63CIDCFGR_SEMWLC_SHIFT 16 1510 1511 /* RCC_R63SEMCR register fields */ 1512 #define RCC_R63SEMCR_SEM_MUTEX BIT(0) 1513 #define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1514 #define RCC_R63SEMCR_SEMCID_SHIFT 4 1515 1516 /* RCC_R64CIDCFGR register fields */ 1517 #define RCC_R64CIDCFGR_CFEN BIT(0) 1518 #define RCC_R64CIDCFGR_SEM_EN BIT(1) 1519 #define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1520 #define RCC_R64CIDCFGR_SCID_SHIFT 4 1521 #define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1522 #define RCC_R64CIDCFGR_SEMWLC_SHIFT 16 1523 1524 /* RCC_R64SEMCR register fields */ 1525 #define RCC_R64SEMCR_SEM_MUTEX BIT(0) 1526 #define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1527 #define RCC_R64SEMCR_SEMCID_SHIFT 4 1528 1529 /* RCC_R65CIDCFGR register fields */ 1530 #define RCC_R65CIDCFGR_CFEN BIT(0) 1531 #define RCC_R65CIDCFGR_SEM_EN BIT(1) 1532 #define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1533 #define RCC_R65CIDCFGR_SCID_SHIFT 4 1534 #define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1535 #define RCC_R65CIDCFGR_SEMWLC_SHIFT 16 1536 1537 /* RCC_R65SEMCR register fields */ 1538 #define RCC_R65SEMCR_SEM_MUTEX BIT(0) 1539 #define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1540 #define RCC_R65SEMCR_SEMCID_SHIFT 4 1541 1542 /* RCC_R66CIDCFGR register fields */ 1543 #define RCC_R66CIDCFGR_CFEN BIT(0) 1544 #define RCC_R66CIDCFGR_SEM_EN BIT(1) 1545 #define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1546 #define RCC_R66CIDCFGR_SCID_SHIFT 4 1547 #define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1548 #define RCC_R66CIDCFGR_SEMWLC_SHIFT 16 1549 1550 /* RCC_R66SEMCR register fields */ 1551 #define RCC_R66SEMCR_SEM_MUTEX BIT(0) 1552 #define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1553 #define RCC_R66SEMCR_SEMCID_SHIFT 4 1554 1555 /* RCC_R67CIDCFGR register fields */ 1556 #define RCC_R67CIDCFGR_CFEN BIT(0) 1557 #define RCC_R67CIDCFGR_SEM_EN BIT(1) 1558 #define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1559 #define RCC_R67CIDCFGR_SCID_SHIFT 4 1560 #define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1561 #define RCC_R67CIDCFGR_SEMWLC_SHIFT 16 1562 1563 /* RCC_R67SEMCR register fields */ 1564 #define RCC_R67SEMCR_SEM_MUTEX BIT(0) 1565 #define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1566 #define RCC_R67SEMCR_SEMCID_SHIFT 4 1567 1568 /* RCC_R68CIDCFGR register fields */ 1569 #define RCC_R68CIDCFGR_CFEN BIT(0) 1570 #define RCC_R68CIDCFGR_SEM_EN BIT(1) 1571 #define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1572 #define RCC_R68CIDCFGR_SCID_SHIFT 4 1573 #define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1574 #define RCC_R68CIDCFGR_SEMWLC_SHIFT 16 1575 1576 /* RCC_R68SEMCR register fields */ 1577 #define RCC_R68SEMCR_SEM_MUTEX BIT(0) 1578 #define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1579 #define RCC_R68SEMCR_SEMCID_SHIFT 4 1580 1581 /* RCC_R69CIDCFGR register fields */ 1582 #define RCC_R69CIDCFGR_CFEN BIT(0) 1583 #define RCC_R69CIDCFGR_SEM_EN BIT(1) 1584 #define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1585 #define RCC_R69CIDCFGR_SCID_SHIFT 4 1586 #define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1587 #define RCC_R69CIDCFGR_SEMWLC_SHIFT 16 1588 1589 /* RCC_R69SEMCR register fields */ 1590 #define RCC_R69SEMCR_SEM_MUTEX BIT(0) 1591 #define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1592 #define RCC_R69SEMCR_SEMCID_SHIFT 4 1593 1594 /* RCC_R70CIDCFGR register fields */ 1595 #define RCC_R70CIDCFGR_CFEN BIT(0) 1596 #define RCC_R70CIDCFGR_SEM_EN BIT(1) 1597 #define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1598 #define RCC_R70CIDCFGR_SCID_SHIFT 4 1599 #define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1600 #define RCC_R70CIDCFGR_SEMWLC_SHIFT 16 1601 1602 /* RCC_R70SEMCR register fields */ 1603 #define RCC_R70SEMCR_SEM_MUTEX BIT(0) 1604 #define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1605 #define RCC_R70SEMCR_SEMCID_SHIFT 4 1606 1607 /* RCC_R71CIDCFGR register fields */ 1608 #define RCC_R71CIDCFGR_CFEN BIT(0) 1609 #define RCC_R71CIDCFGR_SEM_EN BIT(1) 1610 #define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1611 #define RCC_R71CIDCFGR_SCID_SHIFT 4 1612 #define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1613 #define RCC_R71CIDCFGR_SEMWLC_SHIFT 16 1614 1615 /* RCC_R71SEMCR register fields */ 1616 #define RCC_R71SEMCR_SEM_MUTEX BIT(0) 1617 #define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1618 #define RCC_R71SEMCR_SEMCID_SHIFT 4 1619 1620 /* RCC_R72CIDCFGR register fields */ 1621 #define RCC_R72CIDCFGR_CFEN BIT(0) 1622 #define RCC_R72CIDCFGR_SEM_EN BIT(1) 1623 #define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1624 #define RCC_R72CIDCFGR_SCID_SHIFT 4 1625 #define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1626 #define RCC_R72CIDCFGR_SEMWLC_SHIFT 16 1627 1628 /* RCC_R72SEMCR register fields */ 1629 #define RCC_R72SEMCR_SEM_MUTEX BIT(0) 1630 #define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1631 #define RCC_R72SEMCR_SEMCID_SHIFT 4 1632 1633 /* RCC_R73CIDCFGR register fields */ 1634 #define RCC_R73CIDCFGR_CFEN BIT(0) 1635 #define RCC_R73CIDCFGR_SEM_EN BIT(1) 1636 #define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1637 #define RCC_R73CIDCFGR_SCID_SHIFT 4 1638 #define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1639 #define RCC_R73CIDCFGR_SEMWLC_SHIFT 16 1640 1641 /* RCC_R73SEMCR register fields */ 1642 #define RCC_R73SEMCR_SEM_MUTEX BIT(0) 1643 #define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1644 #define RCC_R73SEMCR_SEMCID_SHIFT 4 1645 1646 /* RCC_R74CIDCFGR register fields */ 1647 #define RCC_R74CIDCFGR_CFEN BIT(0) 1648 #define RCC_R74CIDCFGR_SEM_EN BIT(1) 1649 #define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1650 #define RCC_R74CIDCFGR_SCID_SHIFT 4 1651 #define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1652 #define RCC_R74CIDCFGR_SEMWLC_SHIFT 16 1653 1654 /* RCC_R74SEMCR register fields */ 1655 #define RCC_R74SEMCR_SEM_MUTEX BIT(0) 1656 #define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1657 #define RCC_R74SEMCR_SEMCID_SHIFT 4 1658 1659 /* RCC_R75CIDCFGR register fields */ 1660 #define RCC_R75CIDCFGR_CFEN BIT(0) 1661 #define RCC_R75CIDCFGR_SEM_EN BIT(1) 1662 #define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1663 #define RCC_R75CIDCFGR_SCID_SHIFT 4 1664 #define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1665 #define RCC_R75CIDCFGR_SEMWLC_SHIFT 16 1666 1667 /* RCC_R75SEMCR register fields */ 1668 #define RCC_R75SEMCR_SEM_MUTEX BIT(0) 1669 #define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1670 #define RCC_R75SEMCR_SEMCID_SHIFT 4 1671 1672 /* RCC_R76CIDCFGR register fields */ 1673 #define RCC_R76CIDCFGR_CFEN BIT(0) 1674 #define RCC_R76CIDCFGR_SEM_EN BIT(1) 1675 #define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1676 #define RCC_R76CIDCFGR_SCID_SHIFT 4 1677 #define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1678 #define RCC_R76CIDCFGR_SEMWLC_SHIFT 16 1679 1680 /* RCC_R76SEMCR register fields */ 1681 #define RCC_R76SEMCR_SEM_MUTEX BIT(0) 1682 #define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1683 #define RCC_R76SEMCR_SEMCID_SHIFT 4 1684 1685 /* RCC_R77CIDCFGR register fields */ 1686 #define RCC_R77CIDCFGR_CFEN BIT(0) 1687 #define RCC_R77CIDCFGR_SEM_EN BIT(1) 1688 #define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1689 #define RCC_R77CIDCFGR_SCID_SHIFT 4 1690 #define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1691 #define RCC_R77CIDCFGR_SEMWLC_SHIFT 16 1692 1693 /* RCC_R77SEMCR register fields */ 1694 #define RCC_R77SEMCR_SEM_MUTEX BIT(0) 1695 #define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1696 #define RCC_R77SEMCR_SEMCID_SHIFT 4 1697 1698 /* RCC_R78CIDCFGR register fields */ 1699 #define RCC_R78CIDCFGR_CFEN BIT(0) 1700 #define RCC_R78CIDCFGR_SEM_EN BIT(1) 1701 #define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1702 #define RCC_R78CIDCFGR_SCID_SHIFT 4 1703 #define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1704 #define RCC_R78CIDCFGR_SEMWLC_SHIFT 16 1705 1706 /* RCC_R78SEMCR register fields */ 1707 #define RCC_R78SEMCR_SEM_MUTEX BIT(0) 1708 #define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1709 #define RCC_R78SEMCR_SEMCID_SHIFT 4 1710 1711 /* RCC_R79CIDCFGR register fields */ 1712 #define RCC_R79CIDCFGR_CFEN BIT(0) 1713 #define RCC_R79CIDCFGR_SEM_EN BIT(1) 1714 #define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1715 #define RCC_R79CIDCFGR_SCID_SHIFT 4 1716 #define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1717 #define RCC_R79CIDCFGR_SEMWLC_SHIFT 16 1718 1719 /* RCC_R79SEMCR register fields */ 1720 #define RCC_R79SEMCR_SEM_MUTEX BIT(0) 1721 #define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1722 #define RCC_R79SEMCR_SEMCID_SHIFT 4 1723 1724 /* RCC_R80CIDCFGR register fields */ 1725 #define RCC_R80CIDCFGR_CFEN BIT(0) 1726 #define RCC_R80CIDCFGR_SEM_EN BIT(1) 1727 #define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1728 #define RCC_R80CIDCFGR_SCID_SHIFT 4 1729 #define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1730 #define RCC_R80CIDCFGR_SEMWLC_SHIFT 16 1731 1732 /* RCC_R80SEMCR register fields */ 1733 #define RCC_R80SEMCR_SEM_MUTEX BIT(0) 1734 #define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1735 #define RCC_R80SEMCR_SEMCID_SHIFT 4 1736 1737 /* RCC_R81CIDCFGR register fields */ 1738 #define RCC_R81CIDCFGR_CFEN BIT(0) 1739 #define RCC_R81CIDCFGR_SEM_EN BIT(1) 1740 #define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1741 #define RCC_R81CIDCFGR_SCID_SHIFT 4 1742 #define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1743 #define RCC_R81CIDCFGR_SEMWLC_SHIFT 16 1744 1745 /* RCC_R81SEMCR register fields */ 1746 #define RCC_R81SEMCR_SEM_MUTEX BIT(0) 1747 #define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1748 #define RCC_R81SEMCR_SEMCID_SHIFT 4 1749 1750 /* RCC_R82CIDCFGR register fields */ 1751 #define RCC_R82CIDCFGR_CFEN BIT(0) 1752 #define RCC_R82CIDCFGR_SEM_EN BIT(1) 1753 #define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1754 #define RCC_R82CIDCFGR_SCID_SHIFT 4 1755 #define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1756 #define RCC_R82CIDCFGR_SEMWLC_SHIFT 16 1757 1758 /* RCC_R82SEMCR register fields */ 1759 #define RCC_R82SEMCR_SEM_MUTEX BIT(0) 1760 #define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1761 #define RCC_R82SEMCR_SEMCID_SHIFT 4 1762 1763 /* RCC_R83CIDCFGR register fields */ 1764 #define RCC_R83CIDCFGR_CFEN BIT(0) 1765 #define RCC_R83CIDCFGR_SEM_EN BIT(1) 1766 #define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1767 #define RCC_R83CIDCFGR_SCID_SHIFT 4 1768 #define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1769 #define RCC_R83CIDCFGR_SEMWLC_SHIFT 16 1770 1771 /* RCC_R83SEMCR register fields */ 1772 #define RCC_R83SEMCR_SEM_MUTEX BIT(0) 1773 #define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1774 #define RCC_R83SEMCR_SEMCID_SHIFT 4 1775 1776 /* RCC_R84CIDCFGR register fields */ 1777 #define RCC_R84CIDCFGR_CFEN BIT(0) 1778 #define RCC_R84CIDCFGR_SEM_EN BIT(1) 1779 #define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1780 #define RCC_R84CIDCFGR_SCID_SHIFT 4 1781 #define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1782 #define RCC_R84CIDCFGR_SEMWLC_SHIFT 16 1783 1784 /* RCC_R84SEMCR register fields */ 1785 #define RCC_R84SEMCR_SEM_MUTEX BIT(0) 1786 #define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1787 #define RCC_R84SEMCR_SEMCID_SHIFT 4 1788 1789 /* RCC_R85CIDCFGR register fields */ 1790 #define RCC_R85CIDCFGR_CFEN BIT(0) 1791 #define RCC_R85CIDCFGR_SEM_EN BIT(1) 1792 #define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1793 #define RCC_R85CIDCFGR_SCID_SHIFT 4 1794 #define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1795 #define RCC_R85CIDCFGR_SEMWLC_SHIFT 16 1796 1797 /* RCC_R85SEMCR register fields */ 1798 #define RCC_R85SEMCR_SEM_MUTEX BIT(0) 1799 #define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1800 #define RCC_R85SEMCR_SEMCID_SHIFT 4 1801 1802 /* RCC_R86CIDCFGR register fields */ 1803 #define RCC_R86CIDCFGR_CFEN BIT(0) 1804 #define RCC_R86CIDCFGR_SEM_EN BIT(1) 1805 #define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1806 #define RCC_R86CIDCFGR_SCID_SHIFT 4 1807 #define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1808 #define RCC_R86CIDCFGR_SEMWLC_SHIFT 16 1809 1810 /* RCC_R86SEMCR register fields */ 1811 #define RCC_R86SEMCR_SEM_MUTEX BIT(0) 1812 #define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1813 #define RCC_R86SEMCR_SEMCID_SHIFT 4 1814 1815 /* RCC_R87CIDCFGR register fields */ 1816 #define RCC_R87CIDCFGR_CFEN BIT(0) 1817 #define RCC_R87CIDCFGR_SEM_EN BIT(1) 1818 #define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1819 #define RCC_R87CIDCFGR_SCID_SHIFT 4 1820 #define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1821 #define RCC_R87CIDCFGR_SEMWLC_SHIFT 16 1822 1823 /* RCC_R87SEMCR register fields */ 1824 #define RCC_R87SEMCR_SEM_MUTEX BIT(0) 1825 #define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1826 #define RCC_R87SEMCR_SEMCID_SHIFT 4 1827 1828 /* RCC_R88CIDCFGR register fields */ 1829 #define RCC_R88CIDCFGR_CFEN BIT(0) 1830 #define RCC_R88CIDCFGR_SEM_EN BIT(1) 1831 #define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1832 #define RCC_R88CIDCFGR_SCID_SHIFT 4 1833 #define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1834 #define RCC_R88CIDCFGR_SEMWLC_SHIFT 16 1835 1836 /* RCC_R88SEMCR register fields */ 1837 #define RCC_R88SEMCR_SEM_MUTEX BIT(0) 1838 #define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1839 #define RCC_R88SEMCR_SEMCID_SHIFT 4 1840 1841 /* RCC_R89CIDCFGR register fields */ 1842 #define RCC_R89CIDCFGR_CFEN BIT(0) 1843 #define RCC_R89CIDCFGR_SEM_EN BIT(1) 1844 #define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1845 #define RCC_R89CIDCFGR_SCID_SHIFT 4 1846 #define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1847 #define RCC_R89CIDCFGR_SEMWLC_SHIFT 16 1848 1849 /* RCC_R89SEMCR register fields */ 1850 #define RCC_R89SEMCR_SEM_MUTEX BIT(0) 1851 #define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1852 #define RCC_R89SEMCR_SEMCID_SHIFT 4 1853 1854 /* RCC_R90CIDCFGR register fields */ 1855 #define RCC_R90CIDCFGR_CFEN BIT(0) 1856 #define RCC_R90CIDCFGR_SEM_EN BIT(1) 1857 #define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1858 #define RCC_R90CIDCFGR_SCID_SHIFT 4 1859 #define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1860 #define RCC_R90CIDCFGR_SEMWLC_SHIFT 16 1861 1862 /* RCC_R90SEMCR register fields */ 1863 #define RCC_R90SEMCR_SEM_MUTEX BIT(0) 1864 #define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1865 #define RCC_R90SEMCR_SEMCID_SHIFT 4 1866 1867 /* RCC_R91CIDCFGR register fields */ 1868 #define RCC_R91CIDCFGR_CFEN BIT(0) 1869 #define RCC_R91CIDCFGR_SEM_EN BIT(1) 1870 #define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1871 #define RCC_R91CIDCFGR_SCID_SHIFT 4 1872 #define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1873 #define RCC_R91CIDCFGR_SEMWLC_SHIFT 16 1874 1875 /* RCC_R91SEMCR register fields */ 1876 #define RCC_R91SEMCR_SEM_MUTEX BIT(0) 1877 #define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1878 #define RCC_R91SEMCR_SEMCID_SHIFT 4 1879 1880 /* RCC_R92CIDCFGR register fields */ 1881 #define RCC_R92CIDCFGR_CFEN BIT(0) 1882 #define RCC_R92CIDCFGR_SEM_EN BIT(1) 1883 #define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1884 #define RCC_R92CIDCFGR_SCID_SHIFT 4 1885 #define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1886 #define RCC_R92CIDCFGR_SEMWLC_SHIFT 16 1887 1888 /* RCC_R92SEMCR register fields */ 1889 #define RCC_R92SEMCR_SEM_MUTEX BIT(0) 1890 #define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1891 #define RCC_R92SEMCR_SEMCID_SHIFT 4 1892 1893 /* RCC_R93CIDCFGR register fields */ 1894 #define RCC_R93CIDCFGR_CFEN BIT(0) 1895 #define RCC_R93CIDCFGR_SEM_EN BIT(1) 1896 #define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1897 #define RCC_R93CIDCFGR_SCID_SHIFT 4 1898 #define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1899 #define RCC_R93CIDCFGR_SEMWLC_SHIFT 16 1900 1901 /* RCC_R93SEMCR register fields */ 1902 #define RCC_R93SEMCR_SEM_MUTEX BIT(0) 1903 #define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1904 #define RCC_R93SEMCR_SEMCID_SHIFT 4 1905 1906 /* RCC_R94CIDCFGR register fields */ 1907 #define RCC_R94CIDCFGR_CFEN BIT(0) 1908 #define RCC_R94CIDCFGR_SEM_EN BIT(1) 1909 #define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1910 #define RCC_R94CIDCFGR_SCID_SHIFT 4 1911 #define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1912 #define RCC_R94CIDCFGR_SEMWLC_SHIFT 16 1913 1914 /* RCC_R94SEMCR register fields */ 1915 #define RCC_R94SEMCR_SEM_MUTEX BIT(0) 1916 #define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1917 #define RCC_R94SEMCR_SEMCID_SHIFT 4 1918 1919 /* RCC_R95CIDCFGR register fields */ 1920 #define RCC_R95CIDCFGR_CFEN BIT(0) 1921 #define RCC_R95CIDCFGR_SEM_EN BIT(1) 1922 #define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1923 #define RCC_R95CIDCFGR_SCID_SHIFT 4 1924 #define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1925 #define RCC_R95CIDCFGR_SEMWLC_SHIFT 16 1926 1927 /* RCC_R95SEMCR register fields */ 1928 #define RCC_R95SEMCR_SEM_MUTEX BIT(0) 1929 #define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1930 #define RCC_R95SEMCR_SEMCID_SHIFT 4 1931 1932 /* RCC_R96CIDCFGR register fields */ 1933 #define RCC_R96CIDCFGR_CFEN BIT(0) 1934 #define RCC_R96CIDCFGR_SEM_EN BIT(1) 1935 #define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1936 #define RCC_R96CIDCFGR_SCID_SHIFT 4 1937 #define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1938 #define RCC_R96CIDCFGR_SEMWLC_SHIFT 16 1939 1940 /* RCC_R96SEMCR register fields */ 1941 #define RCC_R96SEMCR_SEM_MUTEX BIT(0) 1942 #define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1943 #define RCC_R96SEMCR_SEMCID_SHIFT 4 1944 1945 /* RCC_R97CIDCFGR register fields */ 1946 #define RCC_R97CIDCFGR_CFEN BIT(0) 1947 #define RCC_R97CIDCFGR_SEM_EN BIT(1) 1948 #define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1949 #define RCC_R97CIDCFGR_SCID_SHIFT 4 1950 #define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1951 #define RCC_R97CIDCFGR_SEMWLC_SHIFT 16 1952 1953 /* RCC_R97SEMCR register fields */ 1954 #define RCC_R97SEMCR_SEM_MUTEX BIT(0) 1955 #define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1956 #define RCC_R97SEMCR_SEMCID_SHIFT 4 1957 1958 /* RCC_R98CIDCFGR register fields */ 1959 #define RCC_R98CIDCFGR_CFEN BIT(0) 1960 #define RCC_R98CIDCFGR_SEM_EN BIT(1) 1961 #define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1962 #define RCC_R98CIDCFGR_SCID_SHIFT 4 1963 #define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1964 #define RCC_R98CIDCFGR_SEMWLC_SHIFT 16 1965 1966 /* RCC_R98SEMCR register fields */ 1967 #define RCC_R98SEMCR_SEM_MUTEX BIT(0) 1968 #define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1969 #define RCC_R98SEMCR_SEMCID_SHIFT 4 1970 1971 /* RCC_R99CIDCFGR register fields */ 1972 #define RCC_R99CIDCFGR_CFEN BIT(0) 1973 #define RCC_R99CIDCFGR_SEM_EN BIT(1) 1974 #define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1975 #define RCC_R99CIDCFGR_SCID_SHIFT 4 1976 #define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1977 #define RCC_R99CIDCFGR_SEMWLC_SHIFT 16 1978 1979 /* RCC_R99SEMCR register fields */ 1980 #define RCC_R99SEMCR_SEM_MUTEX BIT(0) 1981 #define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1982 #define RCC_R99SEMCR_SEMCID_SHIFT 4 1983 1984 /* RCC_R100CIDCFGR register fields */ 1985 #define RCC_R100CIDCFGR_CFEN BIT(0) 1986 #define RCC_R100CIDCFGR_SEM_EN BIT(1) 1987 #define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1988 #define RCC_R100CIDCFGR_SCID_SHIFT 4 1989 #define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1990 #define RCC_R100CIDCFGR_SEMWLC_SHIFT 16 1991 1992 /* RCC_R100SEMCR register fields */ 1993 #define RCC_R100SEMCR_SEM_MUTEX BIT(0) 1994 #define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1995 #define RCC_R100SEMCR_SEMCID_SHIFT 4 1996 1997 /* RCC_R101CIDCFGR register fields */ 1998 #define RCC_R101CIDCFGR_CFEN BIT(0) 1999 #define RCC_R101CIDCFGR_SEM_EN BIT(1) 2000 #define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2001 #define RCC_R101CIDCFGR_SCID_SHIFT 4 2002 #define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2003 #define RCC_R101CIDCFGR_SEMWLC_SHIFT 16 2004 2005 /* RCC_R101SEMCR register fields */ 2006 #define RCC_R101SEMCR_SEM_MUTEX BIT(0) 2007 #define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2008 #define RCC_R101SEMCR_SEMCID_SHIFT 4 2009 2010 /* RCC_R102CIDCFGR register fields */ 2011 #define RCC_R102CIDCFGR_CFEN BIT(0) 2012 #define RCC_R102CIDCFGR_SEM_EN BIT(1) 2013 #define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2014 #define RCC_R102CIDCFGR_SCID_SHIFT 4 2015 #define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2016 #define RCC_R102CIDCFGR_SEMWLC_SHIFT 16 2017 2018 /* RCC_R102SEMCR register fields */ 2019 #define RCC_R102SEMCR_SEM_MUTEX BIT(0) 2020 #define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2021 #define RCC_R102SEMCR_SEMCID_SHIFT 4 2022 2023 /* RCC_R103CIDCFGR register fields */ 2024 #define RCC_R103CIDCFGR_CFEN BIT(0) 2025 #define RCC_R103CIDCFGR_SEM_EN BIT(1) 2026 #define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2027 #define RCC_R103CIDCFGR_SCID_SHIFT 4 2028 #define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2029 #define RCC_R103CIDCFGR_SEMWLC_SHIFT 16 2030 2031 /* RCC_R103SEMCR register fields */ 2032 #define RCC_R103SEMCR_SEM_MUTEX BIT(0) 2033 #define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2034 #define RCC_R103SEMCR_SEMCID_SHIFT 4 2035 2036 /* RCC_R104CIDCFGR register fields */ 2037 #define RCC_R104CIDCFGR_CFEN BIT(0) 2038 #define RCC_R104CIDCFGR_SEM_EN BIT(1) 2039 #define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2040 #define RCC_R104CIDCFGR_SCID_SHIFT 4 2041 #define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2042 #define RCC_R104CIDCFGR_SEMWLC_SHIFT 16 2043 2044 /* RCC_R104SEMCR register fields */ 2045 #define RCC_R104SEMCR_SEM_MUTEX BIT(0) 2046 #define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2047 #define RCC_R104SEMCR_SEMCID_SHIFT 4 2048 2049 /* RCC_R105CIDCFGR register fields */ 2050 #define RCC_R105CIDCFGR_CFEN BIT(0) 2051 #define RCC_R105CIDCFGR_SEM_EN BIT(1) 2052 #define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2053 #define RCC_R105CIDCFGR_SCID_SHIFT 4 2054 #define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2055 #define RCC_R105CIDCFGR_SEMWLC_SHIFT 16 2056 2057 /* RCC_R105SEMCR register fields */ 2058 #define RCC_R105SEMCR_SEM_MUTEX BIT(0) 2059 #define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2060 #define RCC_R105SEMCR_SEMCID_SHIFT 4 2061 2062 /* RCC_R106CIDCFGR register fields */ 2063 #define RCC_R106CIDCFGR_CFEN BIT(0) 2064 #define RCC_R106CIDCFGR_SEM_EN BIT(1) 2065 #define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2066 #define RCC_R106CIDCFGR_SCID_SHIFT 4 2067 #define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2068 #define RCC_R106CIDCFGR_SEMWLC_SHIFT 16 2069 2070 /* RCC_R106SEMCR register fields */ 2071 #define RCC_R106SEMCR_SEM_MUTEX BIT(0) 2072 #define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2073 #define RCC_R106SEMCR_SEMCID_SHIFT 4 2074 2075 /* RCC_R107CIDCFGR register fields */ 2076 #define RCC_R107CIDCFGR_CFEN BIT(0) 2077 #define RCC_R107CIDCFGR_SEM_EN BIT(1) 2078 #define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2079 #define RCC_R107CIDCFGR_SCID_SHIFT 4 2080 #define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2081 #define RCC_R107CIDCFGR_SEMWLC_SHIFT 16 2082 2083 /* RCC_R107SEMCR register fields */ 2084 #define RCC_R107SEMCR_SEM_MUTEX BIT(0) 2085 #define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2086 #define RCC_R107SEMCR_SEMCID_SHIFT 4 2087 2088 /* RCC_R108CIDCFGR register fields */ 2089 #define RCC_R108CIDCFGR_CFEN BIT(0) 2090 #define RCC_R108CIDCFGR_SEM_EN BIT(1) 2091 #define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2092 #define RCC_R108CIDCFGR_SCID_SHIFT 4 2093 #define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2094 #define RCC_R108CIDCFGR_SEMWLC_SHIFT 16 2095 2096 /* RCC_R108SEMCR register fields */ 2097 #define RCC_R108SEMCR_SEM_MUTEX BIT(0) 2098 #define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2099 #define RCC_R108SEMCR_SEMCID_SHIFT 4 2100 2101 /* RCC_R109CIDCFGR register fields */ 2102 #define RCC_R109CIDCFGR_CFEN BIT(0) 2103 #define RCC_R109CIDCFGR_SEM_EN BIT(1) 2104 #define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2105 #define RCC_R109CIDCFGR_SCID_SHIFT 4 2106 #define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2107 #define RCC_R109CIDCFGR_SEMWLC_SHIFT 16 2108 2109 /* RCC_R109SEMCR register fields */ 2110 #define RCC_R109SEMCR_SEM_MUTEX BIT(0) 2111 #define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2112 #define RCC_R109SEMCR_SEMCID_SHIFT 4 2113 2114 /* RCC_R110CIDCFGR register fields */ 2115 #define RCC_R110CIDCFGR_CFEN BIT(0) 2116 #define RCC_R110CIDCFGR_SEM_EN BIT(1) 2117 #define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2118 #define RCC_R110CIDCFGR_SCID_SHIFT 4 2119 #define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2120 #define RCC_R110CIDCFGR_SEMWLC_SHIFT 16 2121 2122 /* RCC_R110SEMCR register fields */ 2123 #define RCC_R110SEMCR_SEM_MUTEX BIT(0) 2124 #define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2125 #define RCC_R110SEMCR_SEMCID_SHIFT 4 2126 2127 /* RCC_R111CIDCFGR register fields */ 2128 #define RCC_R111CIDCFGR_CFEN BIT(0) 2129 #define RCC_R111CIDCFGR_SEM_EN BIT(1) 2130 #define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2131 #define RCC_R111CIDCFGR_SCID_SHIFT 4 2132 #define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2133 #define RCC_R111CIDCFGR_SEMWLC_SHIFT 16 2134 2135 /* RCC_R111SEMCR register fields */ 2136 #define RCC_R111SEMCR_SEM_MUTEX BIT(0) 2137 #define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2138 #define RCC_R111SEMCR_SEMCID_SHIFT 4 2139 2140 /* RCC_R112CIDCFGR register fields */ 2141 #define RCC_R112CIDCFGR_CFEN BIT(0) 2142 #define RCC_R112CIDCFGR_SEM_EN BIT(1) 2143 #define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2144 #define RCC_R112CIDCFGR_SCID_SHIFT 4 2145 #define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2146 #define RCC_R112CIDCFGR_SEMWLC_SHIFT 16 2147 2148 /* RCC_R112SEMCR register fields */ 2149 #define RCC_R112SEMCR_SEM_MUTEX BIT(0) 2150 #define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2151 #define RCC_R112SEMCR_SEMCID_SHIFT 4 2152 2153 /* RCC_R113CIDCFGR register fields */ 2154 #define RCC_R113CIDCFGR_CFEN BIT(0) 2155 #define RCC_R113CIDCFGR_SEM_EN BIT(1) 2156 #define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2157 #define RCC_R113CIDCFGR_SCID_SHIFT 4 2158 #define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2159 #define RCC_R113CIDCFGR_SEMWLC_SHIFT 16 2160 2161 /* RCC_R113SEMCR register fields */ 2162 #define RCC_R113SEMCR_SEM_MUTEX BIT(0) 2163 #define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2164 #define RCC_R113SEMCR_SEMCID_SHIFT 4 2165 2166 /* RCC_RxCIDCFGR register fields */ 2167 #define RCC_RxCIDCFGR_CFEN BIT(0) 2168 #define RCC_RxCIDCFGR_SEM_EN BIT(1) 2169 #define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4) 2170 #define RCC_RxCIDCFGR_SCID_SHIFT 4 2171 #define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2172 #define RCC_RxCIDCFGR_SEMWLC_SHIFT 16 2173 2174 /* RCC_RxSEMCR register fields */ 2175 #define RCC_RxSEMCR_SEM_MUTEX BIT(0) 2176 #define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4) 2177 #define RCC_RxSEMCR_SEMCID_SHIFT 4 2178 2179 /* RCC_GRSTCSETR register fields */ 2180 #define RCC_GRSTCSETR_SYSRST BIT(0) 2181 2182 /* RCC_C1RSTCSETR register fields */ 2183 #define RCC_C1RSTCSETR_C1RST BIT(0) 2184 2185 /* RCC_C2RSTCSETR register fields */ 2186 #define RCC_C2RSTCSETR_C2RST BIT(0) 2187 2188 /* RCC_CxRSTCSETR register fields */ 2189 #define RCC_CxRSTCSETR_CxRST BIT(0) 2190 2191 /* RCC_HWRSTSCLRR register fields */ 2192 #define RCC_HWRSTSCLRR_PORRSTF BIT(0) 2193 #define RCC_HWRSTSCLRR_BORRSTF BIT(1) 2194 #define RCC_HWRSTSCLRR_PADRSTF BIT(2) 2195 #define RCC_HWRSTSCLRR_HCSSRSTF BIT(3) 2196 #define RCC_HWRSTSCLRR_VCORERSTF BIT(4) 2197 #define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5) 2198 #define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6) 2199 #define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7) 2200 #define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8) 2201 #define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9) 2202 #define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10) 2203 #define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12) 2204 #define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13) 2205 #define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14) 2206 2207 /* RCC_C1HWRSTSCLRR register fields */ 2208 #define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0) 2209 #define RCC_C1HWRSTSCLRR_C1RSTF BIT(1) 2210 2211 /* RCC_C2HWRSTSCLRR register fields */ 2212 #define RCC_C2HWRSTSCLRR_C2RSTF BIT(0) 2213 2214 /* RCC_C1BOOTRSTSSETR register fields */ 2215 #define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0) 2216 #define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1) 2217 #define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2) 2218 #define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3) 2219 #define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4) 2220 #define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5) 2221 #define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6) 2222 #define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7) 2223 #define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) 2224 #define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) 2225 #define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) 2226 #define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) 2227 #define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13) 2228 #define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17) 2229 #define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) 2230 #define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) 2231 #define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20) 2232 #define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22) 2233 #define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23) 2234 2235 /* RCC_C1BOOTRSTSCLRR register fields */ 2236 #define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0) 2237 #define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1) 2238 #define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2) 2239 #define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3) 2240 #define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4) 2241 #define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5) 2242 #define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6) 2243 #define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7) 2244 #define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) 2245 #define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) 2246 #define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) 2247 #define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) 2248 #define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13) 2249 #define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) 2250 #define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) 2251 #define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) 2252 #define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20) 2253 #define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22) 2254 #define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23) 2255 2256 #define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \ 2257 RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \ 2258 RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \ 2259 RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) 2260 2261 /* RCC_C2BOOTRSTSSETR register fields */ 2262 #define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0) 2263 #define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1) 2264 #define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2) 2265 #define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3) 2266 #define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4) 2267 #define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6) 2268 #define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7) 2269 #define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) 2270 #define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) 2271 #define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) 2272 #define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) 2273 #define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14) 2274 #define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17) 2275 #define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) 2276 #define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) 2277 #define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21) 2278 #define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23) 2279 2280 /* RCC_C2BOOTRSTSCLRR register fields */ 2281 #define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0) 2282 #define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1) 2283 #define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2) 2284 #define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3) 2285 #define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4) 2286 #define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6) 2287 #define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7) 2288 #define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) 2289 #define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) 2290 #define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) 2291 #define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) 2292 #define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14) 2293 #define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) 2294 #define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) 2295 #define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) 2296 #define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21) 2297 #define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23) 2298 2299 /* RCC_C1SREQSETR register fields */ 2300 #define RCC_C1SREQSETR_STPREQ_P0 BIT(0) 2301 #define RCC_C1SREQSETR_STPREQ_P1 BIT(1) 2302 #define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0) 2303 #define RCC_C1SREQSETR_ESLPREQ BIT(16) 2304 2305 /* RCC_C1SREQCLRR register fields */ 2306 #define RCC_C1SREQCLRR_STPREQ_P0 BIT(0) 2307 #define RCC_C1SREQCLRR_STPREQ_P1 BIT(1) 2308 #define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0) 2309 #define RCC_C1SREQCLRR_ESLPREQ BIT(16) 2310 2311 /* RCC_CPUBOOTCR register fields */ 2312 #define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0) 2313 #define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1) 2314 2315 /* RCC_STBYBOOTCR register fields */ 2316 #define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1) 2317 #define RCC_STBYBOOTCR_COLD_CPU2 BIT(2) 2318 #define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4) 2319 #define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5) 2320 #define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8) 2321 2322 /* RCC_LEGBOOTCR register fields */ 2323 #define RCC_LEGBOOTCR_LEGACY_BEN BIT(0) 2324 2325 /* RCC_BDCR register fields */ 2326 #define RCC_BDCR_LSEON BIT(0) 2327 #define RCC_BDCR_LSEBYP BIT(1) 2328 #define RCC_BDCR_LSERDY BIT(2) 2329 #define RCC_BDCR_LSEDIGBYP BIT(3) 2330 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) 2331 #define RCC_BDCR_LSEDRV_SHIFT 4 2332 #define RCC_BDCR_LSECSSON BIT(6) 2333 #define RCC_BDCR_LSEGFON BIT(7) 2334 #define RCC_BDCR_LSECSSD BIT(8) 2335 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) 2336 #define RCC_BDCR_RTCSRC_SHIFT 16 2337 #define RCC_BDCR_RTCCKEN BIT(20) 2338 #define RCC_BDCR_VSWRST BIT(31) 2339 2340 /* RCC_RDCR register fields */ 2341 #define RCC_RDCR_MRD_MASK GENMASK_32(20, 16) 2342 #define RCC_RDCR_MRD_SHIFT 16 2343 #define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24) 2344 #define RCC_RDCR_EADLY_SHIFT 24 2345 2346 /* RCC_C1MSRDCR register fields */ 2347 #define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0) 2348 #define RCC_C1MSRDCR_C1MSRD_SHIFT 0 2349 #define RCC_C1MSRDCR_C1MSRST BIT(8) 2350 2351 /* RCC_PWRLPDLYCR register fields */ 2352 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0) 2353 #define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 2354 #define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24) 2355 2356 /* RCC_C1CIESETR register fields */ 2357 #define RCC_C1CIESETR_LSIRDYIE BIT(0) 2358 #define RCC_C1CIESETR_LSERDYIE BIT(1) 2359 #define RCC_C1CIESETR_HSIRDYIE BIT(2) 2360 #define RCC_C1CIESETR_HSERDYIE BIT(3) 2361 #define RCC_C1CIESETR_MSIRDYIE BIT(4) 2362 #define RCC_C1CIESETR_PLL1RDYIE BIT(5) 2363 #define RCC_C1CIESETR_PLL2RDYIE BIT(6) 2364 #define RCC_C1CIESETR_PLL3RDYIE BIT(7) 2365 #define RCC_C1CIESETR_PLL4RDYIE BIT(8) 2366 #define RCC_C1CIESETR_PLL5RDYIE BIT(9) 2367 #define RCC_C1CIESETR_PLL6RDYIE BIT(10) 2368 #define RCC_C1CIESETR_PLL7RDYIE BIT(11) 2369 #define RCC_C1CIESETR_PLL8RDYIE BIT(12) 2370 #define RCC_C1CIESETR_LSECSSIE BIT(16) 2371 #define RCC_C1CIESETR_WKUPIE BIT(20) 2372 2373 /* RCC_C1CIFCLRR register fields */ 2374 #define RCC_C1CIFCLRR_LSIRDYF BIT(0) 2375 #define RCC_C1CIFCLRR_LSERDYF BIT(1) 2376 #define RCC_C1CIFCLRR_HSIRDYF BIT(2) 2377 #define RCC_C1CIFCLRR_HSERDYF BIT(3) 2378 #define RCC_C1CIFCLRR_MSIRDYF BIT(4) 2379 #define RCC_C1CIFCLRR_PLL1RDYF BIT(5) 2380 #define RCC_C1CIFCLRR_PLL2RDYF BIT(6) 2381 #define RCC_C1CIFCLRR_PLL3RDYF BIT(7) 2382 #define RCC_C1CIFCLRR_PLL4RDYF BIT(8) 2383 #define RCC_C1CIFCLRR_PLL5RDYF BIT(9) 2384 #define RCC_C1CIFCLRR_PLL6RDYF BIT(10) 2385 #define RCC_C1CIFCLRR_PLL7RDYF BIT(11) 2386 #define RCC_C1CIFCLRR_PLL8RDYF BIT(12) 2387 #define RCC_C1CIFCLRR_LSECSSF BIT(16) 2388 #define RCC_C1CIFCLRR_WKUPF BIT(20) 2389 2390 /* RCC_C2CIESETR register fields */ 2391 #define RCC_C2CIESETR_LSIRDYIE BIT(0) 2392 #define RCC_C2CIESETR_LSERDYIE BIT(1) 2393 #define RCC_C2CIESETR_HSIRDYIE BIT(2) 2394 #define RCC_C2CIESETR_HSERDYIE BIT(3) 2395 #define RCC_C2CIESETR_MSIRDYIE BIT(4) 2396 #define RCC_C2CIESETR_PLL1RDYIE BIT(5) 2397 #define RCC_C2CIESETR_PLL2RDYIE BIT(6) 2398 #define RCC_C2CIESETR_PLL3RDYIE BIT(7) 2399 #define RCC_C2CIESETR_PLL4RDYIE BIT(8) 2400 #define RCC_C2CIESETR_PLL5RDYIE BIT(9) 2401 #define RCC_C2CIESETR_PLL6RDYIE BIT(10) 2402 #define RCC_C2CIESETR_PLL7RDYIE BIT(11) 2403 #define RCC_C2CIESETR_PLL8RDYIE BIT(12) 2404 #define RCC_C2CIESETR_LSECSSIE BIT(16) 2405 #define RCC_C2CIESETR_WKUPIE BIT(20) 2406 2407 /* RCC_C2CIFCLRR register fields */ 2408 #define RCC_C2CIFCLRR_LSIRDYF BIT(0) 2409 #define RCC_C2CIFCLRR_LSERDYF BIT(1) 2410 #define RCC_C2CIFCLRR_HSIRDYF BIT(2) 2411 #define RCC_C2CIFCLRR_HSERDYF BIT(3) 2412 #define RCC_C2CIFCLRR_MSIRDYF BIT(4) 2413 #define RCC_C2CIFCLRR_PLL1RDYF BIT(5) 2414 #define RCC_C2CIFCLRR_PLL2RDYF BIT(6) 2415 #define RCC_C2CIFCLRR_PLL3RDYF BIT(7) 2416 #define RCC_C2CIFCLRR_PLL4RDYF BIT(8) 2417 #define RCC_C2CIFCLRR_PLL5RDYF BIT(9) 2418 #define RCC_C2CIFCLRR_PLL6RDYF BIT(10) 2419 #define RCC_C2CIFCLRR_PLL7RDYF BIT(11) 2420 #define RCC_C2CIFCLRR_PLL8RDYF BIT(12) 2421 #define RCC_C2CIFCLRR_LSECSSF BIT(16) 2422 #define RCC_C2CIFCLRR_WKUPF BIT(20) 2423 2424 /* RCC_CxCIESETR register fields */ 2425 #define RCC_CxCIESETR_LSIRDYIE BIT(0) 2426 #define RCC_CxCIESETR_LSERDYIE BIT(1) 2427 #define RCC_CxCIESETR_HSIRDYIE BIT(2) 2428 #define RCC_CxCIESETR_HSERDYIE BIT(3) 2429 #define RCC_CxCIESETR_CSIRDYIE BIT(4) 2430 #define RCC_CxCIESETR_SHSIRDYIE BIT(5) 2431 #define RCC_CxCIESETR_PLL1RDYIE BIT(6) 2432 #define RCC_CxCIESETR_PLL2RDYIE BIT(7) 2433 #define RCC_CxCIESETR_PLL3RDYIE BIT(8) 2434 #define RCC_CxCIESETR_PLL4RDYIE BIT(9) 2435 #define RCC_CxCIESETR_PLL5RDYIE BIT(10) 2436 #define RCC_CxCIESETR_PLL6RDYIE BIT(11) 2437 #define RCC_CxCIESETR_PLL7RDYIE BIT(12) 2438 #define RCC_CxCIESETR_PLL8RDYIE BIT(13) 2439 #define RCC_CxCIESETR_LSECSSIE BIT(16) 2440 #define RCC_CxCIESETR_WKUPIE BIT(20) 2441 2442 /* RCC_CxCIFCLRR register fields */ 2443 #define RCC_CxCIFCLRR_LSIRDYF BIT(0) 2444 #define RCC_CxCIFCLRR_LSERDYF BIT(1) 2445 #define RCC_CxCIFCLRR_HSIRDYF BIT(2) 2446 #define RCC_CxCIFCLRR_HSERDYF BIT(3) 2447 #define RCC_CxCIFCLRR_CSIRDYF BIT(4) 2448 #define RCC_CxCIFCLRR_SHSIRDYF BIT(5) 2449 #define RCC_CxCIFCLRR_PLL1RDYF BIT(6) 2450 #define RCC_CxCIFCLRR_PLL2RDYF BIT(7) 2451 #define RCC_CxCIFCLRR_PLL3RDYF BIT(8) 2452 #define RCC_CxCIFCLRR_PLL4RDYF BIT(9) 2453 #define RCC_CxCIFCLRR_PLL5RDYF BIT(10) 2454 #define RCC_CxCIFCLRR_PLL6RDYF BIT(11) 2455 #define RCC_CxCIFCLRR_PLL7RDYF BIT(12) 2456 #define RCC_CxCIFCLRR_PLL8RDYF BIT(13) 2457 #define RCC_CxCIFCLRR_LSECSSF BIT(16) 2458 #define RCC_CxCIFCLRR_WKUPF BIT(20) 2459 2460 /* RCC_IWDGC1FZSETR register fields */ 2461 #define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0) 2462 #define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1) 2463 2464 /* RCC_IWDGC1FZCLRR register fields */ 2465 #define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0) 2466 #define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1) 2467 2468 /* RCC_IWDGC1CFGSETR register fields */ 2469 #define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0) 2470 #define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2) 2471 #define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18) 2472 2473 /* RCC_IWDGC1CFGCLRR register fields */ 2474 #define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0) 2475 #define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2) 2476 #define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18) 2477 2478 /* RCC_IWDGC2FZSETR register fields */ 2479 #define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0) 2480 #define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1) 2481 2482 /* RCC_IWDGC2FZCLRR register fields */ 2483 #define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0) 2484 #define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1) 2485 2486 /* RCC_IWDGC2CFGSETR register fields */ 2487 #define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0) 2488 #define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2) 2489 #define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18) 2490 2491 /* RCC_IWDGC2CFGCLRR register fields */ 2492 #define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0) 2493 #define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2) 2494 #define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18) 2495 2496 /* RCC_MCO1CFGR register fields */ 2497 #define RCC_MCO1CFGR_MCO1SEL BIT(0) 2498 #define RCC_MCO1CFGR_MCO1ON BIT(8) 2499 2500 /* RCC_MCO2CFGR register fields */ 2501 #define RCC_MCO2CFGR_MCO2SEL BIT(0) 2502 #define RCC_MCO2CFGR_MCO2ON BIT(8) 2503 2504 /* RCC_MCOxCFGR register fields */ 2505 #define RCC_MCOxCFGR_MCOxSEL BIT(0) 2506 #define RCC_MCOxCFGR_MCOxON BIT(8) 2507 2508 /* RCC_OCENSETR register fields */ 2509 #define RCC_OCENSETR_HSION BIT(0) 2510 #define RCC_OCENSETR_HSIKERON BIT(1) 2511 #define RCC_OCENSETR_MSION BIT(2) 2512 #define RCC_OCENSETR_MSIKERON BIT(3) 2513 #define RCC_OCENSETR_HSEDIV2ON BIT(5) 2514 #define RCC_OCENSETR_HSEDIV2BYP BIT(6) 2515 #define RCC_OCENSETR_HSEDIGBYP BIT(7) 2516 #define RCC_OCENSETR_HSEON BIT(8) 2517 #define RCC_OCENSETR_HSEKERON BIT(9) 2518 #define RCC_OCENSETR_HSEBYP BIT(10) 2519 #define RCC_OCENSETR_HSECSSON BIT(11) 2520 2521 /* RCC_OCENCLRR register fields */ 2522 #define RCC_OCENCLRR_HSION BIT(0) 2523 #define RCC_OCENCLRR_HSIKERON BIT(1) 2524 #define RCC_OCENCLRR_MSION BIT(2) 2525 #define RCC_OCENCLRR_MSIKERON BIT(3) 2526 #define RCC_OCENCLRR_HSEDIV2ON BIT(5) 2527 #define RCC_OCENCLRR_HSEDIV2BYP BIT(6) 2528 #define RCC_OCENCLRR_HSEDIGBYP BIT(7) 2529 #define RCC_OCENCLRR_HSEON BIT(8) 2530 #define RCC_OCENCLRR_HSEKERON BIT(9) 2531 #define RCC_OCENCLRR_HSEBYP BIT(10) 2532 2533 /* RCC_OCRDYR register fields */ 2534 #define RCC_OCRDYR_HSIRDY BIT(0) 2535 #define RCC_OCRDYR_MSIRDY BIT(2) 2536 #define RCC_OCRDYR_HSERDY BIT(8) 2537 #define RCC_OCRDYR_CKREST BIT(25) 2538 2539 /* RCC_HSICFGR register fields */ 2540 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) 2541 #define RCC_HSICFGR_HSITRIM_SHIFT 8 2542 #define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16) 2543 #define RCC_HSICFGR_HSICAL_SHIFT 16 2544 2545 /* RCC_MSICFGR register fields */ 2546 #define RCC_MSICFGR_MSITRIM_MASK GENMASK_32(12, 8) 2547 #define RCC_MSICFGR_MSITRIM_SHIFT 8 2548 #define RCC_MSICFGR_MSICAL_MASK GENMASK_32(23, 16) 2549 #define RCC_MSICFGR_MSICAL_SHIFT 16 2550 2551 /* RCC_LSICR register fields */ 2552 #define RCC_LSICR_LSION BIT(0) 2553 #define RCC_LSICR_LSIRDY BIT(1) 2554 2555 /* RCC_RTCDIVR register fields */ 2556 #define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0) 2557 #define RCC_RTCDIVR_RTCDIV_SHIFT 0 2558 2559 /* RCC_APB1DIVR register fields */ 2560 #define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0) 2561 #define RCC_APB1DIVR_APB1DIV_SHIFT 0 2562 #define RCC_APB1DIVR_APB1DIVRDY BIT(31) 2563 2564 /* RCC_APB2DIVR register fields */ 2565 #define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0) 2566 #define RCC_APB2DIVR_APB2DIV_SHIFT 0 2567 #define RCC_APB2DIVR_APB2DIVRDY BIT(31) 2568 2569 /* RCC_APB3DIVR register fields */ 2570 #define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0) 2571 #define RCC_APB3DIVR_APB3DIV_SHIFT 0 2572 #define RCC_APB3DIVR_APB3DIVRDY BIT(31) 2573 2574 /* RCC_APB4DIVR register fields */ 2575 #define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0) 2576 #define RCC_APB4DIVR_APB4DIV_SHIFT 0 2577 #define RCC_APB4DIVR_APB4DIVRDY BIT(31) 2578 2579 /* RCC_APB5DIVR register fields */ 2580 #define RCC_APB5DIVR_APB5DIV_MASK GENMASK_32(2, 0) 2581 #define RCC_APB5DIVR_APB5DIV_SHIFT 0 2582 #define RCC_APB5DIVR_APB5DIVRDY BIT(31) 2583 2584 /* RCC_APBDBGDIVR register fields */ 2585 #define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0) 2586 #define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0 2587 #define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31) 2588 2589 /* RCC_APBxDIVR register fields */ 2590 #define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0) 2591 #define RCC_APBxDIVR_APBxDIV_SHIFT 0 2592 #define RCC_APBxDIVR_APBxDIVRDY BIT(31) 2593 2594 /* RCC_TIMG1PRER register fields */ 2595 #define RCC_TIMG1PRER_TIMG1PRE BIT(0) 2596 #define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) 2597 2598 /* RCC_TIMG2PRER register fields */ 2599 #define RCC_TIMG2PRER_TIMG2PRE BIT(0) 2600 #define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) 2601 2602 /* RCC_TIMGxPRER register fields */ 2603 #define RCC_TIMGxPRER_TIMGxPRE BIT(0) 2604 #define RCC_TIMGxPRER_TIMGxPRERDY BIT(31) 2605 2606 /* RCC_LSMCUDIVR register fields */ 2607 #define RCC_LSMCUDIVR_LSMCUDIV BIT(0) 2608 #define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31) 2609 2610 /* RCC_DDRCPCFGR register fields */ 2611 #define RCC_DDRCPCFGR_DDRCPRST BIT(0) 2612 #define RCC_DDRCPCFGR_DDRCPEN BIT(1) 2613 #define RCC_DDRCPCFGR_DDRCPLPEN BIT(2) 2614 2615 /* RCC_DDRCAPBCFGR register fields */ 2616 #define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0) 2617 #define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1) 2618 #define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2) 2619 2620 /* RCC_DDRPHYCAPBCFGR register fields */ 2621 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0) 2622 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1) 2623 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2) 2624 2625 /* RCC_DDRPHYCCFGR register fields */ 2626 #define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1) 2627 2628 /* RCC_DDRCFGR register fields */ 2629 #define RCC_DDRCFGR_DDRCFGRST BIT(0) 2630 #define RCC_DDRCFGR_DDRCFGEN BIT(1) 2631 #define RCC_DDRCFGR_DDRCFGLPEN BIT(2) 2632 2633 /* RCC_DDRITFCFGR register fields */ 2634 #define RCC_DDRITFCFGR_DDRRST BIT(0) 2635 #define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4) 2636 #define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4 2637 #define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5) 2638 #define RCC_DDRITFCFGR_DDRSHR BIT(8) 2639 #define RCC_DDRITFCFGR_DDRPHYDLP BIT(16) 2640 2641 /* RCC_SYSRAMCFGR register fields */ 2642 #define RCC_SYSRAMCFGR_SYSRAMEN BIT(1) 2643 #define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2) 2644 2645 /* RCC_SRAM1CFGR register fields */ 2646 #define RCC_SRAM1CFGR_SRAM1EN BIT(1) 2647 #define RCC_SRAM1CFGR_SRAM1LPEN BIT(2) 2648 2649 /* RCC_RETRAMCFGR register fields */ 2650 #define RCC_RETRAMCFGR_RETRAMEN BIT(1) 2651 #define RCC_RETRAMCFGR_RETRAMLPEN BIT(2) 2652 2653 /* RCC_BKPSRAMCFGR register fields */ 2654 #define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1) 2655 #define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2) 2656 2657 /* RCC_OSPI1CFGR register fields */ 2658 #define RCC_OSPI1CFGR_OSPI1RST BIT(0) 2659 #define RCC_OSPI1CFGR_OSPI1EN BIT(1) 2660 #define RCC_OSPI1CFGR_OSPI1LPEN BIT(2) 2661 #define RCC_OSPI1CFGR_OTFDEC1RST BIT(8) 2662 #define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16) 2663 2664 /* RCC_OSPIxCFGR register fields */ 2665 #define RCC_OSPIxCFGR_OSPIxRST BIT(0) 2666 #define RCC_OSPIxCFGR_OSPIxEN BIT(1) 2667 #define RCC_OSPIxCFGR_OSPIxLPEN BIT(2) 2668 #define RCC_OSPIxCFGR_OTFDECxRST BIT(8) 2669 #define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16) 2670 2671 /* RCC_FMCCFGR register fields */ 2672 #define RCC_FMCCFGR_FMCRST BIT(0) 2673 #define RCC_FMCCFGR_FMCEN BIT(1) 2674 #define RCC_FMCCFGR_FMCLPEN BIT(2) 2675 2676 /* RCC_DBGCFGR register fields */ 2677 #define RCC_DBGCFGR_DBGEN BIT(8) 2678 #define RCC_DBGCFGR_TRACEEN BIT(9) 2679 #define RCC_DBGCFGR_DBGMCUEN BIT(10) 2680 #define RCC_DBGCFGR_DBGRST BIT(12) 2681 2682 /* RCC_STMCFGR register fields */ 2683 #define RCC_STMCFGR_STMEN BIT(1) 2684 #define RCC_STMCFGR_STMLPEN BIT(2) 2685 2686 /* RCC_ETRCFGR register fields */ 2687 #define RCC_ETRCFGR_ETREN BIT(1) 2688 #define RCC_ETRCFGR_ETRLPEN BIT(2) 2689 2690 /* RCC_GPIOACFGR register fields */ 2691 #define RCC_GPIOACFGR_GPIOARST BIT(0) 2692 #define RCC_GPIOACFGR_GPIOAEN BIT(1) 2693 #define RCC_GPIOACFGR_GPIOALPEN BIT(2) 2694 2695 /* RCC_GPIOBCFGR register fields */ 2696 #define RCC_GPIOBCFGR_GPIOBRST BIT(0) 2697 #define RCC_GPIOBCFGR_GPIOBEN BIT(1) 2698 #define RCC_GPIOBCFGR_GPIOBLPEN BIT(2) 2699 2700 /* RCC_GPIOCCFGR register fields */ 2701 #define RCC_GPIOCCFGR_GPIOCRST BIT(0) 2702 #define RCC_GPIOCCFGR_GPIOCEN BIT(1) 2703 #define RCC_GPIOCCFGR_GPIOCLPEN BIT(2) 2704 2705 /* RCC_GPIODCFGR register fields */ 2706 #define RCC_GPIODCFGR_GPIODRST BIT(0) 2707 #define RCC_GPIODCFGR_GPIODEN BIT(1) 2708 #define RCC_GPIODCFGR_GPIODLPEN BIT(2) 2709 2710 /* RCC_GPIOECFGR register fields */ 2711 #define RCC_GPIOECFGR_GPIOERST BIT(0) 2712 #define RCC_GPIOECFGR_GPIOEEN BIT(1) 2713 #define RCC_GPIOECFGR_GPIOELPEN BIT(2) 2714 2715 /* RCC_GPIOFCFGR register fields */ 2716 #define RCC_GPIOFCFGR_GPIOFRST BIT(0) 2717 #define RCC_GPIOFCFGR_GPIOFEN BIT(1) 2718 #define RCC_GPIOFCFGR_GPIOFLPEN BIT(2) 2719 2720 /* RCC_GPIOGCFGR register fields */ 2721 #define RCC_GPIOGCFGR_GPIOGRST BIT(0) 2722 #define RCC_GPIOGCFGR_GPIOGEN BIT(1) 2723 #define RCC_GPIOGCFGR_GPIOGLPEN BIT(2) 2724 2725 /* RCC_GPIOHCFGR register fields */ 2726 #define RCC_GPIOHCFGR_GPIOHRST BIT(0) 2727 #define RCC_GPIOHCFGR_GPIOHEN BIT(1) 2728 #define RCC_GPIOHCFGR_GPIOHLPEN BIT(2) 2729 2730 /* RCC_GPIOICFGR register fields */ 2731 #define RCC_GPIOICFGR_GPIOIRST BIT(0) 2732 #define RCC_GPIOICFGR_GPIOIEN BIT(1) 2733 #define RCC_GPIOICFGR_GPIOILPEN BIT(2) 2734 2735 /* RCC_GPIOZCFGR register fields */ 2736 #define RCC_GPIOZCFGR_GPIOZRST BIT(0) 2737 #define RCC_GPIOZCFGR_GPIOZEN BIT(1) 2738 #define RCC_GPIOZCFGR_GPIOZLPEN BIT(2) 2739 2740 /* RCC_GPIOxCFGR register fields */ 2741 #define RCC_GPIOxCFGR_GPIOxRST BIT(0) 2742 #define RCC_GPIOxCFGR_GPIOxEN BIT(1) 2743 #define RCC_GPIOxCFGR_GPIOxLPEN BIT(2) 2744 #define RCC_GPIOxCFGR_GPIOxAMEN BIT(3) 2745 2746 /* RCC_HPDMA1CFGR register fields */ 2747 #define RCC_HPDMA1CFGR_HPDMA1RST BIT(0) 2748 #define RCC_HPDMA1CFGR_HPDMA1EN BIT(1) 2749 #define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2) 2750 2751 /* RCC_HPDMA2CFGR register fields */ 2752 #define RCC_HPDMA2CFGR_HPDMA2RST BIT(0) 2753 #define RCC_HPDMA2CFGR_HPDMA2EN BIT(1) 2754 #define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2) 2755 2756 /* RCC_HPDMA3CFGR register fields */ 2757 #define RCC_HPDMA3CFGR_HPDMA3RST BIT(0) 2758 #define RCC_HPDMA3CFGR_HPDMA3EN BIT(1) 2759 #define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2) 2760 2761 /* RCC_HPDMAxCFGR register fields */ 2762 #define RCC_HPDMAxCFGR_HPDMAxRST BIT(0) 2763 #define RCC_HPDMAxCFGR_HPDMAxEN BIT(1) 2764 #define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2) 2765 2766 /* RCC_IPCC1CFGR register fields */ 2767 #define RCC_IPCC1CFGR_IPCC1RST BIT(0) 2768 #define RCC_IPCC1CFGR_IPCC1EN BIT(1) 2769 #define RCC_IPCC1CFGR_IPCC1LPEN BIT(2) 2770 2771 /* RCC_RTCCFGR register fields */ 2772 #define RCC_RTCCFGR_RTCEN BIT(1) 2773 #define RCC_RTCCFGR_RTCLPEN BIT(2) 2774 2775 /* RCC_SYSCPU1CFGR register fields */ 2776 #define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1) 2777 #define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2) 2778 2779 /* RCC_BSECCFGR register fields */ 2780 #define RCC_BSECCFGR_BSECEN BIT(1) 2781 #define RCC_BSECCFGR_BSECLPEN BIT(2) 2782 2783 /* RCC_PLL2CFGR1 register fields */ 2784 #define RCC_PLL2CFGR1_SSMODRST BIT(0) 2785 #define RCC_PLL2CFGR1_PLLEN BIT(8) 2786 #define RCC_PLL2CFGR1_PLLRDY BIT(24) 2787 #define RCC_PLL2CFGR1_CKREFST BIT(28) 2788 2789 /* RCC_PLL2CFGR2 register fields */ 2790 #define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 2791 #define RCC_PLL2CFGR2_FREFDIV_SHIFT 0 2792 #define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16) 2793 #define RCC_PLL2CFGR2_FBDIV_SHIFT 16 2794 2795 /* RCC_PLL2CFGR3 register fields */ 2796 #define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0) 2797 #define RCC_PLL2CFGR3_FRACIN_SHIFT 0 2798 #define RCC_PLL2CFGR3_DOWNSPREAD BIT(24) 2799 #define RCC_PLL2CFGR3_DACEN BIT(25) 2800 #define RCC_PLL2CFGR3_SSCGDIS BIT(26) 2801 2802 /* RCC_PLL2CFGR4 register fields */ 2803 #define RCC_PLL2CFGR4_DSMEN BIT(8) 2804 #define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9) 2805 #define RCC_PLL2CFGR4_BYPASS BIT(10) 2806 2807 /* RCC_PLL2CFGR5 register fields */ 2808 #define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 2809 #define RCC_PLL2CFGR5_DIVVAL_SHIFT 0 2810 #define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16) 2811 #define RCC_PLL2CFGR5_SPREAD_SHIFT 16 2812 2813 /* RCC_PLL2CFGR6 register fields */ 2814 #define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 2815 #define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0 2816 2817 /* RCC_PLL2CFGR7 register fields */ 2818 #define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 2819 #define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0 2820 2821 /* RCC_PLLxCFGR1 register fields */ 2822 #define RCC_PLLxCFGR1_SSMODRST BIT(0) 2823 #define RCC_PLLxCFGR1_PLLEN BIT(8) 2824 #define RCC_PLLxCFGR1_PLLRDY BIT(24) 2825 #define RCC_PLLxCFGR1_CKREFST BIT(28) 2826 2827 /* RCC_PLLxCFGR2 register fields */ 2828 #define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) 2829 #define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 2830 #define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) 2831 #define RCC_PLLxCFGR2_FBDIV_SHIFT 16 2832 2833 /* RCC_PLLxCFGR3 register fields */ 2834 #define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) 2835 #define RCC_PLLxCFGR3_FRACIN_SHIFT 0 2836 #define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) 2837 #define RCC_PLLxCFGR3_DACEN BIT(25) 2838 #define RCC_PLLxCFGR3_SSCGDIS BIT(26) 2839 2840 /* RCC_PLLxCFGR4 register fields */ 2841 #define RCC_PLLxCFGR4_DSMEN BIT(8) 2842 #define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) 2843 #define RCC_PLLxCFGR4_BYPASS BIT(10) 2844 2845 /* RCC_PLLxCFGR5 register fields */ 2846 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) 2847 #define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 2848 #define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) 2849 #define RCC_PLLxCFGR5_SPREAD_SHIFT 16 2850 2851 /* RCC_PLLxCFGR6 register fields */ 2852 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 2853 #define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 2854 2855 /* RCC_PLLxCFGR7 register fields */ 2856 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 2857 #define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 2858 2859 /* RCC_HSIFMONCR register fields */ 2860 #define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0) 2861 #define RCC_HSIFMONCR_HSIREF_SHIFT 0 2862 #define RCC_HSIFMONCR_HSIMONEN BIT(15) 2863 #define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16) 2864 #define RCC_HSIFMONCR_HSIDEV_SHIFT 16 2865 #define RCC_HSIFMONCR_HSIMONIE BIT(30) 2866 #define RCC_HSIFMONCR_HSIMONF BIT(31) 2867 2868 /* RCC_HSIFVALR register fields */ 2869 #define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0) 2870 #define RCC_HSIFVALR_HSIVAL_SHIFT 0 2871 2872 /* RCC_MSIFMONCR register fields */ 2873 #define RCC_MSIFMONCR_MSIREF_MASK GENMASK_32(8, 0) 2874 #define RCC_MSIFMONCR_MSIREF_SHIFT 0 2875 #define RCC_MSIFMONCR_MSIMONEN BIT(15) 2876 #define RCC_MSIFMONCR_MSIDEV_MASK GENMASK_32(20, 16) 2877 #define RCC_MSIFMONCR_MSIDEV_SHIFT 16 2878 #define RCC_MSIFMONCR_MSIMONIE BIT(30) 2879 #define RCC_MSIFMONCR_MSIMONF BIT(31) 2880 2881 /* RCC_MSIFVALR register fields */ 2882 #define RCC_MSIFVALR_MSIVAL_MASK GENMASK_32(8, 0) 2883 #define RCC_MSIFVALR_MSIVAL_SHIFT 0 2884 2885 /* RCC_TIM1CFGR register fields */ 2886 #define RCC_TIM1CFGR_TIM1RST BIT(0) 2887 #define RCC_TIM1CFGR_TIM1EN BIT(1) 2888 #define RCC_TIM1CFGR_TIM1LPEN BIT(2) 2889 2890 /* RCC_TIM2CFGR register fields */ 2891 #define RCC_TIM2CFGR_TIM2RST BIT(0) 2892 #define RCC_TIM2CFGR_TIM2EN BIT(1) 2893 #define RCC_TIM2CFGR_TIM2LPEN BIT(2) 2894 2895 /* RCC_TIM3CFGR register fields */ 2896 #define RCC_TIM3CFGR_TIM3RST BIT(0) 2897 #define RCC_TIM3CFGR_TIM3EN BIT(1) 2898 #define RCC_TIM3CFGR_TIM3LPEN BIT(2) 2899 2900 /* RCC_TIM4CFGR register fields */ 2901 #define RCC_TIM4CFGR_TIM4RST BIT(0) 2902 #define RCC_TIM4CFGR_TIM4EN BIT(1) 2903 #define RCC_TIM4CFGR_TIM4LPEN BIT(2) 2904 2905 /* RCC_TIM5CFGR register fields */ 2906 #define RCC_TIM5CFGR_TIM5RST BIT(0) 2907 #define RCC_TIM5CFGR_TIM5EN BIT(1) 2908 #define RCC_TIM5CFGR_TIM5LPEN BIT(2) 2909 2910 /* RCC_TIM6CFGR register fields */ 2911 #define RCC_TIM6CFGR_TIM6RST BIT(0) 2912 #define RCC_TIM6CFGR_TIM6EN BIT(1) 2913 #define RCC_TIM6CFGR_TIM6LPEN BIT(2) 2914 2915 /* RCC_TIM7CFGR register fields */ 2916 #define RCC_TIM7CFGR_TIM7RST BIT(0) 2917 #define RCC_TIM7CFGR_TIM7EN BIT(1) 2918 #define RCC_TIM7CFGR_TIM7LPEN BIT(2) 2919 2920 /* RCC_TIM8CFGR register fields */ 2921 #define RCC_TIM8CFGR_TIM8RST BIT(0) 2922 #define RCC_TIM8CFGR_TIM8EN BIT(1) 2923 #define RCC_TIM8CFGR_TIM8LPEN BIT(2) 2924 2925 /* RCC_TIM10CFGR register fields */ 2926 #define RCC_TIM10CFGR_TIM10RST BIT(0) 2927 #define RCC_TIM10CFGR_TIM10EN BIT(1) 2928 #define RCC_TIM10CFGR_TIM10LPEN BIT(2) 2929 2930 /* RCC_TIM11CFGR register fields */ 2931 #define RCC_TIM11CFGR_TIM11RST BIT(0) 2932 #define RCC_TIM11CFGR_TIM11EN BIT(1) 2933 #define RCC_TIM11CFGR_TIM11LPEN BIT(2) 2934 2935 /* RCC_TIM12CFGR register fields */ 2936 #define RCC_TIM12CFGR_TIM12RST BIT(0) 2937 #define RCC_TIM12CFGR_TIM12EN BIT(1) 2938 #define RCC_TIM12CFGR_TIM12LPEN BIT(2) 2939 2940 /* RCC_TIM13CFGR register fields */ 2941 #define RCC_TIM13CFGR_TIM13RST BIT(0) 2942 #define RCC_TIM13CFGR_TIM13EN BIT(1) 2943 #define RCC_TIM13CFGR_TIM13LPEN BIT(2) 2944 2945 /* RCC_TIM14CFGR register fields */ 2946 #define RCC_TIM14CFGR_TIM14RST BIT(0) 2947 #define RCC_TIM14CFGR_TIM14EN BIT(1) 2948 #define RCC_TIM14CFGR_TIM14LPEN BIT(2) 2949 2950 /* RCC_TIM15CFGR register fields */ 2951 #define RCC_TIM15CFGR_TIM15RST BIT(0) 2952 #define RCC_TIM15CFGR_TIM15EN BIT(1) 2953 #define RCC_TIM15CFGR_TIM15LPEN BIT(2) 2954 2955 /* RCC_TIM16CFGR register fields */ 2956 #define RCC_TIM16CFGR_TIM16RST BIT(0) 2957 #define RCC_TIM16CFGR_TIM16EN BIT(1) 2958 #define RCC_TIM16CFGR_TIM16LPEN BIT(2) 2959 2960 /* RCC_TIM17CFGR register fields */ 2961 #define RCC_TIM17CFGR_TIM17RST BIT(0) 2962 #define RCC_TIM17CFGR_TIM17EN BIT(1) 2963 #define RCC_TIM17CFGR_TIM17LPEN BIT(2) 2964 2965 /* RCC_LPTIM1CFGR register fields */ 2966 #define RCC_LPTIM1CFGR_LPTIM1RST BIT(0) 2967 #define RCC_LPTIM1CFGR_LPTIM1EN BIT(1) 2968 #define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2) 2969 2970 /* RCC_LPTIM2CFGR register fields */ 2971 #define RCC_LPTIM2CFGR_LPTIM2RST BIT(0) 2972 #define RCC_LPTIM2CFGR_LPTIM2EN BIT(1) 2973 #define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2) 2974 2975 /* RCC_LPTIM3CFGR register fields */ 2976 #define RCC_LPTIM3CFGR_LPTIM3RST BIT(0) 2977 #define RCC_LPTIM3CFGR_LPTIM3EN BIT(1) 2978 #define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2) 2979 2980 /* RCC_LPTIM4CFGR register fields */ 2981 #define RCC_LPTIM4CFGR_LPTIM4RST BIT(0) 2982 #define RCC_LPTIM4CFGR_LPTIM4EN BIT(1) 2983 #define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2) 2984 2985 /* RCC_LPTIM5CFGR register fields */ 2986 #define RCC_LPTIM5CFGR_LPTIM5RST BIT(0) 2987 #define RCC_LPTIM5CFGR_LPTIM5EN BIT(1) 2988 #define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2) 2989 2990 /* RCC_LPTIMxCFGR register fields */ 2991 #define RCC_LPTIMxCFGR_LPTIMxRST BIT(0) 2992 #define RCC_LPTIMxCFGR_LPTIMxEN BIT(1) 2993 #define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2) 2994 #define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3) 2995 2996 /* RCC_SPI1CFGR register fields */ 2997 #define RCC_SPI1CFGR_SPI1RST BIT(0) 2998 #define RCC_SPI1CFGR_SPI1EN BIT(1) 2999 #define RCC_SPI1CFGR_SPI1LPEN BIT(2) 3000 3001 /* RCC_SPI2CFGR register fields */ 3002 #define RCC_SPI2CFGR_SPI2RST BIT(0) 3003 #define RCC_SPI2CFGR_SPI2EN BIT(1) 3004 #define RCC_SPI2CFGR_SPI2LPEN BIT(2) 3005 3006 /* RCC_SPI3CFGR register fields */ 3007 #define RCC_SPI3CFGR_SPI3RST BIT(0) 3008 #define RCC_SPI3CFGR_SPI3EN BIT(1) 3009 #define RCC_SPI3CFGR_SPI3LPEN BIT(2) 3010 3011 /* RCC_SPI4CFGR register fields */ 3012 #define RCC_SPI4CFGR_SPI4RST BIT(0) 3013 #define RCC_SPI4CFGR_SPI4EN BIT(1) 3014 #define RCC_SPI4CFGR_SPI4LPEN BIT(2) 3015 3016 /* RCC_SPI5CFGR register fields */ 3017 #define RCC_SPI5CFGR_SPI5RST BIT(0) 3018 #define RCC_SPI5CFGR_SPI5EN BIT(1) 3019 #define RCC_SPI5CFGR_SPI5LPEN BIT(2) 3020 3021 /* RCC_SPI6CFGR register fields */ 3022 #define RCC_SPI6CFGR_SPI6RST BIT(0) 3023 #define RCC_SPI6CFGR_SPI6EN BIT(1) 3024 #define RCC_SPI6CFGR_SPI6LPEN BIT(2) 3025 3026 /* RCC_SPIxCFGR register fields */ 3027 #define RCC_SPIxCFGR_SPIxRST BIT(0) 3028 #define RCC_SPIxCFGR_SPIxEN BIT(1) 3029 #define RCC_SPIxCFGR_SPIxLPEN BIT(2) 3030 #define RCC_SPIxCFGR_SPIxAMEN BIT(3) 3031 3032 /* RCC_SPDIFRXCFGR register fields */ 3033 #define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0) 3034 #define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1) 3035 #define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2) 3036 3037 /* RCC_USART1CFGR register fields */ 3038 #define RCC_USART1CFGR_USART1RST BIT(0) 3039 #define RCC_USART1CFGR_USART1EN BIT(1) 3040 #define RCC_USART1CFGR_USART1LPEN BIT(2) 3041 3042 /* RCC_USART2CFGR register fields */ 3043 #define RCC_USART2CFGR_USART2RST BIT(0) 3044 #define RCC_USART2CFGR_USART2EN BIT(1) 3045 #define RCC_USART2CFGR_USART2LPEN BIT(2) 3046 3047 /* RCC_USART3CFGR register fields */ 3048 #define RCC_USART3CFGR_USART3RST BIT(0) 3049 #define RCC_USART3CFGR_USART3EN BIT(1) 3050 #define RCC_USART3CFGR_USART3LPEN BIT(2) 3051 3052 /* RCC_UART4CFGR register fields */ 3053 #define RCC_UART4CFGR_UART4RST BIT(0) 3054 #define RCC_UART4CFGR_UART4EN BIT(1) 3055 #define RCC_UART4CFGR_UART4LPEN BIT(2) 3056 3057 /* RCC_UART5CFGR register fields */ 3058 #define RCC_UART5CFGR_UART5RST BIT(0) 3059 #define RCC_UART5CFGR_UART5EN BIT(1) 3060 #define RCC_UART5CFGR_UART5LPEN BIT(2) 3061 3062 /* RCC_USART6CFGR register fields */ 3063 #define RCC_USART6CFGR_USART6RST BIT(0) 3064 #define RCC_USART6CFGR_USART6EN BIT(1) 3065 #define RCC_USART6CFGR_USART6LPEN BIT(2) 3066 3067 /* RCC_UART7CFGR register fields */ 3068 #define RCC_UART7CFGR_UART7RST BIT(0) 3069 #define RCC_UART7CFGR_UART7EN BIT(1) 3070 #define RCC_UART7CFGR_UART7LPEN BIT(2) 3071 3072 /* RCC_USARTxCFGR register fields */ 3073 #define RCC_USARTxCFGR_USARTxRST BIT(0) 3074 #define RCC_USARTxCFGR_USARTxEN BIT(1) 3075 #define RCC_USARTxCFGR_USARTxLPEN BIT(2) 3076 3077 /* RCC_UARTxCFGR register fields */ 3078 #define RCC_UARTxCFGR_UARTxRST BIT(0) 3079 #define RCC_UARTxCFGR_UARTxEN BIT(1) 3080 #define RCC_UARTxCFGR_UARTxLPEN BIT(2) 3081 3082 /* RCC_LPUART1CFGR register fields */ 3083 #define RCC_LPUART1CFGR_LPUART1RST BIT(0) 3084 #define RCC_LPUART1CFGR_LPUART1EN BIT(1) 3085 #define RCC_LPUART1CFGR_LPUART1LPEN BIT(2) 3086 3087 /* RCC_I2C1CFGR register fields */ 3088 #define RCC_I2C1CFGR_I2C1RST BIT(0) 3089 #define RCC_I2C1CFGR_I2C1EN BIT(1) 3090 #define RCC_I2C1CFGR_I2C1LPEN BIT(2) 3091 3092 /* RCC_I2C2CFGR register fields */ 3093 #define RCC_I2C2CFGR_I2C2RST BIT(0) 3094 #define RCC_I2C2CFGR_I2C2EN BIT(1) 3095 #define RCC_I2C2CFGR_I2C2LPEN BIT(2) 3096 3097 /* RCC_I2C3CFGR register fields */ 3098 #define RCC_I2C3CFGR_I2C3RST BIT(0) 3099 #define RCC_I2C3CFGR_I2C3EN BIT(1) 3100 #define RCC_I2C3CFGR_I2C3LPEN BIT(2) 3101 3102 /* RCC_I2CxCFGR register fields */ 3103 #define RCC_I2CxCFGR_I2CxRST BIT(0) 3104 #define RCC_I2CxCFGR_I2CxEN BIT(1) 3105 #define RCC_I2CxCFGR_I2CxLPEN BIT(2) 3106 #define RCC_I2CxCFGR_I2CxAMEN BIT(3) 3107 3108 /* RCC_SAI1CFGR register fields */ 3109 #define RCC_SAI1CFGR_SAI1RST BIT(0) 3110 #define RCC_SAI1CFGR_SAI1EN BIT(1) 3111 #define RCC_SAI1CFGR_SAI1LPEN BIT(2) 3112 3113 /* RCC_SAI2CFGR register fields */ 3114 #define RCC_SAI2CFGR_SAI2RST BIT(0) 3115 #define RCC_SAI2CFGR_SAI2EN BIT(1) 3116 #define RCC_SAI2CFGR_SAI2LPEN BIT(2) 3117 3118 /* RCC_SAI3CFGR register fields */ 3119 #define RCC_SAI3CFGR_SAI3RST BIT(0) 3120 #define RCC_SAI3CFGR_SAI3EN BIT(1) 3121 #define RCC_SAI3CFGR_SAI3LPEN BIT(2) 3122 3123 /* RCC_SAI4CFGR register fields */ 3124 #define RCC_SAI4CFGR_SAI4RST BIT(0) 3125 #define RCC_SAI4CFGR_SAI4EN BIT(1) 3126 #define RCC_SAI4CFGR_SAI4LPEN BIT(2) 3127 3128 /* RCC_SAIxCFGR register fields */ 3129 #define RCC_SAIxCFGR_SAIxRST BIT(0) 3130 #define RCC_SAIxCFGR_SAIxEN BIT(1) 3131 #define RCC_SAIxCFGR_SAIxLPEN BIT(2) 3132 3133 /* RCC_MDF1CFGR register fields */ 3134 #define RCC_MDF1CFGR_MDF1RST BIT(0) 3135 #define RCC_MDF1CFGR_MDF1EN BIT(1) 3136 #define RCC_MDF1CFGR_MDF1LPEN BIT(2) 3137 3138 /* RCC_FDCANCFGR register fields */ 3139 #define RCC_FDCANCFGR_FDCANRST BIT(0) 3140 #define RCC_FDCANCFGR_FDCANEN BIT(1) 3141 #define RCC_FDCANCFGR_FDCANLPEN BIT(2) 3142 3143 /* RCC_HDPCFGR register fields */ 3144 #define RCC_HDPCFGR_HDPRST BIT(0) 3145 #define RCC_HDPCFGR_HDPEN BIT(1) 3146 3147 /* RCC_ADC1CFGR register fields */ 3148 #define RCC_ADC1CFGR_ADC1RST BIT(0) 3149 #define RCC_ADC1CFGR_ADC1EN BIT(1) 3150 #define RCC_ADC1CFGR_ADC1LPEN BIT(2) 3151 #define RCC_ADC1CFGR_ADC1KERSEL BIT(12) 3152 3153 /* RCC_ADC2CFGR register fields */ 3154 #define RCC_ADC2CFGR_ADC2RST BIT(0) 3155 #define RCC_ADC2CFGR_ADC2EN BIT(1) 3156 #define RCC_ADC2CFGR_ADC2LPEN BIT(2) 3157 #define RCC_ADC2CFGR_ADC2KERSEL_MASK GENMASK_32(13, 12) 3158 #define RCC_ADC2CFGR_ADC2KERSEL_SHIFT 12 3159 3160 /* RCC_ETH1CFGR register fields */ 3161 #define RCC_ETH1CFGR_ETH1RST BIT(0) 3162 #define RCC_ETH1CFGR_ETH1MACEN BIT(1) 3163 #define RCC_ETH1CFGR_ETH1MACLPEN BIT(2) 3164 #define RCC_ETH1CFGR_ETH1STPEN BIT(4) 3165 #define RCC_ETH1CFGR_ETH1EN BIT(5) 3166 #define RCC_ETH1CFGR_ETH1LPEN BIT(6) 3167 #define RCC_ETH1CFGR_ETH1TXEN BIT(8) 3168 #define RCC_ETH1CFGR_ETH1TXLPEN BIT(9) 3169 #define RCC_ETH1CFGR_ETH1RXEN BIT(10) 3170 #define RCC_ETH1CFGR_ETH1RXLPEN BIT(11) 3171 3172 /* RCC_ETH2CFGR register fields */ 3173 #define RCC_ETH2CFGR_ETH2RST BIT(0) 3174 #define RCC_ETH2CFGR_ETH2MACEN BIT(1) 3175 #define RCC_ETH2CFGR_ETH2MACLPEN BIT(2) 3176 #define RCC_ETH2CFGR_ETH2STPEN BIT(4) 3177 #define RCC_ETH2CFGR_ETH2EN BIT(5) 3178 #define RCC_ETH2CFGR_ETH2LPEN BIT(6) 3179 #define RCC_ETH2CFGR_ETH2TXEN BIT(8) 3180 #define RCC_ETH2CFGR_ETH2TXLPEN BIT(9) 3181 #define RCC_ETH2CFGR_ETH2RXEN BIT(10) 3182 #define RCC_ETH2CFGR_ETH2RXLPEN BIT(11) 3183 3184 /* RCC_ETHxCFGR register fields */ 3185 #define RCC_ETHxCFGR_ETHxRST BIT(0) 3186 #define RCC_ETHxCFGR_ETHxMACEN BIT(1) 3187 #define RCC_ETHxCFGR_ETHxMACLPEN BIT(2) 3188 #define RCC_ETHxCFGR_ETHxSTPEN BIT(4) 3189 #define RCC_ETHxCFGR_ETHxEN BIT(5) 3190 #define RCC_ETHxCFGR_ETHxLPEN BIT(6) 3191 #define RCC_ETHxCFGR_ETHxTXEN BIT(8) 3192 #define RCC_ETHxCFGR_ETHxTXLPEN BIT(9) 3193 #define RCC_ETHxCFGR_ETHxRXEN BIT(10) 3194 #define RCC_ETHxCFGR_ETHxRXLPEN BIT(11) 3195 3196 /* RCC_USBHCFGR register fields */ 3197 #define RCC_USBHCFGR_USBHRST BIT(0) 3198 #define RCC_USBHCFGR_USBHEN BIT(1) 3199 #define RCC_USBHCFGR_USBHLPEN BIT(2) 3200 #define RCC_USBHCFGR_USBHSTPEN BIT(4) 3201 3202 /* RCC_USB2PHY1CFGR register fields */ 3203 #define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0) 3204 #define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1) 3205 #define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2) 3206 #define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4) 3207 #define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15) 3208 3209 /* RCC_OTGCFGR register fields */ 3210 #define RCC_OTGCFGR_OTGRST BIT(0) 3211 #define RCC_OTGCFGR_OTGEN BIT(1) 3212 #define RCC_OTGCFGR_OTGLPEN BIT(2) 3213 3214 /* RCC_USB2PHY2CFGR register fields */ 3215 #define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0) 3216 #define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1) 3217 #define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2) 3218 #define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4) 3219 #define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15) 3220 3221 /* RCC_USB2PHYxCFGR register fields */ 3222 #define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0) 3223 #define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1) 3224 #define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2) 3225 #define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4) 3226 #define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15) 3227 3228 /* RCC_STGENCFGR register fields */ 3229 #define RCC_STGENCFGR_STGENEN BIT(1) 3230 #define RCC_STGENCFGR_STGENLPEN BIT(2) 3231 #define RCC_STGENCFGR_STGENSTPEN BIT(4) 3232 3233 /* RCC_SDMMC1CFGR register fields */ 3234 #define RCC_SDMMC1CFGR_SDMMC1RST BIT(0) 3235 #define RCC_SDMMC1CFGR_SDMMC1EN BIT(1) 3236 #define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2) 3237 #define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16) 3238 3239 /* RCC_SDMMC2CFGR register fields */ 3240 #define RCC_SDMMC2CFGR_SDMMC2RST BIT(0) 3241 #define RCC_SDMMC2CFGR_SDMMC2EN BIT(1) 3242 #define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2) 3243 #define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16) 3244 3245 /* RCC_SDMMC3CFGR register fields */ 3246 #define RCC_SDMMC3CFGR_SDMMC3RST BIT(0) 3247 #define RCC_SDMMC3CFGR_SDMMC3EN BIT(1) 3248 #define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2) 3249 #define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16) 3250 3251 /* RCC_SDMMCxCFGR register fields */ 3252 #define RCC_SDMMCxCFGR_SDMMC1RST BIT(0) 3253 #define RCC_SDMMCxCFGR_SDMMC1EN BIT(1) 3254 #define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2) 3255 #define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16) 3256 3257 /* RCC_LTDCCFGR register fields */ 3258 #define RCC_LTDCCFGR_LTDCRST BIT(0) 3259 #define RCC_LTDCCFGR_LTDCEN BIT(1) 3260 #define RCC_LTDCCFGR_LTDCLPEN BIT(2) 3261 3262 /* RCC_CSICFGR register fields */ 3263 #define RCC_CSICFGR_CSIRST BIT(0) 3264 #define RCC_CSICFGR_CSIEN BIT(1) 3265 #define RCC_CSICFGR_CSILPEN BIT(2) 3266 3267 /* RCC_DCMIPPCFGR register fields */ 3268 #define RCC_DCMIPPCFGR_DCMIPPRST BIT(0) 3269 #define RCC_DCMIPPCFGR_DCMIPPEN BIT(1) 3270 #define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2) 3271 3272 /* RCC_DCMIPSSICFGR register fields */ 3273 #define RCC_DCMIPSSICFGR_DCMIPSSIRST BIT(0) 3274 #define RCC_DCMIPSSICFGR_DCMIPSSIEN BIT(1) 3275 #define RCC_DCMIPSSICFGR_DCMIPSSILPEN BIT(2) 3276 3277 /* RCC_RNG1CFGR register fields */ 3278 #define RCC_RNG1CFGR_RNG1RST BIT(0) 3279 #define RCC_RNG1CFGR_RNG1EN BIT(1) 3280 #define RCC_RNG1CFGR_RNG1LPEN BIT(2) 3281 3282 /* RCC_RNG2CFGR register fields */ 3283 #define RCC_RNG2CFGR_RNG2RST BIT(0) 3284 #define RCC_RNG2CFGR_RNG2EN BIT(1) 3285 #define RCC_RNG2CFGR_RNG2LPEN BIT(2) 3286 3287 /* RCC_PKACFGR register fields */ 3288 #define RCC_PKACFGR_PKARST BIT(0) 3289 #define RCC_PKACFGR_PKAEN BIT(1) 3290 #define RCC_PKACFGR_PKALPEN BIT(2) 3291 3292 /* RCC_SAESCFGR register fields */ 3293 #define RCC_SAESCFGR_SAESRST BIT(0) 3294 #define RCC_SAESCFGR_SAESEN BIT(1) 3295 #define RCC_SAESCFGR_SAESLPEN BIT(2) 3296 3297 /* RCC_HASH1CFGR register fields */ 3298 #define RCC_HASH1CFGR_HASH1RST BIT(0) 3299 #define RCC_HASH1CFGR_HASH1EN BIT(1) 3300 #define RCC_HASH1CFGR_HASH1LPEN BIT(2) 3301 3302 /* RCC_HASH2CFGR register fields */ 3303 #define RCC_HASH2CFGR_HASH2RST BIT(0) 3304 #define RCC_HASH2CFGR_HASH2EN BIT(1) 3305 #define RCC_HASH2CFGR_HASH2LPEN BIT(2) 3306 3307 /* RCC_CRYP1CFGR register fields */ 3308 #define RCC_CRYP1CFGR_CRYP1RST BIT(0) 3309 #define RCC_CRYP1CFGR_CRYP1EN BIT(1) 3310 #define RCC_CRYP1CFGR_CRYP1LPEN BIT(2) 3311 3312 /* RCC_CRYP2CFGR register fields */ 3313 #define RCC_CRYP2CFGR_CRYP2RST BIT(0) 3314 #define RCC_CRYP2CFGR_CRYP2EN BIT(1) 3315 #define RCC_CRYP2CFGR_CRYP2LPEN BIT(2) 3316 3317 /* RCC_CRYPxCFGR register fields */ 3318 #define RCC_CRYPxCFGR_CRYPxRST BIT(0) 3319 #define RCC_CRYPxCFGR_CRYPxEN BIT(1) 3320 #define RCC_CRYPxCFGR_CRYPxLPEN BIT(2) 3321 3322 /* RCC_IWDG1CFGR register fields */ 3323 #define RCC_IWDG1CFGR_IWDG1EN BIT(1) 3324 #define RCC_IWDG1CFGR_IWDG1LPEN BIT(2) 3325 3326 /* RCC_IWDG2CFGR register fields */ 3327 #define RCC_IWDG2CFGR_IWDG2EN BIT(1) 3328 #define RCC_IWDG2CFGR_IWDG2LPEN BIT(2) 3329 3330 /* RCC_IWDG3CFGR register fields */ 3331 #define RCC_IWDG3CFGR_IWDG3EN BIT(1) 3332 #define RCC_IWDG3CFGR_IWDG3LPEN BIT(2) 3333 3334 /* RCC_IWDG4CFGR register fields */ 3335 #define RCC_IWDG4CFGR_IWDG4EN BIT(1) 3336 #define RCC_IWDG4CFGR_IWDG4LPEN BIT(2) 3337 3338 /* RCC_IWDGxCFGR register fields */ 3339 #define RCC_IWDGxCFGR_IWDGxEN BIT(1) 3340 #define RCC_IWDGxCFGR_IWDGxLPEN BIT(2) 3341 3342 /* RCC_WWDG1CFGR register fields */ 3343 #define RCC_WWDG1CFGR_WWDG1RST BIT(0) 3344 #define RCC_WWDG1CFGR_WWDG1EN BIT(1) 3345 #define RCC_WWDG1CFGR_WWDG1LPEN BIT(2) 3346 3347 /* RCC_VREFCFGR register fields */ 3348 #define RCC_VREFCFGR_VREFRST BIT(0) 3349 #define RCC_VREFCFGR_VREFEN BIT(1) 3350 #define RCC_VREFCFGR_VREFLPEN BIT(2) 3351 3352 /* RCC_DTSCFGR register fields */ 3353 #define RCC_DTSCFGR_DTSRST BIT(0) 3354 #define RCC_DTSCFGR_DTSEN BIT(1) 3355 #define RCC_DTSCFGR_DTSLPEN BIT(2) 3356 #define RCC_DTSCFGR_DTSKERSEL_MASK GENMASK_32(13, 12) 3357 #define RCC_DTSCFGR_DTSKERSEL_SHIFT 12 3358 3359 /* RCC_CRCCFGR register fields */ 3360 #define RCC_CRCCFGR_CRCRST BIT(0) 3361 #define RCC_CRCCFGR_CRCEN BIT(1) 3362 #define RCC_CRCCFGR_CRCLPEN BIT(2) 3363 3364 /* RCC_SERCCFGR register fields */ 3365 #define RCC_SERCCFGR_SERCRST BIT(0) 3366 #define RCC_SERCCFGR_SERCEN BIT(1) 3367 #define RCC_SERCCFGR_SERCLPEN BIT(2) 3368 3369 /* RCC_DDRPERFMCFGR register fields */ 3370 #define RCC_DDRPERFMCFGR_DDRPERFMRST BIT(0) 3371 #define RCC_DDRPERFMCFGR_DDRPERFMEN BIT(1) 3372 #define RCC_DDRPERFMCFGR_DDRPERFMLPEN BIT(2) 3373 3374 /* RCC_I3C1CFGR register fields */ 3375 #define RCC_I3C1CFGR_I3C1RST BIT(0) 3376 #define RCC_I3C1CFGR_I3C1EN BIT(1) 3377 #define RCC_I3C1CFGR_I3C1LPEN BIT(2) 3378 3379 /* RCC_I3C2CFGR register fields */ 3380 #define RCC_I3C2CFGR_I3C2RST BIT(0) 3381 #define RCC_I3C2CFGR_I3C2EN BIT(1) 3382 #define RCC_I3C2CFGR_I3C2LPEN BIT(2) 3383 3384 /* RCC_I3C3CFGR register fields */ 3385 #define RCC_I3C3CFGR_I3C3RST BIT(0) 3386 #define RCC_I3C3CFGR_I3C3EN BIT(1) 3387 #define RCC_I3C3CFGR_I3C3LPEN BIT(2) 3388 3389 /* RCC_I3CxCFGR register fields */ 3390 #define RCC_I3CxCFGR_I3CxRST BIT(0) 3391 #define RCC_I3CxCFGR_I3CxEN BIT(1) 3392 #define RCC_I3CxCFGR_I3CxLPEN BIT(2) 3393 #define RCC_I3CxCFGR_I3CxAMEN BIT(3) 3394 3395 /* RCC_MUXSELCFGR register fields */ 3396 #define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(2, 0) 3397 #define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0 3398 #define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(6, 4) 3399 #define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4 3400 #define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(10, 8) 3401 #define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8 3402 #define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(14, 12) 3403 #define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12 3404 #define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(18, 16) 3405 #define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16 3406 #define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20) 3407 #define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20 3408 #define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24) 3409 #define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24 3410 #define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28) 3411 #define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28 3412 3413 /* RCC_XBAR0CFGR register fields */ 3414 #define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0) 3415 #define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0 3416 #define RCC_XBAR0CFGR_XBAR0EN BIT(6) 3417 #define RCC_XBAR0CFGR_XBAR0STS BIT(7) 3418 3419 /* RCC_XBAR1CFGR register fields */ 3420 #define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0) 3421 #define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0 3422 #define RCC_XBAR1CFGR_XBAR1EN BIT(6) 3423 #define RCC_XBAR1CFGR_XBAR1STS BIT(7) 3424 3425 /* RCC_XBAR2CFGR register fields */ 3426 #define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0) 3427 #define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0 3428 #define RCC_XBAR2CFGR_XBAR2EN BIT(6) 3429 #define RCC_XBAR2CFGR_XBAR2STS BIT(7) 3430 3431 /* RCC_XBAR3CFGR register fields */ 3432 #define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0) 3433 #define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0 3434 #define RCC_XBAR3CFGR_XBAR3EN BIT(6) 3435 #define RCC_XBAR3CFGR_XBAR3STS BIT(7) 3436 3437 /* RCC_XBAR4CFGR register fields */ 3438 #define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0) 3439 #define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0 3440 #define RCC_XBAR4CFGR_XBAR4EN BIT(6) 3441 #define RCC_XBAR4CFGR_XBAR4STS BIT(7) 3442 3443 /* RCC_XBAR5CFGR register fields */ 3444 #define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0) 3445 #define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0 3446 #define RCC_XBAR5CFGR_XBAR5EN BIT(6) 3447 #define RCC_XBAR5CFGR_XBAR5STS BIT(7) 3448 3449 /* RCC_XBAR6CFGR register fields */ 3450 #define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0) 3451 #define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0 3452 #define RCC_XBAR6CFGR_XBAR6EN BIT(6) 3453 #define RCC_XBAR6CFGR_XBAR6STS BIT(7) 3454 3455 /* RCC_XBAR7CFGR register fields */ 3456 #define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0) 3457 #define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0 3458 #define RCC_XBAR7CFGR_XBAR7EN BIT(6) 3459 #define RCC_XBAR7CFGR_XBAR7STS BIT(7) 3460 3461 /* RCC_XBAR8CFGR register fields */ 3462 #define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0) 3463 #define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0 3464 #define RCC_XBAR8CFGR_XBAR8EN BIT(6) 3465 #define RCC_XBAR8CFGR_XBAR8STS BIT(7) 3466 3467 /* RCC_XBAR9CFGR register fields */ 3468 #define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0) 3469 #define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0 3470 #define RCC_XBAR9CFGR_XBAR9EN BIT(6) 3471 #define RCC_XBAR9CFGR_XBAR9STS BIT(7) 3472 3473 /* RCC_XBAR10CFGR register fields */ 3474 #define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0) 3475 #define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0 3476 #define RCC_XBAR10CFGR_XBAR10EN BIT(6) 3477 #define RCC_XBAR10CFGR_XBAR10STS BIT(7) 3478 3479 /* RCC_XBAR11CFGR register fields */ 3480 #define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0) 3481 #define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0 3482 #define RCC_XBAR11CFGR_XBAR11EN BIT(6) 3483 #define RCC_XBAR11CFGR_XBAR11STS BIT(7) 3484 3485 /* RCC_XBAR12CFGR register fields */ 3486 #define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0) 3487 #define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0 3488 #define RCC_XBAR12CFGR_XBAR12EN BIT(6) 3489 #define RCC_XBAR12CFGR_XBAR12STS BIT(7) 3490 3491 /* RCC_XBAR13CFGR register fields */ 3492 #define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0) 3493 #define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0 3494 #define RCC_XBAR13CFGR_XBAR13EN BIT(6) 3495 #define RCC_XBAR13CFGR_XBAR13STS BIT(7) 3496 3497 /* RCC_XBAR14CFGR register fields */ 3498 #define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0) 3499 #define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0 3500 #define RCC_XBAR14CFGR_XBAR14EN BIT(6) 3501 #define RCC_XBAR14CFGR_XBAR14STS BIT(7) 3502 3503 /* RCC_XBAR15CFGR register fields */ 3504 #define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0) 3505 #define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0 3506 #define RCC_XBAR15CFGR_XBAR15EN BIT(6) 3507 #define RCC_XBAR15CFGR_XBAR15STS BIT(7) 3508 3509 /* RCC_XBAR16CFGR register fields */ 3510 #define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0) 3511 #define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0 3512 #define RCC_XBAR16CFGR_XBAR16EN BIT(6) 3513 #define RCC_XBAR16CFGR_XBAR16STS BIT(7) 3514 3515 /* RCC_XBAR17CFGR register fields */ 3516 #define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0) 3517 #define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0 3518 #define RCC_XBAR17CFGR_XBAR17EN BIT(6) 3519 #define RCC_XBAR17CFGR_XBAR17STS BIT(7) 3520 3521 /* RCC_XBAR18CFGR register fields */ 3522 #define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0) 3523 #define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0 3524 #define RCC_XBAR18CFGR_XBAR18EN BIT(6) 3525 #define RCC_XBAR18CFGR_XBAR18STS BIT(7) 3526 3527 /* RCC_XBAR19CFGR register fields */ 3528 #define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0) 3529 #define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0 3530 #define RCC_XBAR19CFGR_XBAR19EN BIT(6) 3531 #define RCC_XBAR19CFGR_XBAR19STS BIT(7) 3532 3533 /* RCC_XBAR20CFGR register fields */ 3534 #define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0) 3535 #define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0 3536 #define RCC_XBAR20CFGR_XBAR20EN BIT(6) 3537 #define RCC_XBAR20CFGR_XBAR20STS BIT(7) 3538 3539 /* RCC_XBAR21CFGR register fields */ 3540 #define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0) 3541 #define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0 3542 #define RCC_XBAR21CFGR_XBAR21EN BIT(6) 3543 #define RCC_XBAR21CFGR_XBAR21STS BIT(7) 3544 3545 /* RCC_XBAR22CFGR register fields */ 3546 #define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0) 3547 #define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0 3548 #define RCC_XBAR22CFGR_XBAR22EN BIT(6) 3549 #define RCC_XBAR22CFGR_XBAR22STS BIT(7) 3550 3551 /* RCC_XBAR23CFGR register fields */ 3552 #define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0) 3553 #define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0 3554 #define RCC_XBAR23CFGR_XBAR23EN BIT(6) 3555 #define RCC_XBAR23CFGR_XBAR23STS BIT(7) 3556 3557 /* RCC_XBAR24CFGR register fields */ 3558 #define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0) 3559 #define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0 3560 #define RCC_XBAR24CFGR_XBAR24EN BIT(6) 3561 #define RCC_XBAR24CFGR_XBAR24STS BIT(7) 3562 3563 /* RCC_XBAR25CFGR register fields */ 3564 #define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0) 3565 #define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0 3566 #define RCC_XBAR25CFGR_XBAR25EN BIT(6) 3567 #define RCC_XBAR25CFGR_XBAR25STS BIT(7) 3568 3569 /* RCC_XBAR26CFGR register fields */ 3570 #define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0) 3571 #define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0 3572 #define RCC_XBAR26CFGR_XBAR26EN BIT(6) 3573 #define RCC_XBAR26CFGR_XBAR26STS BIT(7) 3574 3575 /* RCC_XBAR27CFGR register fields */ 3576 #define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0) 3577 #define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0 3578 #define RCC_XBAR27CFGR_XBAR27EN BIT(6) 3579 #define RCC_XBAR27CFGR_XBAR27STS BIT(7) 3580 3581 /* RCC_XBAR28CFGR register fields */ 3582 #define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0) 3583 #define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0 3584 #define RCC_XBAR28CFGR_XBAR28EN BIT(6) 3585 #define RCC_XBAR28CFGR_XBAR28STS BIT(7) 3586 3587 /* RCC_XBAR29CFGR register fields */ 3588 #define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0) 3589 #define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0 3590 #define RCC_XBAR29CFGR_XBAR29EN BIT(6) 3591 #define RCC_XBAR29CFGR_XBAR29STS BIT(7) 3592 3593 /* RCC_XBAR30CFGR register fields */ 3594 #define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0) 3595 #define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0 3596 #define RCC_XBAR30CFGR_XBAR30EN BIT(6) 3597 #define RCC_XBAR30CFGR_XBAR30STS BIT(7) 3598 3599 /* RCC_XBAR31CFGR register fields */ 3600 #define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0) 3601 #define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0 3602 #define RCC_XBAR31CFGR_XBAR31EN BIT(6) 3603 #define RCC_XBAR31CFGR_XBAR31STS BIT(7) 3604 3605 /* RCC_XBAR32CFGR register fields */ 3606 #define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0) 3607 #define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0 3608 #define RCC_XBAR32CFGR_XBAR32EN BIT(6) 3609 #define RCC_XBAR32CFGR_XBAR32STS BIT(7) 3610 3611 /* RCC_XBAR33CFGR register fields */ 3612 #define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0) 3613 #define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0 3614 #define RCC_XBAR33CFGR_XBAR33EN BIT(6) 3615 #define RCC_XBAR33CFGR_XBAR33STS BIT(7) 3616 3617 /* RCC_XBAR34CFGR register fields */ 3618 #define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0) 3619 #define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0 3620 #define RCC_XBAR34CFGR_XBAR34EN BIT(6) 3621 #define RCC_XBAR34CFGR_XBAR34STS BIT(7) 3622 3623 /* RCC_XBAR35CFGR register fields */ 3624 #define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0) 3625 #define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0 3626 #define RCC_XBAR35CFGR_XBAR35EN BIT(6) 3627 #define RCC_XBAR35CFGR_XBAR35STS BIT(7) 3628 3629 /* RCC_XBAR36CFGR register fields */ 3630 #define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0) 3631 #define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0 3632 #define RCC_XBAR36CFGR_XBAR36EN BIT(6) 3633 #define RCC_XBAR36CFGR_XBAR36STS BIT(7) 3634 3635 /* RCC_XBAR37CFGR register fields */ 3636 #define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0) 3637 #define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0 3638 #define RCC_XBAR37CFGR_XBAR37EN BIT(6) 3639 #define RCC_XBAR37CFGR_XBAR37STS BIT(7) 3640 3641 /* RCC_XBAR38CFGR register fields */ 3642 #define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0) 3643 #define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0 3644 #define RCC_XBAR38CFGR_XBAR38EN BIT(6) 3645 #define RCC_XBAR38CFGR_XBAR38STS BIT(7) 3646 3647 /* RCC_XBAR39CFGR register fields */ 3648 #define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0) 3649 #define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0 3650 #define RCC_XBAR39CFGR_XBAR39EN BIT(6) 3651 #define RCC_XBAR39CFGR_XBAR39STS BIT(7) 3652 3653 /* RCC_XBAR40CFGR register fields */ 3654 #define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0) 3655 #define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0 3656 #define RCC_XBAR40CFGR_XBAR40EN BIT(6) 3657 #define RCC_XBAR40CFGR_XBAR40STS BIT(7) 3658 3659 /* RCC_XBAR41CFGR register fields */ 3660 #define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0) 3661 #define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0 3662 #define RCC_XBAR41CFGR_XBAR41EN BIT(6) 3663 #define RCC_XBAR41CFGR_XBAR41STS BIT(7) 3664 3665 /* RCC_XBAR42CFGR register fields */ 3666 #define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0) 3667 #define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0 3668 #define RCC_XBAR42CFGR_XBAR42EN BIT(6) 3669 #define RCC_XBAR42CFGR_XBAR42STS BIT(7) 3670 3671 /* RCC_XBAR43CFGR register fields */ 3672 #define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0) 3673 #define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0 3674 #define RCC_XBAR43CFGR_XBAR43EN BIT(6) 3675 #define RCC_XBAR43CFGR_XBAR43STS BIT(7) 3676 3677 /* RCC_XBAR44CFGR register fields */ 3678 #define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0) 3679 #define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0 3680 #define RCC_XBAR44CFGR_XBAR44EN BIT(6) 3681 #define RCC_XBAR44CFGR_XBAR44STS BIT(7) 3682 3683 /* RCC_XBAR45CFGR register fields */ 3684 #define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0) 3685 #define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0 3686 #define RCC_XBAR45CFGR_XBAR45EN BIT(6) 3687 #define RCC_XBAR45CFGR_XBAR45STS BIT(7) 3688 3689 /* RCC_XBAR46CFGR register fields */ 3690 #define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0) 3691 #define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0 3692 #define RCC_XBAR46CFGR_XBAR46EN BIT(6) 3693 #define RCC_XBAR46CFGR_XBAR46STS BIT(7) 3694 3695 /* RCC_XBAR47CFGR register fields */ 3696 #define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0) 3697 #define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0 3698 #define RCC_XBAR47CFGR_XBAR47EN BIT(6) 3699 #define RCC_XBAR47CFGR_XBAR47STS BIT(7) 3700 3701 /* RCC_XBAR48CFGR register fields */ 3702 #define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0) 3703 #define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0 3704 #define RCC_XBAR48CFGR_XBAR48EN BIT(6) 3705 #define RCC_XBAR48CFGR_XBAR48STS BIT(7) 3706 3707 /* RCC_XBAR49CFGR register fields */ 3708 #define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0) 3709 #define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0 3710 #define RCC_XBAR49CFGR_XBAR49EN BIT(6) 3711 #define RCC_XBAR49CFGR_XBAR49STS BIT(7) 3712 3713 /* RCC_XBAR50CFGR register fields */ 3714 #define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0) 3715 #define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0 3716 #define RCC_XBAR50CFGR_XBAR50EN BIT(6) 3717 #define RCC_XBAR50CFGR_XBAR50STS BIT(7) 3718 3719 /* RCC_XBAR51CFGR register fields */ 3720 #define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0) 3721 #define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0 3722 #define RCC_XBAR51CFGR_XBAR51EN BIT(6) 3723 #define RCC_XBAR51CFGR_XBAR51STS BIT(7) 3724 3725 /* RCC_XBAR52CFGR register fields */ 3726 #define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0) 3727 #define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0 3728 #define RCC_XBAR52CFGR_XBAR52EN BIT(6) 3729 #define RCC_XBAR52CFGR_XBAR52STS BIT(7) 3730 3731 /* RCC_XBAR53CFGR register fields */ 3732 #define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0) 3733 #define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0 3734 #define RCC_XBAR53CFGR_XBAR53EN BIT(6) 3735 #define RCC_XBAR53CFGR_XBAR53STS BIT(7) 3736 3737 /* RCC_XBAR54CFGR register fields */ 3738 #define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0) 3739 #define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0 3740 #define RCC_XBAR54CFGR_XBAR54EN BIT(6) 3741 #define RCC_XBAR54CFGR_XBAR54STS BIT(7) 3742 3743 /* RCC_XBAR55CFGR register fields */ 3744 #define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0) 3745 #define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0 3746 #define RCC_XBAR55CFGR_XBAR55EN BIT(6) 3747 #define RCC_XBAR55CFGR_XBAR55STS BIT(7) 3748 3749 /* RCC_XBAR56CFGR register fields */ 3750 #define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0) 3751 #define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0 3752 #define RCC_XBAR56CFGR_XBAR56EN BIT(6) 3753 #define RCC_XBAR56CFGR_XBAR56STS BIT(7) 3754 3755 /* RCC_XBAR57CFGR register fields */ 3756 #define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0) 3757 #define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0 3758 #define RCC_XBAR57CFGR_XBAR57EN BIT(6) 3759 #define RCC_XBAR57CFGR_XBAR57STS BIT(7) 3760 3761 /* RCC_XBAR58CFGR register fields */ 3762 #define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0) 3763 #define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0 3764 #define RCC_XBAR58CFGR_XBAR58EN BIT(6) 3765 #define RCC_XBAR58CFGR_XBAR58STS BIT(7) 3766 3767 /* RCC_XBAR59CFGR register fields */ 3768 #define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0) 3769 #define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0 3770 #define RCC_XBAR59CFGR_XBAR59EN BIT(6) 3771 #define RCC_XBAR59CFGR_XBAR59STS BIT(7) 3772 3773 /* RCC_XBAR60CFGR register fields */ 3774 #define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0) 3775 #define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0 3776 #define RCC_XBAR60CFGR_XBAR60EN BIT(6) 3777 #define RCC_XBAR60CFGR_XBAR60STS BIT(7) 3778 3779 /* RCC_XBAR61CFGR register fields */ 3780 #define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0) 3781 #define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0 3782 #define RCC_XBAR61CFGR_XBAR61EN BIT(6) 3783 #define RCC_XBAR61CFGR_XBAR61STS BIT(7) 3784 3785 /* RCC_XBAR62CFGR register fields */ 3786 #define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0) 3787 #define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0 3788 #define RCC_XBAR62CFGR_XBAR62EN BIT(6) 3789 #define RCC_XBAR62CFGR_XBAR62STS BIT(7) 3790 3791 /* RCC_XBAR63CFGR register fields */ 3792 #define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0) 3793 #define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0 3794 #define RCC_XBAR63CFGR_XBAR63EN BIT(6) 3795 #define RCC_XBAR63CFGR_XBAR63STS BIT(7) 3796 3797 /* RCC_XBARxCFGR register fields */ 3798 #define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0) 3799 #define RCC_XBARxCFGR_XBARxSEL_SHIFT 0 3800 #define RCC_XBARxCFGR_XBARxEN BIT(6) 3801 #define RCC_XBARxCFGR_XBARxSTS BIT(7) 3802 3803 /* RCC_PREDIV0CFGR register fields */ 3804 #define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0) 3805 #define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0 3806 3807 /* RCC_PREDIV1CFGR register fields */ 3808 #define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0) 3809 #define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0 3810 3811 /* RCC_PREDIV2CFGR register fields */ 3812 #define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0) 3813 #define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0 3814 3815 /* RCC_PREDIV3CFGR register fields */ 3816 #define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0) 3817 #define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0 3818 3819 /* RCC_PREDIV4CFGR register fields */ 3820 #define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0) 3821 #define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0 3822 3823 /* RCC_PREDIV5CFGR register fields */ 3824 #define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0) 3825 #define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0 3826 3827 /* RCC_PREDIV6CFGR register fields */ 3828 #define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0) 3829 #define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0 3830 3831 /* RCC_PREDIV7CFGR register fields */ 3832 #define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0) 3833 #define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0 3834 3835 /* RCC_PREDIV8CFGR register fields */ 3836 #define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0) 3837 #define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0 3838 3839 /* RCC_PREDIV9CFGR register fields */ 3840 #define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0) 3841 #define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0 3842 3843 /* RCC_PREDIV10CFGR register fields */ 3844 #define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0) 3845 #define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0 3846 3847 /* RCC_PREDIV11CFGR register fields */ 3848 #define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0) 3849 #define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0 3850 3851 /* RCC_PREDIV12CFGR register fields */ 3852 #define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0) 3853 #define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0 3854 3855 /* RCC_PREDIV13CFGR register fields */ 3856 #define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0) 3857 #define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0 3858 3859 /* RCC_PREDIV14CFGR register fields */ 3860 #define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0) 3861 #define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0 3862 3863 /* RCC_PREDIV15CFGR register fields */ 3864 #define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0) 3865 #define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0 3866 3867 /* RCC_PREDIV16CFGR register fields */ 3868 #define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0) 3869 #define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0 3870 3871 /* RCC_PREDIV17CFGR register fields */ 3872 #define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0) 3873 #define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0 3874 3875 /* RCC_PREDIV18CFGR register fields */ 3876 #define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0) 3877 #define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0 3878 3879 /* RCC_PREDIV19CFGR register fields */ 3880 #define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0) 3881 #define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0 3882 3883 /* RCC_PREDIV20CFGR register fields */ 3884 #define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0) 3885 #define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0 3886 3887 /* RCC_PREDIV21CFGR register fields */ 3888 #define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0) 3889 #define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0 3890 3891 /* RCC_PREDIV22CFGR register fields */ 3892 #define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0) 3893 #define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0 3894 3895 /* RCC_PREDIV23CFGR register fields */ 3896 #define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0) 3897 #define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0 3898 3899 /* RCC_PREDIV24CFGR register fields */ 3900 #define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0) 3901 #define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0 3902 3903 /* RCC_PREDIV25CFGR register fields */ 3904 #define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0) 3905 #define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0 3906 3907 /* RCC_PREDIV26CFGR register fields */ 3908 #define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0) 3909 #define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0 3910 3911 /* RCC_PREDIV27CFGR register fields */ 3912 #define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0) 3913 #define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0 3914 3915 /* RCC_PREDIV28CFGR register fields */ 3916 #define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0) 3917 #define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0 3918 3919 /* RCC_PREDIV29CFGR register fields */ 3920 #define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0) 3921 #define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0 3922 3923 /* RCC_PREDIV30CFGR register fields */ 3924 #define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0) 3925 #define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0 3926 3927 /* RCC_PREDIV31CFGR register fields */ 3928 #define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0) 3929 #define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0 3930 3931 /* RCC_PREDIV32CFGR register fields */ 3932 #define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0) 3933 #define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0 3934 3935 /* RCC_PREDIV33CFGR register fields */ 3936 #define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0) 3937 #define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0 3938 3939 /* RCC_PREDIV34CFGR register fields */ 3940 #define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0) 3941 #define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0 3942 3943 /* RCC_PREDIV35CFGR register fields */ 3944 #define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0) 3945 #define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0 3946 3947 /* RCC_PREDIV36CFGR register fields */ 3948 #define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0) 3949 #define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0 3950 3951 /* RCC_PREDIV37CFGR register fields */ 3952 #define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0) 3953 #define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0 3954 3955 /* RCC_PREDIV38CFGR register fields */ 3956 #define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0) 3957 #define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0 3958 3959 /* RCC_PREDIV39CFGR register fields */ 3960 #define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0) 3961 #define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0 3962 3963 /* RCC_PREDIV40CFGR register fields */ 3964 #define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0) 3965 #define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0 3966 3967 /* RCC_PREDIV41CFGR register fields */ 3968 #define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0) 3969 #define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0 3970 3971 /* RCC_PREDIV42CFGR register fields */ 3972 #define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0) 3973 #define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0 3974 3975 /* RCC_PREDIV43CFGR register fields */ 3976 #define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0) 3977 #define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0 3978 3979 /* RCC_PREDIV44CFGR register fields */ 3980 #define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0) 3981 #define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0 3982 3983 /* RCC_PREDIV45CFGR register fields */ 3984 #define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0) 3985 #define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0 3986 3987 /* RCC_PREDIV46CFGR register fields */ 3988 #define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0) 3989 #define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0 3990 3991 /* RCC_PREDIV47CFGR register fields */ 3992 #define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0) 3993 #define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0 3994 3995 /* RCC_PREDIV48CFGR register fields */ 3996 #define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0) 3997 #define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0 3998 3999 /* RCC_PREDIV49CFGR register fields */ 4000 #define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0) 4001 #define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0 4002 4003 /* RCC_PREDIV50CFGR register fields */ 4004 #define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0) 4005 #define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0 4006 4007 /* RCC_PREDIV51CFGR register fields */ 4008 #define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0) 4009 #define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0 4010 4011 /* RCC_PREDIV52CFGR register fields */ 4012 #define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0) 4013 #define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0 4014 4015 /* RCC_PREDIV53CFGR register fields */ 4016 #define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0) 4017 #define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0 4018 4019 /* RCC_PREDIV54CFGR register fields */ 4020 #define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0) 4021 #define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0 4022 4023 /* RCC_PREDIV55CFGR register fields */ 4024 #define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0) 4025 #define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0 4026 4027 /* RCC_PREDIV56CFGR register fields */ 4028 #define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0) 4029 #define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0 4030 4031 /* RCC_PREDIV57CFGR register fields */ 4032 #define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0) 4033 #define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0 4034 4035 /* RCC_PREDIV58CFGR register fields */ 4036 #define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0) 4037 #define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0 4038 4039 /* RCC_PREDIV59CFGR register fields */ 4040 #define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0) 4041 #define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0 4042 4043 /* RCC_PREDIV60CFGR register fields */ 4044 #define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0) 4045 #define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0 4046 4047 /* RCC_PREDIV61CFGR register fields */ 4048 #define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0) 4049 #define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0 4050 4051 /* RCC_PREDIV62CFGR register fields */ 4052 #define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0) 4053 #define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0 4054 4055 /* RCC_PREDIV63CFGR register fields */ 4056 #define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0) 4057 #define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0 4058 4059 /* RCC_PREDIVxCFGR register fields */ 4060 #define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0) 4061 #define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0 4062 4063 /* RCC_FINDIV0CFGR register fields */ 4064 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) 4065 #define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0 4066 #define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) 4067 4068 /* RCC_FINDIV1CFGR register fields */ 4069 #define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0) 4070 #define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0 4071 #define RCC_FINDIV1CFGR_FINDIV1EN BIT(6) 4072 4073 /* RCC_FINDIV2CFGR register fields */ 4074 #define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0) 4075 #define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0 4076 #define RCC_FINDIV2CFGR_FINDIV2EN BIT(6) 4077 4078 /* RCC_FINDIV3CFGR register fields */ 4079 #define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0) 4080 #define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0 4081 #define RCC_FINDIV3CFGR_FINDIV3EN BIT(6) 4082 4083 /* RCC_FINDIV4CFGR register fields */ 4084 #define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0) 4085 #define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0 4086 #define RCC_FINDIV4CFGR_FINDIV4EN BIT(6) 4087 4088 /* RCC_FINDIV5CFGR register fields */ 4089 #define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0) 4090 #define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0 4091 #define RCC_FINDIV5CFGR_FINDIV5EN BIT(6) 4092 4093 /* RCC_FINDIV6CFGR register fields */ 4094 #define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0) 4095 #define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0 4096 #define RCC_FINDIV6CFGR_FINDIV6EN BIT(6) 4097 4098 /* RCC_FINDIV7CFGR register fields */ 4099 #define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0) 4100 #define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0 4101 #define RCC_FINDIV7CFGR_FINDIV7EN BIT(6) 4102 4103 /* RCC_FINDIV8CFGR register fields */ 4104 #define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0) 4105 #define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0 4106 #define RCC_FINDIV8CFGR_FINDIV8EN BIT(6) 4107 4108 /* RCC_FINDIV9CFGR register fields */ 4109 #define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0) 4110 #define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0 4111 #define RCC_FINDIV9CFGR_FINDIV9EN BIT(6) 4112 4113 /* RCC_FINDIV10CFGR register fields */ 4114 #define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0) 4115 #define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0 4116 #define RCC_FINDIV10CFGR_FINDIV10EN BIT(6) 4117 4118 /* RCC_FINDIV11CFGR register fields */ 4119 #define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0) 4120 #define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0 4121 #define RCC_FINDIV11CFGR_FINDIV11EN BIT(6) 4122 4123 /* RCC_FINDIV12CFGR register fields */ 4124 #define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0) 4125 #define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0 4126 #define RCC_FINDIV12CFGR_FINDIV12EN BIT(6) 4127 4128 /* RCC_FINDIV13CFGR register fields */ 4129 #define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0) 4130 #define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0 4131 #define RCC_FINDIV13CFGR_FINDIV13EN BIT(6) 4132 4133 /* RCC_FINDIV14CFGR register fields */ 4134 #define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0) 4135 #define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0 4136 #define RCC_FINDIV14CFGR_FINDIV14EN BIT(6) 4137 4138 /* RCC_FINDIV15CFGR register fields */ 4139 #define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0) 4140 #define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0 4141 #define RCC_FINDIV15CFGR_FINDIV15EN BIT(6) 4142 4143 /* RCC_FINDIV16CFGR register fields */ 4144 #define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0) 4145 #define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0 4146 #define RCC_FINDIV16CFGR_FINDIV16EN BIT(6) 4147 4148 /* RCC_FINDIV17CFGR register fields */ 4149 #define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0) 4150 #define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0 4151 #define RCC_FINDIV17CFGR_FINDIV17EN BIT(6) 4152 4153 /* RCC_FINDIV18CFGR register fields */ 4154 #define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0) 4155 #define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0 4156 #define RCC_FINDIV18CFGR_FINDIV18EN BIT(6) 4157 4158 /* RCC_FINDIV19CFGR register fields */ 4159 #define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0) 4160 #define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0 4161 #define RCC_FINDIV19CFGR_FINDIV19EN BIT(6) 4162 4163 /* RCC_FINDIV20CFGR register fields */ 4164 #define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0) 4165 #define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0 4166 #define RCC_FINDIV20CFGR_FINDIV20EN BIT(6) 4167 4168 /* RCC_FINDIV21CFGR register fields */ 4169 #define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0) 4170 #define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0 4171 #define RCC_FINDIV21CFGR_FINDIV21EN BIT(6) 4172 4173 /* RCC_FINDIV22CFGR register fields */ 4174 #define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0) 4175 #define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0 4176 #define RCC_FINDIV22CFGR_FINDIV22EN BIT(6) 4177 4178 /* RCC_FINDIV23CFGR register fields */ 4179 #define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0) 4180 #define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0 4181 #define RCC_FINDIV23CFGR_FINDIV23EN BIT(6) 4182 4183 /* RCC_FINDIV24CFGR register fields */ 4184 #define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0) 4185 #define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0 4186 #define RCC_FINDIV24CFGR_FINDIV24EN BIT(6) 4187 4188 /* RCC_FINDIV25CFGR register fields */ 4189 #define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0) 4190 #define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0 4191 #define RCC_FINDIV25CFGR_FINDIV25EN BIT(6) 4192 4193 /* RCC_FINDIV26CFGR register fields */ 4194 #define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0) 4195 #define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0 4196 #define RCC_FINDIV26CFGR_FINDIV26EN BIT(6) 4197 4198 /* RCC_FINDIV27CFGR register fields */ 4199 #define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0) 4200 #define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0 4201 #define RCC_FINDIV27CFGR_FINDIV27EN BIT(6) 4202 4203 /* RCC_FINDIV28CFGR register fields */ 4204 #define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0) 4205 #define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0 4206 #define RCC_FINDIV28CFGR_FINDIV28EN BIT(6) 4207 4208 /* RCC_FINDIV29CFGR register fields */ 4209 #define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0) 4210 #define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0 4211 #define RCC_FINDIV29CFGR_FINDIV29EN BIT(6) 4212 4213 /* RCC_FINDIV30CFGR register fields */ 4214 #define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0) 4215 #define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0 4216 #define RCC_FINDIV30CFGR_FINDIV30EN BIT(6) 4217 4218 /* RCC_FINDIV31CFGR register fields */ 4219 #define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0) 4220 #define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0 4221 #define RCC_FINDIV31CFGR_FINDIV31EN BIT(6) 4222 4223 /* RCC_FINDIV32CFGR register fields */ 4224 #define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0) 4225 #define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0 4226 #define RCC_FINDIV32CFGR_FINDIV32EN BIT(6) 4227 4228 /* RCC_FINDIV33CFGR register fields */ 4229 #define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0) 4230 #define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0 4231 #define RCC_FINDIV33CFGR_FINDIV33EN BIT(6) 4232 4233 /* RCC_FINDIV34CFGR register fields */ 4234 #define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0) 4235 #define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0 4236 #define RCC_FINDIV34CFGR_FINDIV34EN BIT(6) 4237 4238 /* RCC_FINDIV35CFGR register fields */ 4239 #define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0) 4240 #define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0 4241 #define RCC_FINDIV35CFGR_FINDIV35EN BIT(6) 4242 4243 /* RCC_FINDIV36CFGR register fields */ 4244 #define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0) 4245 #define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0 4246 #define RCC_FINDIV36CFGR_FINDIV36EN BIT(6) 4247 4248 /* RCC_FINDIV37CFGR register fields */ 4249 #define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0) 4250 #define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0 4251 #define RCC_FINDIV37CFGR_FINDIV37EN BIT(6) 4252 4253 /* RCC_FINDIV38CFGR register fields */ 4254 #define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0) 4255 #define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0 4256 #define RCC_FINDIV38CFGR_FINDIV38EN BIT(6) 4257 4258 /* RCC_FINDIV39CFGR register fields */ 4259 #define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0) 4260 #define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0 4261 #define RCC_FINDIV39CFGR_FINDIV39EN BIT(6) 4262 4263 /* RCC_FINDIV40CFGR register fields */ 4264 #define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0) 4265 #define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0 4266 #define RCC_FINDIV40CFGR_FINDIV40EN BIT(6) 4267 4268 /* RCC_FINDIV41CFGR register fields */ 4269 #define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0) 4270 #define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0 4271 #define RCC_FINDIV41CFGR_FINDIV41EN BIT(6) 4272 4273 /* RCC_FINDIV42CFGR register fields */ 4274 #define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0) 4275 #define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0 4276 #define RCC_FINDIV42CFGR_FINDIV42EN BIT(6) 4277 4278 /* RCC_FINDIV43CFGR register fields */ 4279 #define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0) 4280 #define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0 4281 #define RCC_FINDIV43CFGR_FINDIV43EN BIT(6) 4282 4283 /* RCC_FINDIV44CFGR register fields */ 4284 #define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0) 4285 #define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0 4286 #define RCC_FINDIV44CFGR_FINDIV44EN BIT(6) 4287 4288 /* RCC_FINDIV45CFGR register fields */ 4289 #define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0) 4290 #define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0 4291 #define RCC_FINDIV45CFGR_FINDIV45EN BIT(6) 4292 4293 /* RCC_FINDIV46CFGR register fields */ 4294 #define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0) 4295 #define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0 4296 #define RCC_FINDIV46CFGR_FINDIV46EN BIT(6) 4297 4298 /* RCC_FINDIV47CFGR register fields */ 4299 #define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0) 4300 #define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0 4301 #define RCC_FINDIV47CFGR_FINDIV47EN BIT(6) 4302 4303 /* RCC_FINDIV48CFGR register fields */ 4304 #define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0) 4305 #define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0 4306 #define RCC_FINDIV48CFGR_FINDIV48EN BIT(6) 4307 4308 /* RCC_FINDIV49CFGR register fields */ 4309 #define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0) 4310 #define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0 4311 #define RCC_FINDIV49CFGR_FINDIV49EN BIT(6) 4312 4313 /* RCC_FINDIV50CFGR register fields */ 4314 #define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0) 4315 #define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0 4316 #define RCC_FINDIV50CFGR_FINDIV50EN BIT(6) 4317 4318 /* RCC_FINDIV51CFGR register fields */ 4319 #define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0) 4320 #define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0 4321 #define RCC_FINDIV51CFGR_FINDIV51EN BIT(6) 4322 4323 /* RCC_FINDIV52CFGR register fields */ 4324 #define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0) 4325 #define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0 4326 #define RCC_FINDIV52CFGR_FINDIV52EN BIT(6) 4327 4328 /* RCC_FINDIV53CFGR register fields */ 4329 #define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0) 4330 #define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0 4331 #define RCC_FINDIV53CFGR_FINDIV53EN BIT(6) 4332 4333 /* RCC_FINDIV54CFGR register fields */ 4334 #define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0) 4335 #define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0 4336 #define RCC_FINDIV54CFGR_FINDIV54EN BIT(6) 4337 4338 /* RCC_FINDIV55CFGR register fields */ 4339 #define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0) 4340 #define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0 4341 #define RCC_FINDIV55CFGR_FINDIV55EN BIT(6) 4342 4343 /* RCC_FINDIV56CFGR register fields */ 4344 #define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0) 4345 #define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0 4346 #define RCC_FINDIV56CFGR_FINDIV56EN BIT(6) 4347 4348 /* RCC_FINDIV57CFGR register fields */ 4349 #define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0) 4350 #define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0 4351 #define RCC_FINDIV57CFGR_FINDIV57EN BIT(6) 4352 4353 /* RCC_FINDIV58CFGR register fields */ 4354 #define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0) 4355 #define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0 4356 #define RCC_FINDIV58CFGR_FINDIV58EN BIT(6) 4357 4358 /* RCC_FINDIV59CFGR register fields */ 4359 #define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0) 4360 #define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0 4361 #define RCC_FINDIV59CFGR_FINDIV59EN BIT(6) 4362 4363 /* RCC_FINDIV60CFGR register fields */ 4364 #define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0) 4365 #define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0 4366 #define RCC_FINDIV60CFGR_FINDIV60EN BIT(6) 4367 4368 /* RCC_FINDIV61CFGR register fields */ 4369 #define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0) 4370 #define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0 4371 #define RCC_FINDIV61CFGR_FINDIV61EN BIT(6) 4372 4373 /* RCC_FINDIV62CFGR register fields */ 4374 #define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0) 4375 #define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0 4376 #define RCC_FINDIV62CFGR_FINDIV62EN BIT(6) 4377 4378 /* RCC_FINDIV63CFGR register fields */ 4379 #define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0) 4380 #define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0 4381 #define RCC_FINDIV63CFGR_FINDIV63EN BIT(6) 4382 4383 /* RCC_FINDIVxCFGR register fields */ 4384 #define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0) 4385 #define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0 4386 #define RCC_FINDIVxCFGR_FINDIVxEN BIT(6) 4387 4388 /* RCC_FCALCOBS0CFGR register fields */ 4389 #define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0) 4390 #define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0 4391 #define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) 4392 #define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8 4393 #define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15) 4394 #define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16) 4395 #define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17) 4396 #define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18) 4397 #define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) 4398 #define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22 4399 #define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25) 4400 #define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26) 4401 4402 /* RCC_FCALCOBS1CFGR register fields */ 4403 #define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0) 4404 #define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0 4405 #define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) 4406 #define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8 4407 #define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16) 4408 #define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18) 4409 #define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) 4410 #define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22 4411 #define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26) 4412 #define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27) 4413 4414 /* RCC_FCALCREFCFGR register fields */ 4415 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0) 4416 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0 4417 4418 /* RCC_FCALCCR1 register fields */ 4419 #define RCC_FCALCCR1_FCALCRUN BIT(0) 4420 4421 /* RCC_FCALCCR2 register fields */ 4422 #define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3) 4423 #define RCC_FCALCCR2_FCALCMD_SHIFT 3 4424 #define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11) 4425 #define RCC_FCALCCR2_FCALCTWC_SHIFT 11 4426 #define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17) 4427 #define RCC_FCALCCR2_FCALCTYP_SHIFT 17 4428 4429 /* RCC_FCALCSR register fields */ 4430 #define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0) 4431 #define RCC_FCALCSR_FVAL_SHIFT 0 4432 #define RCC_FCALCSR_FCALCSTS BIT(19) 4433 4434 /* RCC_PLL4CFGR1 register fields */ 4435 #define RCC_PLL4CFGR1_SSMODRST BIT(0) 4436 #define RCC_PLL4CFGR1_PLLEN BIT(8) 4437 #define RCC_PLL4CFGR1_PLLRDY BIT(24) 4438 #define RCC_PLL4CFGR1_CKREFST BIT(28) 4439 4440 /* RCC_PLL4CFGR2 register fields */ 4441 #define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4442 #define RCC_PLL4CFGR2_FREFDIV_SHIFT 0 4443 #define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4444 #define RCC_PLL4CFGR2_FBDIV_SHIFT 16 4445 4446 /* RCC_PLL4CFGR3 register fields */ 4447 #define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4448 #define RCC_PLL4CFGR3_FRACIN_SHIFT 0 4449 #define RCC_PLL4CFGR3_DOWNSPREAD BIT(24) 4450 #define RCC_PLL4CFGR3_DACEN BIT(25) 4451 #define RCC_PLL4CFGR3_SSCGDIS BIT(26) 4452 4453 /* RCC_PLL4CFGR4 register fields */ 4454 #define RCC_PLL4CFGR4_DSMEN BIT(8) 4455 #define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9) 4456 #define RCC_PLL4CFGR4_BYPASS BIT(10) 4457 4458 /* RCC_PLL4CFGR5 register fields */ 4459 #define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4460 #define RCC_PLL4CFGR5_DIVVAL_SHIFT 0 4461 #define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4462 #define RCC_PLL4CFGR5_SPREAD_SHIFT 16 4463 4464 /* RCC_PLL4CFGR6 register fields */ 4465 #define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4466 #define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0 4467 4468 /* RCC_PLL4CFGR7 register fields */ 4469 #define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4470 #define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0 4471 4472 /* RCC_PLL5CFGR1 register fields */ 4473 #define RCC_PLL5CFGR1_SSMODRST BIT(0) 4474 #define RCC_PLL5CFGR1_PLLEN BIT(8) 4475 #define RCC_PLL5CFGR1_PLLRDY BIT(24) 4476 #define RCC_PLL5CFGR1_CKREFST BIT(28) 4477 4478 /* RCC_PLL5CFGR2 register fields */ 4479 #define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4480 #define RCC_PLL5CFGR2_FREFDIV_SHIFT 0 4481 #define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4482 #define RCC_PLL5CFGR2_FBDIV_SHIFT 16 4483 4484 /* RCC_PLL5CFGR3 register fields */ 4485 #define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4486 #define RCC_PLL5CFGR3_FRACIN_SHIFT 0 4487 #define RCC_PLL5CFGR3_DOWNSPREAD BIT(24) 4488 #define RCC_PLL5CFGR3_DACEN BIT(25) 4489 #define RCC_PLL5CFGR3_SSCGDIS BIT(26) 4490 4491 /* RCC_PLL5CFGR4 register fields */ 4492 #define RCC_PLL5CFGR4_DSMEN BIT(8) 4493 #define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9) 4494 #define RCC_PLL5CFGR4_BYPASS BIT(10) 4495 4496 /* RCC_PLL5CFGR5 register fields */ 4497 #define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4498 #define RCC_PLL5CFGR5_DIVVAL_SHIFT 0 4499 #define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4500 #define RCC_PLL5CFGR5_SPREAD_SHIFT 16 4501 4502 /* RCC_PLL5CFGR6 register fields */ 4503 #define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4504 #define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0 4505 4506 /* RCC_PLL5CFGR7 register fields */ 4507 #define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4508 #define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0 4509 4510 /* RCC_PLL6CFGR1 register fields */ 4511 #define RCC_PLL6CFGR1_SSMODRST BIT(0) 4512 #define RCC_PLL6CFGR1_PLLEN BIT(8) 4513 #define RCC_PLL6CFGR1_PLLRDY BIT(24) 4514 #define RCC_PLL6CFGR1_CKREFST BIT(28) 4515 4516 /* RCC_PLL6CFGR2 register fields */ 4517 #define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4518 #define RCC_PLL6CFGR2_FREFDIV_SHIFT 0 4519 #define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4520 #define RCC_PLL6CFGR2_FBDIV_SHIFT 16 4521 4522 /* RCC_PLL6CFGR3 register fields */ 4523 #define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4524 #define RCC_PLL6CFGR3_FRACIN_SHIFT 0 4525 #define RCC_PLL6CFGR3_DOWNSPREAD BIT(24) 4526 #define RCC_PLL6CFGR3_DACEN BIT(25) 4527 #define RCC_PLL6CFGR3_SSCGDIS BIT(26) 4528 4529 /* RCC_PLL6CFGR4 register fields */ 4530 #define RCC_PLL6CFGR4_DSMEN BIT(8) 4531 #define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9) 4532 #define RCC_PLL6CFGR4_BYPASS BIT(10) 4533 4534 /* RCC_PLL6CFGR5 register fields */ 4535 #define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4536 #define RCC_PLL6CFGR5_DIVVAL_SHIFT 0 4537 #define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4538 #define RCC_PLL6CFGR5_SPREAD_SHIFT 16 4539 4540 /* RCC_PLL6CFGR6 register fields */ 4541 #define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4542 #define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0 4543 4544 /* RCC_PLL6CFGR7 register fields */ 4545 #define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4546 #define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0 4547 4548 /* RCC_PLL7CFGR1 register fields */ 4549 #define RCC_PLL7CFGR1_SSMODRST BIT(0) 4550 #define RCC_PLL7CFGR1_PLLEN BIT(8) 4551 #define RCC_PLL7CFGR1_PLLRDY BIT(24) 4552 #define RCC_PLL7CFGR1_CKREFST BIT(28) 4553 4554 /* RCC_PLL7CFGR2 register fields */ 4555 #define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4556 #define RCC_PLL7CFGR2_FREFDIV_SHIFT 0 4557 #define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4558 #define RCC_PLL7CFGR2_FBDIV_SHIFT 16 4559 4560 /* RCC_PLL7CFGR3 register fields */ 4561 #define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4562 #define RCC_PLL7CFGR3_FRACIN_SHIFT 0 4563 #define RCC_PLL7CFGR3_DOWNSPREAD BIT(24) 4564 #define RCC_PLL7CFGR3_DACEN BIT(25) 4565 #define RCC_PLL7CFGR3_SSCGDIS BIT(26) 4566 4567 /* RCC_PLL7CFGR4 register fields */ 4568 #define RCC_PLL7CFGR4_DSMEN BIT(8) 4569 #define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9) 4570 #define RCC_PLL7CFGR4_BYPASS BIT(10) 4571 4572 /* RCC_PLL7CFGR5 register fields */ 4573 #define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4574 #define RCC_PLL7CFGR5_DIVVAL_SHIFT 0 4575 #define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4576 #define RCC_PLL7CFGR5_SPREAD_SHIFT 16 4577 4578 /* RCC_PLL7CFGR6 register fields */ 4579 #define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4580 #define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0 4581 4582 /* RCC_PLL7CFGR7 register fields */ 4583 #define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4584 #define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0 4585 4586 /* RCC_PLL8CFGR1 register fields */ 4587 #define RCC_PLL8CFGR1_SSMODRST BIT(0) 4588 #define RCC_PLL8CFGR1_PLLEN BIT(8) 4589 #define RCC_PLL8CFGR1_PLLRDY BIT(24) 4590 #define RCC_PLL8CFGR1_CKREFST BIT(28) 4591 4592 /* RCC_PLL8CFGR2 register fields */ 4593 #define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4594 #define RCC_PLL8CFGR2_FREFDIV_SHIFT 0 4595 #define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4596 #define RCC_PLL8CFGR2_FBDIV_SHIFT 16 4597 4598 /* RCC_PLL8CFGR3 register fields */ 4599 #define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4600 #define RCC_PLL8CFGR3_FRACIN_SHIFT 0 4601 #define RCC_PLL8CFGR3_DOWNSPREAD BIT(24) 4602 #define RCC_PLL8CFGR3_DACEN BIT(25) 4603 #define RCC_PLL8CFGR3_SSCGDIS BIT(26) 4604 4605 /* RCC_PLL8CFGR4 register fields */ 4606 #define RCC_PLL8CFGR4_DSMEN BIT(8) 4607 #define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9) 4608 #define RCC_PLL8CFGR4_BYPASS BIT(10) 4609 4610 /* RCC_PLL8CFGR5 register fields */ 4611 #define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4612 #define RCC_PLL8CFGR5_DIVVAL_SHIFT 0 4613 #define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4614 #define RCC_PLL8CFGR5_SPREAD_SHIFT 16 4615 4616 /* RCC_PLL8CFGR6 register fields */ 4617 #define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4618 #define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0 4619 4620 /* RCC_PLL8CFGR7 register fields */ 4621 #define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4622 #define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0 4623 4624 /* RCC_PLLxCFGR1 register fields */ 4625 #define RCC_PLLxCFGR1_SSMODRST BIT(0) 4626 #define RCC_PLLxCFGR1_PLLEN BIT(8) 4627 #define RCC_PLLxCFGR1_PLLRDY BIT(24) 4628 #define RCC_PLLxCFGR1_CKREFST BIT(28) 4629 4630 /* RCC_PLLxCFGR2 register fields */ 4631 #define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4632 #define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 4633 #define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) 4634 #define RCC_PLLxCFGR2_FBDIV_SHIFT 16 4635 4636 /* RCC_PLLxCFGR3 register fields */ 4637 #define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) 4638 #define RCC_PLLxCFGR3_FRACIN_SHIFT 0 4639 #define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) 4640 #define RCC_PLLxCFGR3_DACEN BIT(25) 4641 #define RCC_PLLxCFGR3_SSCGDIS BIT(26) 4642 4643 /* RCC_PLLxCFGR4 register fields */ 4644 #define RCC_PLLxCFGR4_DSMEN BIT(8) 4645 #define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) 4646 #define RCC_PLLxCFGR4_BYPASS BIT(10) 4647 4648 /* RCC_PLLxCFGR5 register fields */ 4649 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4650 #define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 4651 #define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) 4652 #define RCC_PLLxCFGR5_SPREAD_SHIFT 16 4653 4654 /* RCC_PLLxCFGR6 register fields */ 4655 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4656 #define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 4657 4658 /* RCC_PLLxCFGR7 register fields */ 4659 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4660 #define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 4661 4662 /* RCC_VERR register fields */ 4663 #define RCC_VERR_MINREV_MASK GENMASK_32(3, 0) 4664 #define RCC_VERR_MINREV_SHIFT 0 4665 #define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4) 4666 #define RCC_VERR_MAJREV_SHIFT 4 4667 4668 #endif /* STM32MP21_RCC_H */ 4669