1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 9 #include <ddrphy_phyinit.h> 10 11 #include <lib/mmio.h> 12 13 #include <platform_def.h> 14 15 /* 16 * Execute the Training Firmware 17 * 18 * The training firmware is executed with the procedure: 19 * 20 * -# Reset the firmware microcontroller by writing the MicroReset register to 21 * set the StallToMicro and ResetToMicro fields to 1 (all other fields should be 22 * zero). Then rewrite the registers so that only the StallToMicro remains set 23 * (all other fields should be zero). 24 * -# Begin execution of the training firmware by setting the MicroReset 25 * register to 0. 26 * -# Wait for the training firmware to complete by following the procedure implemented in 27 * ddrphy_phyinit_usercustom_g_waitfwdone() function. 28 * -# Halt the microcontroller. 29 * 30 * \return 0 on success. 31 */ ddrphy_phyinit_g_execfw(void)32int ddrphy_phyinit_g_execfw(void) 33 { 34 int ret; 35 36 /* 37 * 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the 38 * StallToMicro and ResetToMicro fields to 1 (all other fields should be zero). 39 * Then rewrite the CSR so that only the StallToMicro remains set (all other fields should 40 * be zero). 41 */ 42 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), 43 CSR_STALLTOMICRO_MASK); 44 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 45 CSR_RESETTOMICRO_MASK | CSR_STALLTOMICRO_MASK); 46 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 47 CSR_STALLTOMICRO_MASK); 48 49 /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 0 */ 50 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 0x0U); 51 52 /* 53 * 3. Wait for the training firmware to complete by following the procedure 54 * implemented in ddrphy_phyinit_usercustom_g_waitfwdone() function. 55 */ 56 ret = ddrphy_phyinit_usercustom_g_waitfwdone(); 57 if (ret != 0) { 58 return ret; 59 } 60 61 /* 4. Halt the microcontroller */ 62 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 63 CSR_STALLTOMICRO_MASK); 64 65 return 0; 66 } 67