1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 #include "mp_precomp.h"
22 #include "../phydm_precomp.h"
23
24
25
26 /*---------------------------Define Local Constant---------------------------*/
27 // 2010/04/25 MH Define the max tx power tracking tx agc power.
28 #define ODM_TXPWRTRACK_MAX_IDX8723B 6
29
30 // MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0]
31 #define PATH_S0 1 // RF_PATH_B
32 #define IDX_0xC94 0
33 #define IDX_0xC80 1
34 #define IDX_0xC4C 2
35 #define IDX_0xC14 0
36 #define IDX_0xCA0 1
37 #define KEY 0
38 #define VAL 1
39
40 // MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1]
41 #define PATH_S1 0 // RF_PATH_A
42 #define IDX_0xC9C 0
43 #define IDX_0xC88 1
44 #define IDX_0xC4C 2
45 #define IDX_0xC1C 0
46 #define IDX_0xC78 1
47
48
49 /*---------------------------Define Local Constant---------------------------*/
50
51
52 //3============================================================
53 //3 Tx Power Tracking
54 //3============================================================
55
56
setIqkMatrix_8723B(PDM_ODM_T pDM_Odm,u1Byte OFDM_index,u1Byte RFPath,s4Byte IqkResult_X,s4Byte IqkResult_Y)57 void setIqkMatrix_8723B(
58 PDM_ODM_T pDM_Odm,
59 u1Byte OFDM_index,
60 u1Byte RFPath,
61 s4Byte IqkResult_X,
62 s4Byte IqkResult_Y
63 )
64 {
65 s4Byte ele_A=0, ele_D, ele_C=0, value32;
66
67 if (OFDM_index >= OFDM_TABLE_SIZE)
68 OFDM_index = OFDM_TABLE_SIZE-1;
69
70 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
71
72 //new element A = element D x X
73 if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
74 {
75 if ((IqkResult_X & 0x00000200) != 0) //consider minus
76 IqkResult_X = IqkResult_X | 0xFFFFFC00;
77 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
78
79 //new element C = element D x Y
80 if ((IqkResult_Y & 0x00000200) != 0)
81 IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
82 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
83
84 //if (RFPath == ODM_RF_PATH_A)
85 switch (RFPath)
86 {
87 case ODM_RF_PATH_A:
88 //wirte new elements A, C, D to regC80 and regC94, element B is always 0
89 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
90 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
91
92 value32 = (ele_C&0x000003C0)>>6;
93 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
94
95 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
96 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
97 break;
98 case ODM_RF_PATH_B:
99 //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
100 value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
101 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
102
103 value32 = (ele_C&0x000003C0)>>6;
104 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
105
106 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
107 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
108
109 break;
110 default:
111 break;
112 }
113 }
114 else
115 {
116 switch (RFPath)
117 {
118 case ODM_RF_PATH_A:
119 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
120 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
121 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);
122 break;
123
124 case ODM_RF_PATH_B:
125 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
126 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
127 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);
128 break;
129
130 default:
131 break;
132 }
133 }
134
135 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
136 (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));
137 }
138
139
140 VOID
setCCKFilterCoefficient(PDM_ODM_T pDM_Odm,u1Byte CCKSwingIndex)141 setCCKFilterCoefficient(
142 PDM_ODM_T pDM_Odm,
143 u1Byte CCKSwingIndex
144 )
145 {
146 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
147 {
148 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]);
149 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]);
150 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]);
151 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]);
152 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]);
153 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]);
154 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]);
155 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]);
156 }
157 else
158 {
159 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]);
160 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]);
161 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]);
162 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]);
163 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]);
164 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]);
165 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]);
166 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]);
167 }
168 }
169
DoIQK_8723B(PVOID pDM_VOID,u1Byte DeltaThermalIndex,u1Byte ThermalValue,u1Byte Threshold)170 void DoIQK_8723B(
171 PVOID pDM_VOID,
172 u1Byte DeltaThermalIndex,
173 u1Byte ThermalValue,
174 u1Byte Threshold
175 )
176 {
177 #if 0 // mark by Lucas@SD4 20140128, suggested by Allen@SD3
178 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
179 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
180 PADAPTER Adapter = pDM_Odm->Adapter;
181 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
182 #endif
183
184 ODM_ResetIQKResult(pDM_Odm);
185
186 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
187 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
188 #if USE_WORKITEM
189 PlatformAcquireMutex(&pHalData->mxChnlBwControl);
190 #else
191 PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
192 #endif
193 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
194 PlatformAcquireMutex(&pHalData->mxChnlBwControl);
195 #endif
196 #endif
197
198
199 pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;
200 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
201 PHY_IQCalibrate_8723B(pDM_Odm, FALSE, FALSE);
202 #else
203 PHY_IQCalibrate_8723B(Adapter, FALSE, FALSE);
204 #endif
205
206 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
207 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
208 #if USE_WORKITEM
209 PlatformReleaseMutex(&pHalData->mxChnlBwControl);
210 #else
211 PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
212 #endif
213 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
214 PlatformReleaseMutex(&pHalData->mxChnlBwControl);
215 #endif
216 #endif
217 #endif // #if 0
218 }
219
220 /*-----------------------------------------------------------------------------
221 * Function: odm_TxPwrTrackSetPwr88E()
222 *
223 * Overview: 88E change all channel tx power accordign to flag.
224 * OFDM & CCK are all different.
225 *
226 * Input: NONE
227 *
228 * Output: NONE
229 *
230 * Return: NONE
231 *
232 * Revised History:
233 * When Who Remark
234 * 04/23/2012 MHC Create Version 0.
235 *
236 *---------------------------------------------------------------------------*/
237 VOID
ODM_TxPwrTrackSetPwr_8723B(IN PVOID pDM_VOID,PWRTRACK_METHOD Method,u1Byte RFPath,u1Byte ChannelMappedIndex)238 ODM_TxPwrTrackSetPwr_8723B(
239 IN PVOID pDM_VOID,
240 PWRTRACK_METHOD Method,
241 u1Byte RFPath,
242 u1Byte ChannelMappedIndex
243 )
244 {
245 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
246 PADAPTER Adapter = pDM_Odm->Adapter;
247 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
248 u1Byte PwrTrackingLimit_OFDM = 34; //+0dB
249 u1Byte PwrTrackingLimit_CCK= 28; //-2dB
250 u1Byte TxRate = 0xFF;
251 u1Byte Final_OFDM_Swing_Index = 0;
252 u1Byte Final_CCK_Swing_Index = 0;
253 u1Byte i = 0;
254 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
255
256 if (pDM_Odm->mp_mode == TRUE) {
257 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
258 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
259 #if (MP_DRIVER == 1)
260 PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
261
262 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
263 #endif
264 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
265 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
266
267 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
268 #endif
269 #endif
270 } else {
271 u2Byte rate = *(pDM_Odm->pForcedDataRate);
272
273 if (!rate) { /*auto rate*/
274 if (rate != 0xFF) {
275 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
276 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
277 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
278 TxRate = HwRateToMRate(pDM_Odm->TxRate);
279 #endif
280 }
281 } else { /*force rate*/
282 TxRate = (u1Byte)rate;
283 }
284 }
285
286 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
287 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n"));
288
289 if(TxRate != 0xFF)
290 {
291 //2 CCK
292 if((TxRate >= MGN_1M)&&(TxRate <= MGN_11M))
293 PwrTrackingLimit_CCK = 28; //-2dB
294 //2 OFDM
295 else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M))
296 PwrTrackingLimit_OFDM= 36; //+3dB
297 else if(TxRate == MGN_54M)
298 PwrTrackingLimit_OFDM= 34; //+2dB
299
300 //2 HT
301 else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK
302 PwrTrackingLimit_OFDM= 38; //+4dB
303 else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM
304 PwrTrackingLimit_OFDM= 36; //+3dB
305 else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM
306 PwrTrackingLimit_OFDM= 34; //+2dB
307
308 else
309 PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/
310 }
311 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM));
312
313 if (Method == TXAGC)
314 {
315 u1Byte rf = 0;
316 u4Byte pwr = 0, TxAGC = 0;
317 PADAPTER Adapter = pDM_Odm->Adapter;
318
319 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH=%d\n", *(pDM_Odm->pChannel)));
320
321 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
322
323 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))
324 if (pDM_Odm->mp_mode == TRUE)
325 {
326 pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);
327 pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[RFPath];
328 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr);
329 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
330 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);
331 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: CCK Tx-rf(A) Power = 0x%x\n", TxAGC));
332
333 pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);
334 pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[RFPath] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RFPath]);
335 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
336 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
337 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
338 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
339 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
340 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
341 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
342 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8723B: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC));
343 }
344 else
345 {
346 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;
347 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;
348
349 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK);
350 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM);
351 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7);
352 }
353 #endif
354 }
355 else if (Method == BBSWING)
356 {
357 Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
358 Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
359
360 // Adjust BB swing by OFDM IQ matrix
361 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
362 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
363 else if (Final_OFDM_Swing_Index <= 0)
364 Final_OFDM_Swing_Index = 0;
365
366 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
367 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
368 else if (pRFCalibrateInfo->BbSwingIdxCck <= 0)
369 Final_CCK_Swing_Index = 0;
370
371 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
372 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
373 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
374
375 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
376
377 }
378 else if (Method == MIX_MODE)
379 {
380 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
381 ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
382 pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath));
383
384 Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
385 Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
386
387 if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit
388 {
389 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
390
391 setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath,
392 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
393 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
394
395 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;
396 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );
397 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );
398
399 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
400 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n",
401 PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]));
402 }
403 else if (Final_OFDM_Swing_Index <= 0)
404 {
405 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;
406
407 setIqkMatrix_8723B(pDM_Odm, 0, RFPath,
408 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
409 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
410
411 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;
412 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );
413 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );
414
415 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
416 ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n",
417 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]));
418 }
419 else
420 {
421 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath,
422 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
423 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
424
425 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
426 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index));
427
428 if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/
429 {
430 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0;
431 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM );
432 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7 );
433 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE;
434
435 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
436 ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n"));
437 }
438 }
439
440 if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK)
441 {
442 pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
443 setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK);
444 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;
445 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );
446
447 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
448 ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx));
449 }
450 else if(Final_CCK_Swing_Index <= 0) // Lowest CCK Index = 0
451 {
452 pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
453 setCCKFilterCoefficient(pDM_Odm, 0);
454 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;
455 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );
456
457 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
458 ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx));
459 }
460 else
461 {
462 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index);
463
464 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
465 ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index));
466
467 if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) /*If TxAGC has changed, reset TxAGC again*/
468 {
469 pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;
470 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK );
471 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE;
472
473 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
474 ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n"));
475 }
476 }
477 }
478 else
479 {
480 return; // This method is not supported.
481 }
482 }
483
484 VOID
GetDeltaSwingTable_8723B(IN PVOID pDM_VOID,OUT pu1Byte * TemperatureUP_A,OUT pu1Byte * TemperatureDOWN_A,OUT pu1Byte * TemperatureUP_B,OUT pu1Byte * TemperatureDOWN_B)485 GetDeltaSwingTable_8723B(
486 IN PVOID pDM_VOID,
487 OUT pu1Byte *TemperatureUP_A,
488 OUT pu1Byte *TemperatureDOWN_A,
489 OUT pu1Byte *TemperatureUP_B,
490 OUT pu1Byte *TemperatureDOWN_B
491 )
492 {
493 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
494 PADAPTER Adapter = pDM_Odm->Adapter;
495 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
496 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
497 u1Byte TxRate = 0xFF;
498 u1Byte channel = pHalData->CurrentChannel;
499
500 if (pDM_Odm->mp_mode == TRUE) {
501 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
502 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
503 #if (MP_DRIVER == 1)
504 PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
505
506 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
507 #endif
508 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
509 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
510
511 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
512 #endif
513 #endif
514 } else {
515 u2Byte rate = *(pDM_Odm->pForcedDataRate);
516
517 if (!rate) { /*auto rate*/
518 if (rate != 0xFF) {
519 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
520 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
521 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
522 TxRate = HwRateToMRate(pDM_Odm->TxRate);
523 #endif
524 }
525 } else { /*force rate*/
526 TxRate = (u1Byte)rate;
527 }
528 }
529
530 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
531
532 if ( 1 <= channel && channel <= 14) {
533 if (IS_CCK_RATE(TxRate)) {
534 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
535 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
536 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
537 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
538 } else {
539 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
540 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
541 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
542 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
543 }
544 } else {
545 *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
546 *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
547 *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
548 *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
549 }
550
551 return;
552 }
553
554
ConfigureTxpowerTrack_8723B(PTXPWRTRACK_CFG pConfig)555 void ConfigureTxpowerTrack_8723B(
556 PTXPWRTRACK_CFG pConfig
557 )
558 {
559 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
560 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
561 pConfig->Threshold_IQK = IQK_THRESHOLD;
562 pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B;
563 pConfig->RfPathCount = MAX_PATH_NUM_8723B;
564 pConfig->ThermalRegAddr = RF_T_METER_8723B;
565
566 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B;
567 pConfig->DoIQK = DoIQK_8723B;
568 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B;
569 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B;
570 }
571
572 //1 7. IQK
573 #define MAX_TOLERANCE 5
574 #define IQK_DELAY_TIME 1 //ms
575
576 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_IQK_8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN configPathB,IN u1Byte RF_Path)577 phy_PathA_IQK_8723B(
578 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
579 IN PDM_ODM_T pDM_Odm,
580 #else
581 IN PADAPTER pAdapter,
582 #endif
583 IN BOOLEAN configPathB,
584 IN u1Byte RF_Path
585 )
586 {
587 u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/;
588 u1Byte result = 0x00;
589
590 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
591 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
592 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
593 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
594 #endif
595 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
596 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
597 #endif
598 #endif
599
600
601 // Save RF Path
602 Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);
603
604 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
605
606 //leave IQK mode
607 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
608
609 // enable path A PA in TXIQK mode
610 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
611 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 );
612 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f );
613 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );
614 // disable path B PA in TXIQK mode
615 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 );
616 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1 );
617
618 //1 Tx IQK
619 //IQK setting
620 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
621 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
622 //path-A IQK setting
623 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));
624 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
625 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
626 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
627 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
628 // ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214010a);
629 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea);
630 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
631 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
632 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
633
634 //LO calibration setting
635 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
636 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
637
638 //enter IQK mode
639 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
640
641 //Ant switch
642 if (configPathB || (RF_Path == 0))
643 // wifi switch to S1
644 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);
645 else
646 // wifi switch to S0
647 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
648
649 //GNT_BT = 0
650 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);
651
652 //One shot, path A LOK & IQK
653 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
654 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
655 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
656
657 // delay x ms
658 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B));
659 //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);
660 ODM_delay_ms(IQK_DELAY_TIME_8723B);
661
662 //restore Ant Path
663 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);
664 //GNT_BT = 1
665 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);
666
667 //leave IQK mode
668 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
669
670
671 // Check failed
672 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
673 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
674 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
675 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
676 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
677 //monitor image power before & after IQK
678 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
679 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));
680
681
682 if(!(regEAC & BIT28) &&
683 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
684 (((regE9C & 0x03FF0000)>>16) != 0x42))
685 result |= 0x01;
686
687 return result;
688
689 #if 0
690 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
691 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
692 (((regEAC & 0x03FF0000)>>16) != 0x36))
693 result |= 0x02;
694 else
695 RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
696 #endif
697 }
698
699 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN configPathB,IN u1Byte RF_Path)700 phy_PathA_RxIQK8723B(
701 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
702 IN PDM_ODM_T pDM_Odm,
703 #else
704 IN PADAPTER pAdapter,
705 #endif
706 IN BOOLEAN configPathB,
707 IN u1Byte RF_Path
708 )
709 {
710 u4Byte regEAC, regE94, regE9C, regEA4, u4tmp,tmp, Path_SEL_BB;
711 u1Byte result = 0x00;
712 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
713 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
714 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
715 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
716 #endif
717 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
718 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
719 #endif
720 #endif
721 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));
722
723 // Save RF Path
724 Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);
725
726 //leave IQK mode
727 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
728
729 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n"));
730 //1 Get TXIMR setting
731 //modify RXIQK mode table
732 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));
733 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
734 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
735 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
736 //LNA2 off, PA on for Dcut
737 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
738 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);
739 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
740
741 //IQK setting
742 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
743 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
744
745 //path-A IQK setting
746 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
747 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
748 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
749 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
750
751 // ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
752 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0);
753 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
754 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
755 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
756
757 //LO calibration setting
758 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
759 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
760
761 //enter IQK mode
762 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
763
764 //Ant switch
765 if (configPathB || (RF_Path == 0))
766 // wifi switch to S1
767 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);
768 else
769 // wifi switch to S0
770 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
771
772 //GNT_BT = 0
773 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);
774
775 //One shot, path A LOK & IQK
776 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
777 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
778 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
779
780 // delay x ms
781 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B));
782 //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);
783 ODM_delay_ms(IQK_DELAY_TIME_8723B);
784
785 //restore Ant Path
786 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);
787 //GNT_BT = 1
788 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);
789
790 //leave IQK mode
791 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
792
793 // Check failed
794 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
795 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
796 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
797 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
798 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
799 //monitor image power before & after IQK
800 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
801 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));
802
803 if(!(regEAC & BIT28) &&
804 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
805 (((regE9C & 0x03FF0000)>>16) != 0x42))
806
807 result |= 0x01;
808 else //if Tx not OK, ignore Rx
809 return result;
810
811
812 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
813 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);
814 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));
815
816
817 //1 RX IQK
818 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n"));
819
820 //modify RXIQK mode table
821 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
822 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
823 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
824 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
825 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );
826 //LAN2 on, PA off for Dcut
827 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77 );
828 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);
829
830 //PA, PAD setting
831 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80 );
832 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f );
833
834
835 //IQK setting
836 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
837
838 //path-A IQK setting
839 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
840 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
841 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
842 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
843
844 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
845 // ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);
846 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);
847 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
848 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
849
850 //LO calibration setting
851 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
852 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
853
854 //enter IQK mode
855 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
856
857 //Ant switch
858 if (configPathB || (RF_Path == 0))
859 // wifi switch to S1
860 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);
861 else
862 // wifi switch to S0
863 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
864
865 //GNT_BT = 0
866 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);
867
868 //One shot, path A LOK & IQK
869 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
870 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
871 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
872
873 // delay x ms
874 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
875 //PlatformStallExecution(IQK_DELAY_TIME_8723B*1000);
876 ODM_delay_ms(IQK_DELAY_TIME_8723B);
877
878 //restore Ant Path
879 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);
880 //GNT_BT = 1
881 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);
882
883 //leave IQK mode
884 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
885
886 // Check failed
887 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
888 regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
889 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
890 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));
891 //monitor image power before & after IQK
892 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
893 ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord)));
894
895 // PA/PAD controlled by 0x0
896 //leave IQK mode
897 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
898 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780 );
899
900 /* Allen 20141201 */
901 tmp=(regEAC & 0x03FF0000)>>16;
902 if ((tmp & 0x200)> 0)
903 tmp = 0x400 - tmp;
904
905 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
906 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
907 (((regEAC & 0x03FF0000)>>16) != 0x36)&&
908 (((regEA4 & 0x03FF0000)>>16) < 0x11a) &&
909 (((regEA4 & 0x03FF0000)>>16) > 0xe6) &&
910 (tmp < 0x1a))
911 result |= 0x02;
912 else //if Tx not OK, ignore Rx
913 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n"));
914
915
916 return result;
917
918
919 }
920
921 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathB_IQK_8723B(IN PDM_ODM_T pDM_Odm)922 phy_PathB_IQK_8723B(
923 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
924 IN PDM_ODM_T pDM_Odm
925 #else
926 IN PADAPTER pAdapter
927 #endif
928 )
929 {
930 u4Byte regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/;
931 u1Byte result = 0x00;
932 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
933 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
934 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
935 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
936 #endif
937 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
938 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
939 #endif
940 #endif
941 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
942
943 // Save RF Path
944 Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);
945
946 //leave IQK mode
947 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
948
949 // in TXIQK mode
950 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );
951 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 );
952 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f );
953 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 );
954 // enable path B PA in TXIQK mode
955 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
956 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1);
957
958
959
960 //1 Tx IQK
961 //IQK setting
962 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
963 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
964 //path-A IQK setting
965 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n"));
966 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
967 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
968 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
969 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
970
971 // ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140114);
972 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ea);
973 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
974 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
975 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
976
977 //LO calibration setting
978 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
979 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
980
981 //enter IQK mode
982 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
983
984 //switch to path B
985 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
986 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);
987
988 //GNT_BT = 0
989 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);
990
991 //One shot, path B LOK & IQK
992 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));
993 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
994 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
995
996 // delay x ms
997 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));
998 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
999 ODM_delay_ms(IQK_DELAY_TIME_8723B);
1000
1001 //restore Ant Path
1002 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);
1003 //GNT_BT = 1
1004 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);
1005
1006 //leave IQK mode
1007 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1008
1009 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord)));
1010
1011
1012 // Check failed
1013 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
1014 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
1015 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
1016 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
1017 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
1018 //monitor image power before & after IQK
1019 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
1020 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));
1021
1022 if(!(regEAC & BIT28) &&
1023 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
1024 (((regE9C & 0x03FF0000)>>16) != 0x42))
1025 result |= 0x01;
1026
1027 return result;
1028
1029 #if 0
1030 if(!(regEAC & BIT30) &&
1031 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
1032 (((regECC & 0x03FF0000)>>16) != 0x36))
1033 result |= 0x02;
1034 else
1035 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
1036
1037 #endif
1038 }
1039
1040
1041
1042 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathB_RxIQK8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN configPathB)1043 phy_PathB_RxIQK8723B(
1044 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1045 IN PDM_ODM_T pDM_Odm,
1046 #else
1047 IN PADAPTER pAdapter,
1048 #endif
1049 IN BOOLEAN configPathB
1050 )
1051 {
1052 u4Byte regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB;
1053 u1Byte result = 0x00;
1054 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1055 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1056 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1057 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1058 #endif
1059 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1060 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1061 #endif
1062 #endif
1063 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n"));
1064
1065 // Save RF Path
1066 Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);
1067 //leave IQK mode
1068 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1069
1070 //switch to path B
1071 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
1072
1073 //1 Get TXIMR setting
1074 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n"));
1075 //modify RXIQK mode table
1076 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));
1077 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );
1078 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
1079 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );
1080 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7 );
1081 //open PA S1 & SMIXER
1082 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 );
1083 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fcd );
1084
1085
1086 //IQK setting
1087 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1088 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1089
1090
1091 //path-B IQK setting
1092 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
1093 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
1094 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1095 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1096
1097 // ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f );
1098 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160ff0);
1099 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28110000);
1100 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
1101 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
1102
1103 //LO calibration setting
1104 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
1105 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
1106
1107 //enter IQK mode
1108 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1109
1110 //switch to path B
1111 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
1112 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);
1113
1114 //GNT_BT = 0
1115 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);
1116
1117 //One shot, path B TXIQK @ RXIQK
1118 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));
1119 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
1120 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1121
1122
1123 // delay x ms
1124 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
1125 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
1126 ODM_delay_ms(IQK_DELAY_TIME_8723B);
1127
1128 //restore Ant Path
1129 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);
1130 //GNT_BT = 1
1131 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);
1132
1133 //leave IQK mode
1134 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1135
1136 // Check failed
1137 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
1138 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
1139 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
1140 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
1141 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C));
1142 //monitor image power before & after IQK
1143 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
1144 ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord)));
1145
1146
1147 if(!(regEAC & BIT28) &&
1148 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
1149 (((regE9C & 0x03FF0000)>>16) != 0x42))
1150 result |= 0x01;
1151 else //if Tx not OK, ignore Rx
1152 return result;
1153
1154
1155
1156 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
1157 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);
1158 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));
1159
1160
1161 //1 RX IQK
1162 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n"));
1163
1164 //modify RXIQK mode table
1165 //<20121009, Kordan> RF Mode = 3
1166 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1167 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
1168 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
1169 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
1170 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77);
1171 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0);
1172
1173 //open PA S1 & close SMIXER
1174 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
1175 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60ebd);
1176
1177 //PA, PAD setting
1178 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
1179 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
1180
1181
1182
1183 //IQK setting
1184 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1185
1186 //path-B IQK setting
1187 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
1188 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
1189 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1190 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c);
1191
1192 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82110000);
1193 // ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281604c2);
1194 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x2816001f);
1195 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82110000);
1196 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x28110000);
1197
1198 //LO calibration setting
1199 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
1200 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1);
1201
1202 //enter IQK mode
1203 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1204
1205 //switch to path B
1206 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
1207 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0);
1208
1209 //GNT_BT = 0
1210 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00000800);
1211
1212 //One shot, path B LOK & IQK
1213 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n"));
1214 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
1215 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1216
1217 // delay x ms
1218 // ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
1219 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
1220 ODM_delay_ms(IQK_DELAY_TIME_8723B);
1221
1222 //restore Ant Path
1223 ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord,Path_SEL_BB);
1224 //GNT_BT = 1
1225 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, 0x00001800);
1226
1227 //leave IQK mode
1228 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1229
1230 // Check failed
1231 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
1232 regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);;
1233
1234 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
1235 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC));
1236 //monitor image power before & after IQK
1237 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
1238 ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord)));
1239
1240 // PA/PAD controlled by 0x0
1241 //leave IQK mode
1242 // ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x00000000);
1243 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180 );
1244
1245
1246
1247 #if 0
1248 if(!(regEAC & BIT31) &&
1249 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
1250 (((regEBC & 0x03FF0000)>>16) != 0x42) )
1251 result |= 0x01;
1252 else //if Tx not OK, ignore Rx
1253 return result;
1254 #endif
1255
1256
1257 /* Allen 20141201 */
1258 tmp=(regEAC & 0x03FF0000)>>16;
1259 if ((tmp & 0x200)> 0)
1260 tmp = 0x400 - tmp;
1261
1262 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
1263 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
1264 (((regEAC & 0x03FF0000)>>16) != 0x36) &&
1265 (((regEA4 & 0x03FF0000)>>16) < 0x11a) &&
1266 (((regEA4 & 0x03FF0000)>>16) > 0xe6) &&
1267 (tmp < 0x1a))
1268
1269 result |= 0x02;
1270 else
1271 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
1272
1273
1274 return result;
1275
1276
1277 }
1278
1279
1280 VOID
_PHY_PathAFillIQKMatrix8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bIQKOK,IN s4Byte result[][8],IN u1Byte final_candidate,IN BOOLEAN bTxOnly)1281 _PHY_PathAFillIQKMatrix8723B(
1282 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1283 IN PDM_ODM_T pDM_Odm,
1284 #else
1285 IN PADAPTER pAdapter,
1286 #endif
1287 IN BOOLEAN bIQKOK,
1288 IN s4Byte result[][8],
1289 IN u1Byte final_candidate,
1290 IN BOOLEAN bTxOnly
1291 )
1292 {
1293 u4Byte Oldval_0, X, TX0_A, reg;
1294 s4Byte Y, TX0_C;
1295 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1296 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1297 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1298 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1299 #endif
1300 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1301 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1302 #endif
1303 #endif
1304 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1305
1306 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
1307
1308 if(final_candidate == 0xFF)
1309 return;
1310
1311 else if(bIQKOK)
1312 {
1313 Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1314
1315 X = result[final_candidate][0];
1316 if ((X & 0x00000200) != 0)
1317 X = X | 0xFFFFFC00;
1318 TX0_A = (X * Oldval_0) >> 8;
1319 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
1320 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
1321
1322 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
1323
1324 Y = result[final_candidate][1];
1325 if ((Y & 0x00000200) != 0)
1326 Y = Y | 0xFFFFFC00;
1327
1328 //2 Tx IQC
1329 TX0_C = (Y * Oldval_0) >> 8;
1330 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
1331 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
1332 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1333 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord);
1334
1335 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
1336 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1337 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord);
1338
1339 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
1340 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1341 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord);
1342
1343 if(bTxOnly)
1344 {
1345 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n"));
1346
1347 // <20130226, Kordan> Saving RxIQC, otherwise not initialized.
1348 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1349 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);
1350 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1351 // pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);
1352 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100;
1353 return;
1354 }
1355
1356 reg = result[final_candidate][2];
1357 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
1358 if( RTL_ABS(reg ,0x100) >= 16)
1359 reg = 0x100;
1360 #endif
1361
1362 //2 Rx IQC
1363 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);
1364 reg = result[final_candidate][3] & 0x3F;
1365 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);
1366 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1367 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);
1368
1369 reg = (result[final_candidate][3] >> 6) & 0xF;
1370 ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
1371 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1372 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);
1373
1374 }
1375 }
1376
1377 VOID
_PHY_PathBFillIQKMatrix8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bIQKOK,IN s4Byte result[][8],IN u1Byte final_candidate,IN BOOLEAN bTxOnly)1378 _PHY_PathBFillIQKMatrix8723B(
1379 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1380 IN PDM_ODM_T pDM_Odm,
1381 #else
1382 IN PADAPTER pAdapter,
1383 #endif
1384 IN BOOLEAN bIQKOK,
1385 IN s4Byte result[][8],
1386 IN u1Byte final_candidate,
1387 IN BOOLEAN bTxOnly //do Tx only
1388 )
1389 {
1390 u4Byte Oldval_1, X, TX1_A, reg;
1391 s4Byte Y, TX1_C;
1392 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1393 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1394 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1395 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1396 #endif
1397 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1398 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1399 #endif
1400 #endif
1401 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1402
1403 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
1404
1405 if(final_candidate == 0xFF)
1406 return;
1407
1408 else if(bIQKOK)
1409 {
1410 Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
1411
1412 X = result[final_candidate][4];
1413 if ((X & 0x00000200) != 0)
1414 X = X | 0xFFFFFC00;
1415 TX1_A = (X * Oldval_1) >> 8;
1416 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
1417
1418 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
1419
1420 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
1421
1422 Y = result[final_candidate][5];
1423 if ((Y & 0x00000200) != 0)
1424 Y = Y | 0xFFFFFC00;
1425
1426 TX1_C = (Y * Oldval_1) >> 8;
1427 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
1428
1429 //2 Tx IQC
1430 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
1431 // pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE;
1432 // pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);
1433 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE;
1434 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord);
1435
1436 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
1437 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance;
1438 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord);
1439
1440 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
1441 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold;
1442 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord);
1443
1444 if(bTxOnly) {
1445 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n"));
1446
1447 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1448 // pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord);
1449 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100;
1450 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1451 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord);
1452 return;
1453 }
1454
1455 //2 Rx IQC
1456 reg = result[final_candidate][6];
1457 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
1458 reg = result[final_candidate][7] & 0x3F;
1459 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
1460 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance;
1461 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord);
1462
1463 reg = (result[final_candidate][7] >> 6) & 0xF;
1464 // ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);
1465 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta;
1466 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(ODM_GetBBReg(pDM_Odm,rOFDM0_RxIQExtAnta, bMaskDWord)& 0x0fffffff);
1467 }
1468 }
1469
1470 //
1471 // 2011/07/26 MH Add an API for testing IQK fail case.
1472 //
1473 // MP Already declare in odm.c
1474
1475 VOID
ODM_SetIQCbyRFpath(IN PDM_ODM_T pDM_Odm,IN u4Byte RFpath)1476 ODM_SetIQCbyRFpath(
1477 IN PDM_ODM_T pDM_Odm,
1478 IN u4Byte RFpath
1479 )
1480 {
1481
1482 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
1483
1484 if((pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0)&&
1485 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0))
1486 {
1487 if(RFpath) //S1: RFpath = 0, S0:RFpath = 1
1488 {
1489 //S0 TX IQC
1490 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]);
1491 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]);
1492 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]);
1493 //S0 RX IQC
1494 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]);
1495 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]);
1496 }
1497 else
1498 {
1499 //S1 TX IQC
1500 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]);
1501 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]);
1502 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]);
1503 //S1 RX IQC
1504 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]);
1505 ODM_SetBBReg(pDM_Odm, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]);
1506 }
1507 }
1508 }
1509
1510 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN)
1511 BOOLEAN
ODM_CheckPowerStatus(IN PADAPTER Adapter)1512 ODM_CheckPowerStatus(
1513 IN PADAPTER Adapter)
1514 {
1515 /*
1516 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1517 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1518 RT_RF_POWER_STATE rtState;
1519 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
1520
1521 // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
1522 if (pMgntInfo->init_adpt_in_progress == TRUE)
1523 {
1524 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
1525 return TRUE;
1526 }
1527
1528 //
1529 // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
1530 //
1531 rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
1532 if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
1533 {
1534 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop:%s/%d/%d\n",
1535 rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
1536 return FALSE;
1537 }
1538 */
1539 return TRUE;
1540 }
1541 #endif
1542
1543 VOID
_PHY_SaveADDARegisters8723B(IN PDM_ODM_T pDM_Odm,IN pu4Byte ADDAReg,IN pu4Byte ADDABackup,IN u4Byte RegisterNum)1544 _PHY_SaveADDARegisters8723B(
1545 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1546 IN PDM_ODM_T pDM_Odm,
1547 #else
1548 IN PADAPTER pAdapter,
1549 #endif
1550 IN pu4Byte ADDAReg,
1551 IN pu4Byte ADDABackup,
1552 IN u4Byte RegisterNum
1553 )
1554 {
1555 u4Byte i;
1556 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1557 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1558 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1559 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1560 #endif
1561 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1562 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1563 #endif
1564
1565 if (ODM_CheckPowerStatus(pAdapter) == FALSE)
1566 return;
1567 #endif
1568
1569 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
1570 for( i = 0 ; i < RegisterNum ; i++){
1571 ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);
1572 }
1573 }
1574
1575
1576 VOID
_PHY_SaveMACRegisters8723B(IN PDM_ODM_T pDM_Odm,IN pu4Byte MACReg,IN pu4Byte MACBackup)1577 _PHY_SaveMACRegisters8723B(
1578 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1579 IN PDM_ODM_T pDM_Odm,
1580 #else
1581 IN PADAPTER pAdapter,
1582 #endif
1583 IN pu4Byte MACReg,
1584 IN pu4Byte MACBackup
1585 )
1586 {
1587 u4Byte i;
1588 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1589 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1590 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1591 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1592 #endif
1593 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1594 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1595 #endif
1596 #endif
1597 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
1598 for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
1599 MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
1600 }
1601 MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);
1602
1603 }
1604
1605
1606 VOID
_PHY_ReloadADDARegisters8723B(IN PDM_ODM_T pDM_Odm,IN pu4Byte ADDAReg,IN pu4Byte ADDABackup,IN u4Byte RegiesterNum)1607 _PHY_ReloadADDARegisters8723B(
1608 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1609 IN PDM_ODM_T pDM_Odm,
1610 #else
1611 IN PADAPTER pAdapter,
1612 #endif
1613 IN pu4Byte ADDAReg,
1614 IN pu4Byte ADDABackup,
1615 IN u4Byte RegiesterNum
1616 )
1617 {
1618 u4Byte i;
1619 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1620 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1621 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1622 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1623 #endif
1624 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1625 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1626 #endif
1627 #endif
1628
1629 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
1630 for(i = 0 ; i < RegiesterNum; i++)
1631 {
1632 ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);
1633 }
1634 }
1635
1636 VOID
_PHY_ReloadMACRegisters8723B(IN PDM_ODM_T pDM_Odm,IN pu4Byte MACReg,IN pu4Byte MACBackup)1637 _PHY_ReloadMACRegisters8723B(
1638 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1639 IN PDM_ODM_T pDM_Odm,
1640 #else
1641 IN PADAPTER pAdapter,
1642 #endif
1643 IN pu4Byte MACReg,
1644 IN pu4Byte MACBackup
1645 )
1646 {
1647 u4Byte i;
1648 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1649 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1650 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1651 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1652 #endif
1653 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1654 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1655 #endif
1656 #endif
1657 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
1658 for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
1659 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);
1660 }
1661 ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
1662 }
1663
1664
1665 VOID
_PHY_PathADDAOn8723B(IN PDM_ODM_T pDM_Odm,IN pu4Byte ADDAReg,IN BOOLEAN isPathAOn,IN BOOLEAN is2T)1666 _PHY_PathADDAOn8723B(
1667 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1668 IN PDM_ODM_T pDM_Odm,
1669 #else
1670 IN PADAPTER pAdapter,
1671 #endif
1672 IN pu4Byte ADDAReg,
1673 IN BOOLEAN isPathAOn,
1674 IN BOOLEAN is2T
1675 )
1676 {
1677 u4Byte pathOn;
1678 u4Byte i;
1679 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1680 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1681 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1682 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1683 #endif
1684 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1685 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1686 #endif
1687 #endif
1688 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
1689
1690 pathOn = isPathAOn ? 0x01c00014 : 0x01c00014;
1691 if(FALSE == is2T){
1692 pathOn = 0x01c00014;
1693 ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x01c00014);
1694 }
1695 else{
1696 ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);
1697 }
1698
1699 for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
1700 ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);
1701 }
1702
1703 }
1704
1705 VOID
_PHY_MACSettingCalibration8723B(IN PDM_ODM_T pDM_Odm,IN pu4Byte MACReg,IN pu4Byte MACBackup)1706 _PHY_MACSettingCalibration8723B(
1707 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1708 IN PDM_ODM_T pDM_Odm,
1709 #else
1710 IN PADAPTER pAdapter,
1711 #endif
1712 IN pu4Byte MACReg,
1713 IN pu4Byte MACBackup
1714 )
1715 {
1716 u4Byte i = 0;
1717 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1718 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1719 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1720 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1721 #endif
1722 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1723 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1724 #endif
1725 #endif
1726 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
1727
1728 ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
1729
1730 for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
1731 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));
1732 }
1733 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5)));
1734
1735 }
1736
1737 VOID
_PHY_PathAStandBy8723B(IN PDM_ODM_T pDM_Odm)1738 _PHY_PathAStandBy8723B(
1739 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1740 IN PDM_ODM_T pDM_Odm
1741 #else
1742 IN PADAPTER pAdapter
1743 #endif
1744 )
1745 {
1746 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1747 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1748 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1749 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1750 #endif
1751 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1752 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1753 #endif
1754 #endif
1755 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n"));
1756
1757 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0);
1758 //Allen
1759 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
1760 //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);
1761 //
1762 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1763 }
1764
1765 VOID
_PHY_PIModeSwitch8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN PIMode)1766 _PHY_PIModeSwitch8723B(
1767 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1768 IN PDM_ODM_T pDM_Odm,
1769 #else
1770 IN PADAPTER pAdapter,
1771 #endif
1772 IN BOOLEAN PIMode
1773 )
1774 {
1775 u4Byte mode;
1776 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1777 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1778 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1779 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1780 #endif
1781 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1782 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1783 #endif
1784 #endif
1785 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
1786
1787 mode = PIMode ? 0x01000100 : 0x01000000;
1788 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
1789 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
1790 }
1791
1792 BOOLEAN
phy_SimularityCompare_8723B(IN PDM_ODM_T pDM_Odm,IN s4Byte result[][8],IN u1Byte c1,IN u1Byte c2)1793 phy_SimularityCompare_8723B(
1794 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1795 IN PDM_ODM_T pDM_Odm,
1796 #else
1797 IN PADAPTER pAdapter,
1798 #endif
1799 IN s4Byte result[][8],
1800 IN u1Byte c1,
1801 IN u1Byte c2
1802 )
1803 {
1804 u4Byte i, j, diff, SimularityBitMap, bound = 0;
1805 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1806 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1807 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1808 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1809 #endif
1810 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1811 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1812 #endif
1813 #endif
1814 u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
1815 BOOLEAN bResult = TRUE;
1816 //#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1817 // BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);
1818 //#else
1819 BOOLEAN is2T = TRUE;
1820 //#endif
1821
1822 s4Byte tmp1 = 0,tmp2 = 0;
1823
1824 if(is2T)
1825 bound = 8;
1826 else
1827 bound = 4;
1828
1829 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2));
1830
1831
1832 SimularityBitMap = 0;
1833
1834 for( i = 0; i < bound; i++ )
1835 {
1836
1837 if((i==1) || (i==3) || (i==5) || (i==7))
1838 {
1839 if((result[c1][i]& 0x00000200) != 0)
1840 tmp1 = result[c1][i] | 0xFFFFFC00;
1841 else
1842 tmp1 = result[c1][i];
1843
1844 if((result[c2][i]& 0x00000200) != 0)
1845 tmp2 = result[c2][i] | 0xFFFFFC00;
1846 else
1847 tmp2 = result[c2][i];
1848 }
1849 else
1850 {
1851 tmp1 = result[c1][i];
1852 tmp2 = result[c2][i];
1853 }
1854
1855 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
1856
1857 if (diff > MAX_TOLERANCE)
1858 {
1859 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i]));
1860
1861 if((i == 2 || i == 6) && !SimularityBitMap)
1862 {
1863 if(result[c1][i]+result[c1][i+1] == 0)
1864 final_candidate[(i/4)] = c2;
1865 else if (result[c2][i]+result[c2][i+1] == 0)
1866 final_candidate[(i/4)] = c1;
1867 else
1868 SimularityBitMap = SimularityBitMap|(1<<i);
1869 }
1870 else
1871 SimularityBitMap = SimularityBitMap|(1<<i);
1872 }
1873 }
1874
1875 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap));
1876
1877 if ( SimularityBitMap == 0)
1878 {
1879 for( i = 0; i < (bound/4); i++ )
1880 {
1881 if(final_candidate[i] != 0xFF)
1882 {
1883 for( j = i*4; j < (i+1)*4-2; j++)
1884 result[3][j] = result[final_candidate[i]][j];
1885 bResult = FALSE;
1886 }
1887 }
1888 return bResult;
1889 }
1890 else
1891 {
1892
1893 if (!(SimularityBitMap & 0x03)) //path A TX OK
1894 {
1895 for(i = 0; i < 2; i++)
1896 result[3][i] = result[c1][i];
1897 }
1898
1899 if (!(SimularityBitMap & 0x0c)) //path A RX OK
1900 {
1901 for(i = 2; i < 4; i++)
1902 result[3][i] = result[c1][i];
1903 }
1904
1905 if (!(SimularityBitMap & 0x30)) //path B TX OK
1906 {
1907 for(i = 4; i < 6; i++)
1908 result[3][i] = result[c1][i];
1909
1910 }
1911
1912 if (!(SimularityBitMap & 0xc0)) //path B RX OK
1913 {
1914 for(i = 6; i < 8; i++)
1915 result[3][i] = result[c1][i];
1916 }
1917 return FALSE;
1918 }
1919 }
1920
1921
1922
1923 VOID
phy_IQCalibrate_8723B(IN PDM_ODM_T pDM_Odm,IN s4Byte result[][8],IN u1Byte t,IN BOOLEAN is2T,IN u1Byte RF_Path)1924 phy_IQCalibrate_8723B(
1925 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1926 IN PDM_ODM_T pDM_Odm,
1927 #else
1928 IN PADAPTER pAdapter,
1929 #endif
1930 IN s4Byte result[][8],
1931 IN u1Byte t,
1932 IN BOOLEAN is2T,
1933 IN u1Byte RF_Path
1934 )
1935 {
1936 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1937 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1938 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1939 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1940 #endif
1941 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1942 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1943 #endif
1944 #endif
1945 u4Byte i;
1946 u1Byte PathAOK, PathBOK;
1947 u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0);
1948 u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0);
1949 u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
1950 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
1951 rRx_Wait_CCA, rTx_CCK_RFON,
1952 rTx_CCK_BBON, rTx_OFDM_RFON,
1953 rTx_OFDM_BBON, rTx_To_Rx,
1954 rTx_To_Tx, rRx_CCK,
1955 rRx_OFDM, rRx_Wait_RIFS,
1956 rRx_TO_Rx, rStandby,
1957 rSleep, rPMPD_ANAEN };
1958 u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1959 REG_TXPAUSE, REG_BCN_CTRL,
1960 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1961
1962 //since 92C & 92D have the different define in IQK_BB_REG
1963 u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1964 rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
1965 rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
1966 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
1967 rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting
1968 };
1969
1970 u4Byte Path_SEL_BB;
1971 // u4Byte Path_SEL_BB, Path_SEL_RF;
1972
1973 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1974 u4Byte retryCount = 2;
1975 #else
1976 #if MP_DRIVER
1977 const u4Byte retryCount = 1;
1978 #else
1979 const u4Byte retryCount = 2;
1980 #endif
1981 #endif
1982
1983 if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 )
1984 {
1985 DBG_871X("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n",__func__);
1986 return;
1987 }
1988
1989 // Note: IQ calibration must be performed after loading
1990 // PHY_REG.txt , and radio_a, radio_b.txt
1991
1992 //u4Byte bbvalue;
1993
1994 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1995 #ifdef MP_TEST
1996 if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
1997 retryCount = 9;
1998 #endif
1999 #endif
2000
2001
2002 if(t==0)
2003 {
2004 // bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
2005 // RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));
2006
2007 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
2008
2009 // Save ADDA parameters, turn Path A ADDA on
2010 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2011 _PHY_SaveADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
2012 _PHY_SaveMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
2013 _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
2014 #else
2015 _PHY_SaveADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
2016 _PHY_SaveMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
2017 _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
2018 #endif
2019 }
2020 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
2021
2022 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2023
2024 _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, TRUE, is2T);
2025 #else
2026 _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, TRUE, is2T);
2027 #endif
2028
2029 //no serial mode
2030 #if 0
2031 if(t==0)
2032 {
2033 pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
2034 }
2035
2036 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
2037 // Switch BB to PI mode to do IQ Calibration.
2038 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2039 _PHY_PIModeSwitch8723B(pAdapter, TRUE);
2040 #else
2041 _PHY_PIModeSwitch8723B(pDM_Odm, TRUE);
2042 #endif
2043 }
2044 #endif
2045
2046 //save RF path for 8723B
2047 // Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);
2048 // Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff);
2049
2050 //MAC settings
2051 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2052 _PHY_MACSettingCalibration8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
2053 #else
2054 _PHY_MACSettingCalibration8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
2055 #endif
2056
2057 //BB setting
2058 //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);
2059 ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf);
2060 ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
2061 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
2062 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
2063
2064
2065 // ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
2066 // ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
2067 // ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
2068 // ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
2069
2070
2071 //for 8723B
2072 #if 0
2073 if(is2T)
2074 {
2075
2076 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
2077 }
2078 #endif
2079
2080
2081 //no APK
2082 #if 0
2083 //Page B init
2084 //AP or IQK
2085 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
2086
2087 if(is2T)
2088 {
2089 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);
2090 }
2091 #endif
2092
2093 //RX IQ calibration setting for 8723B D cut large current issue when leaving IPS
2094
2095 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2096 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
2097 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
2098 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f);
2099 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7);
2100 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1);
2101 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd);
2102 /*
2103 //LOK RF setting
2104 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x2, 0x1);
2105 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x2, 0x1);
2106 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x00032);
2107 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x76, bRFRegOffsetMask, 0x00032);
2108 */
2109
2110
2111 //path A TX IQK
2112 #if 1
2113
2114 for(i = 0 ; i < retryCount ; i++){
2115 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2116 PathAOK = phy_PathA_IQK_8723B(pAdapter, is2T, RF_Path);
2117 #else
2118 PathAOK = phy_PathA_IQK_8723B(pDM_Odm, is2T, RF_Path);
2119 #endif
2120 // if(PathAOK == 0x03){
2121 if(PathAOK == 0x01){
2122 // Path A Tx IQK Success
2123 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2124 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask);
2125
2126 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
2127 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2128 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2129 break;
2130 }
2131 #if 0
2132 else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
2133 {
2134 RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
2135
2136 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2137 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2138 }
2139 #endif
2140 }
2141 #endif
2142
2143 //path A RXIQK
2144 #if 1
2145
2146 for(i = 0 ; i < retryCount ; i++){
2147 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2148 PathAOK = phy_PathA_RxIQK8723B(pAdapter, is2T, RF_Path);
2149 #else
2150 PathAOK = phy_PathA_RxIQK8723B(pDM_Odm, is2T, RF_Path);
2151 #endif
2152 if(PathAOK == 0x03){
2153 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
2154 // result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2155 // result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2156 result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
2157 result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
2158 break;
2159 }
2160 else
2161 {
2162 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
2163 }
2164 }
2165
2166 if(0x00 == PathAOK){
2167 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
2168 }
2169 #endif
2170
2171 //path B IQK
2172 #if 1
2173
2174 if(is2T){
2175
2176 /*
2177 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2178 // _PHY_PathAStandBy8723B(pAdapter);
2179
2180 // Turn Path B ADDA on
2181 _PHY_PathADDAOn8723B(pAdapter, ADDA_REG, FALSE, is2T);
2182 #else
2183 // _PHY_PathAStandBy8723B(pDM_Odm);
2184
2185 // Turn Path B ADDA on
2186 _PHY_PathADDAOn8723B(pDM_Odm, ADDA_REG, FALSE, is2T);
2187 #endif
2188 */
2189
2190 //path B TX IQK
2191 #if 1
2192 for(i = 0 ; i < retryCount ; i++){
2193 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2194 PathBOK = phy_PathB_IQK_8723B(pAdapter);
2195 #else
2196 PathBOK = phy_PathB_IQK_8723B(pDM_Odm);
2197 #endif
2198 // if(PathBOK == 0x03){
2199 if(PathBOK == 0x01){
2200 // Path B Tx IQK Success
2201 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2202 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask);
2203
2204 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n"));
2205 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2206 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2207 break;
2208 }
2209 #if 0
2210 else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
2211 {
2212 RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n"));
2213
2214 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
2215 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
2216 }
2217 #endif
2218 }
2219 #endif
2220
2221 //path B RX IQK
2222 #if 1
2223
2224 for(i = 0 ; i < retryCount ; i++){
2225 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2226 PathBOK = phy_PathB_RxIQK8723B(pAdapter, is2T);
2227 #else
2228 PathBOK = phy_PathB_RxIQK8723B(pDM_Odm, is2T);
2229 #endif
2230 if(PathBOK == 0x03){
2231 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n"));
2232 // result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2233 // result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
2234 result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
2235 result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
2236 break;
2237 }
2238 else
2239 {
2240 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n"));
2241 }
2242 }
2243
2244 #endif
2245
2246 ////////Allen end /////////
2247 if(0x00 == PathBOK){
2248 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
2249 }
2250 }
2251 #endif //pathB IQK
2252
2253 //Back to BB mode, load original value
2254 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
2255 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);
2256
2257 if(t!=0)
2258 {
2259 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
2260 // Switch back BB to SI mode after finish IQ Calibration.
2261 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2262 // _PHY_PIModeSwitch8723B(pAdapter, FALSE);
2263 #else
2264 // _PHY_PIModeSwitch8723B(pDM_Odm, FALSE);
2265 #endif
2266 }
2267 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2268
2269 // Reload ADDA power saving parameters
2270 _PHY_ReloadADDARegisters8723B(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
2271
2272 // Reload MAC parameters
2273 _PHY_ReloadMACRegisters8723B(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
2274
2275 _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
2276 #else
2277 // Reload ADDA power saving parameters
2278 _PHY_ReloadADDARegisters8723B(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
2279
2280 // Reload MAC parameters
2281 _PHY_ReloadMACRegisters8723B(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
2282
2283 _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
2284 #endif
2285
2286
2287 //Reload RF path
2288 // ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB);
2289 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);
2290
2291 //Allen initial gain 0xc50
2292 // Restore RX initial gain
2293 ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50);
2294 ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50);
2295 if(is2T){
2296 ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50);
2297 ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58);
2298 }
2299
2300 //load 0xe30 IQC default value
2301 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2302 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2303
2304 }
2305 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n"));
2306
2307 }
2308
2309
2310 VOID
phy_LCCalibrate_8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN is2T)2311 phy_LCCalibrate_8723B(
2312 IN PDM_ODM_T pDM_Odm,
2313 IN BOOLEAN is2T
2314 )
2315 {
2316 u1Byte tmpReg;
2317 u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
2318 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2319 PADAPTER pAdapter = pDM_Odm->Adapter;
2320 #endif
2321 if( pAdapter->registrypriv.mp_mode == 1 && pAdapter->mppriv.mode == 3 )
2322 {
2323 DBG_871X("%s() :return !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n",__func__);
2324 return;
2325 }
2326
2327 //Check continuous TX and Packet TX
2328 tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);
2329
2330 if((tmpReg&0x70) != 0) //Deal with contisuous TX case
2331 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX
2332 else // Deal with Packet TX case
2333 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues
2334
2335 if((tmpReg&0x70) != 0)
2336 {
2337 //1. Read original RF mode
2338 //Path-A
2339 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2340 RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);
2341
2342 //Path-B
2343 if(is2T)
2344 RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits);
2345 #else
2346 RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits);
2347
2348 //Path-B
2349 if(is2T)
2350 RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits);
2351 #endif
2352
2353 //2. Set RF mode = standby mode
2354 //Path-A
2355 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
2356
2357 //Path-B
2358 if(is2T)
2359 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
2360 }
2361
2362 //3. Read RF reg18
2363 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2364 LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
2365 #else
2366 LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
2367 #endif
2368
2369 //4. Set LC calibration begin bit15
2370 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); // LDO ON
2371 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
2372
2373 ODM_delay_ms(100);
2374
2375 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); // LDO OFF
2376
2377 // Channel 10 LC calibration issue for 8723bs with 26M xtal
2378 if(pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2)
2379 {
2380 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal);
2381 }
2382
2383 //Restore original situation
2384 if((tmpReg&0x70) != 0) //Deal with contisuous TX case
2385 {
2386 //Path-A
2387 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);
2388 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
2389
2390 //Path-B
2391 if(is2T)
2392 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
2393 }
2394 else // Deal with Packet TX case
2395 {
2396 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
2397 }
2398 }
2399
2400 //Analog Pre-distortion calibration
2401 #define APK_BB_REG_NUM 8
2402 #define APK_CURVE_REG_NUM 4
2403 #define PATH_NUM 2
2404
2405 VOID
phy_APCalibrate_8723B(IN PDM_ODM_T pDM_Odm,IN s1Byte delta,IN BOOLEAN is2T)2406 phy_APCalibrate_8723B(
2407 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2408 IN PDM_ODM_T pDM_Odm,
2409 #else
2410 IN PADAPTER pAdapter,
2411 #endif
2412 IN s1Byte delta,
2413 IN BOOLEAN is2T
2414 )
2415 {
2416 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2417 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2418 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2419 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
2420 #endif
2421 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2422 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
2423 #endif
2424 #endif
2425 u4Byte regD[PATH_NUM];
2426 u4Byte tmpReg, index, offset, apkbound;
2427 u1Byte path, i, pathbound = PATH_NUM;
2428 u4Byte BB_backup[APK_BB_REG_NUM];
2429 u4Byte BB_REG[APK_BB_REG_NUM] = {
2430 rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
2431 rFPGA0_RFMOD, rOFDM0_TRMuxPar,
2432 rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
2433 rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
2434 u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
2435 0x00000020, 0x00a05430, 0x02040000,
2436 0x000800e4, 0x00204000 };
2437 u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = {
2438 0x00000020, 0x00a05430, 0x02040000,
2439 0x000800e4, 0x22204000 };
2440
2441 u4Byte AFE_backup[IQK_ADDA_REG_NUM];
2442 u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
2443 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
2444 rRx_Wait_CCA, rTx_CCK_RFON,
2445 rTx_CCK_BBON, rTx_OFDM_RFON,
2446 rTx_OFDM_BBON, rTx_To_Rx,
2447 rTx_To_Tx, rRx_CCK,
2448 rRx_OFDM, rRx_Wait_RIFS,
2449 rRx_TO_Rx, rStandby,
2450 rSleep, rPMPD_ANAEN };
2451
2452 u4Byte MAC_backup[IQK_MAC_REG_NUM];
2453 u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
2454 REG_TXPAUSE, REG_BCN_CTRL,
2455 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
2456
2457 u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
2458 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
2459 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
2460 };
2461
2462 u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
2463 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
2464 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
2465 };
2466
2467 u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
2468 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
2469 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
2470 };
2471
2472 u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
2473 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
2474 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
2475 };
2476
2477 u4Byte AFE_on_off[PATH_NUM] = {
2478 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
2479
2480 u4Byte APK_offset[PATH_NUM] = {
2481 rConfig_AntA, rConfig_AntB};
2482
2483 u4Byte APK_normal_offset[PATH_NUM] = {
2484 rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
2485
2486 u4Byte APK_value[PATH_NUM] = {
2487 0x92fc0000, 0x12fc0000};
2488
2489 u4Byte APK_normal_value[PATH_NUM] = {
2490 0x92680000, 0x12680000};
2491
2492 s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = {
2493 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
2494 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
2495 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
2496 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
2497 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
2498 };
2499
2500 u4Byte APK_normal_setting_value_1[13] = {
2501 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
2502 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
2503 0x12680000, 0x00880000, 0x00880000
2504 };
2505
2506 u4Byte APK_normal_setting_value_2[16] = {
2507 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
2508 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
2509 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
2510 0x00050006
2511 };
2512
2513 u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
2514 // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
2515
2516 s4Byte BB_offset, delta_V, delta_offset;
2517
2518 #if MP_DRIVER == 1
2519 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2520 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2521 #else
2522 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
2523 #endif
2524 pMptCtx->APK_bound[0] = 45;
2525 pMptCtx->APK_bound[1] = 52;
2526
2527 #endif
2528
2529 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
2530 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
2531 if(!is2T)
2532 pathbound = 1;
2533
2534 //2 FOR NORMAL CHIP SETTINGS
2535
2536 // Temporarily do not allow normal driver to do the following settings because these offset
2537 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
2538 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
2539 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
2540 #if MP_DRIVER != 1
2541 return;
2542 #endif
2543 //settings adjust for normal chip
2544 for(index = 0; index < PATH_NUM; index ++)
2545 {
2546 APK_offset[index] = APK_normal_offset[index];
2547 APK_value[index] = APK_normal_value[index];
2548 AFE_on_off[index] = 0x6fdb25a4;
2549 }
2550
2551 for(index = 0; index < APK_BB_REG_NUM; index ++)
2552 {
2553 for(path = 0; path < pathbound; path++)
2554 {
2555 APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
2556 APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
2557 }
2558 BB_AP_MODE[index] = BB_normal_AP_MODE[index];
2559 }
2560
2561 apkbound = 6;
2562
2563 //save BB default value
2564 for(index = 0; index < APK_BB_REG_NUM ; index++)
2565 {
2566 if(index == 0) //skip
2567 continue;
2568 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
2569 }
2570
2571 //save MAC default value
2572 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2573 _PHY_SaveMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);
2574
2575 //save AFE default value
2576 _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2577 #else
2578 _PHY_SaveMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);
2579
2580 //save AFE default value
2581 _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2582 #endif
2583
2584 for(path = 0; path < pathbound; path++)
2585 {
2586
2587
2588 if(path == ODM_RF_PATH_A)
2589 {
2590 //path A APK
2591 //load APK setting
2592 //path-A
2593 offset = rPdp_AntA;
2594 for(index = 0; index < 11; index ++)
2595 {
2596 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
2597 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
2598
2599 offset += 0x04;
2600 }
2601
2602 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
2603
2604 offset = rConfig_AntA;
2605 for(; index < 13; index ++)
2606 {
2607 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
2608 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
2609
2610 offset += 0x04;
2611 }
2612
2613 //page-B1
2614 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
2615
2616 //path A
2617 offset = rPdp_AntA;
2618 for(index = 0; index < 16; index++)
2619 {
2620 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
2621 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
2622
2623 offset += 0x04;
2624 }
2625 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2626 }
2627 else if(path == ODM_RF_PATH_B)
2628 {
2629 //path B APK
2630 //load APK setting
2631 //path-B
2632 offset = rPdp_AntB;
2633 for(index = 0; index < 10; index ++)
2634 {
2635 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
2636 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
2637
2638 offset += 0x04;
2639 }
2640 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
2641 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2642 PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
2643 #else
2644 PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
2645 #endif
2646
2647 offset = rConfig_AntA;
2648 index = 11;
2649 for(; index < 13; index ++) //offset 0xb68, 0xb6c
2650 {
2651 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
2652 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
2653
2654 offset += 0x04;
2655 }
2656
2657 //page-B1
2658 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
2659
2660 //path B
2661 offset = 0xb60;
2662 for(index = 0; index < 16; index++)
2663 {
2664 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
2665 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
2666
2667 offset += 0x04;
2668 }
2669 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);
2670 }
2671
2672 //save RF default value
2673 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2674 regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);
2675 #else
2676 regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord);
2677 #endif
2678
2679 //Path A AFE all on, path B AFE All off or vise versa
2680 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
2681 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
2682 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));
2683
2684 //BB to AP mode
2685 if(path == 0)
2686 {
2687 for(index = 0; index < APK_BB_REG_NUM ; index++)
2688 {
2689
2690 if(index == 0) //skip
2691 continue;
2692 else if (index < 5)
2693 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
2694 else if (BB_REG[index] == 0x870)
2695 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
2696 else
2697 ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);
2698 }
2699
2700 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2701 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2702 }
2703 else //path B
2704 {
2705 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
2706 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
2707
2708 }
2709
2710 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));
2711
2712 //MAC settings
2713 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2714 _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup);
2715 #else
2716 _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup);
2717 #endif
2718
2719 if(path == ODM_RF_PATH_A) //Path B to standby mode
2720 {
2721 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
2722 }
2723 else //Path A to standby mode
2724 {
2725 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
2726 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
2727 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);
2728 }
2729
2730 delta_offset = ((delta+14)/2);
2731 if(delta_offset < 0)
2732 delta_offset = 0;
2733 else if (delta_offset > 12)
2734 delta_offset = 12;
2735
2736 //AP calibration
2737 for(index = 0; index < APK_BB_REG_NUM; index++)
2738 {
2739 if(index != 1) //only DO PA11+PAD01001, AP RF setting
2740 continue;
2741
2742 tmpReg = APK_RF_init_value[path][index];
2743 #if 1
2744 if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)
2745 {
2746 BB_offset = (tmpReg & 0xF0000) >> 16;
2747
2748 if(!(tmpReg & BIT15)) //sign bit 0
2749 {
2750 BB_offset = -BB_offset;
2751 }
2752
2753 delta_V = APK_delta_mapping[index][delta_offset];
2754
2755 BB_offset += delta_V;
2756
2757 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));
2758
2759 if(BB_offset < 0)
2760 {
2761 tmpReg = tmpReg & (~BIT15);
2762 BB_offset = -BB_offset;
2763 }
2764 else
2765 {
2766 tmpReg = tmpReg | BIT15;
2767 }
2768 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
2769 }
2770 #endif
2771
2772 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e);
2773 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2774 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));
2775 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
2776 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));
2777 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg);
2778 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));
2779 #else
2780 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));
2781 ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
2782 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));
2783 ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);
2784 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));
2785 #endif
2786
2787 // PA11+PAD01111, one shot
2788 i = 0;
2789 do
2790 {
2791 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);
2792 {
2793 ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);
2794 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
2795 ODM_delay_ms(3);
2796 ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);
2797 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
2798
2799 ODM_delay_ms(20);
2800 }
2801 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2802
2803 if(path == ODM_RF_PATH_A)
2804 tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);
2805 else
2806 tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);
2807 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));
2808
2809
2810 i++;
2811 }
2812 while(tmpReg > apkbound && i < 4);
2813
2814 APK_result[path][index] = tmpReg;
2815 }
2816 }
2817
2818 //reload MAC default value
2819 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2820 _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);
2821 #else
2822 _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);
2823 #endif
2824
2825 //reload BB default value
2826 for(index = 0; index < APK_BB_REG_NUM ; index++)
2827 {
2828
2829 if(index == 0) //skip
2830 continue;
2831 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
2832 }
2833
2834 //reload AFE default value
2835 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2836 _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2837 #else
2838 _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2839 #endif
2840
2841 //reload RF path default value
2842 for(path = 0; path < pathbound; path++)
2843 {
2844 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]);
2845 if(path == ODM_RF_PATH_B)
2846 {
2847 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
2848 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
2849 }
2850
2851 //note no index == 0
2852 if (APK_result[path][1] > 6)
2853 APK_result[path][1] = 6;
2854 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
2855 }
2856
2857 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
2858
2859
2860 for(path = 0; path < pathbound; path++)
2861 {
2862 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord,
2863 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
2864 if(path == ODM_RF_PATH_A)
2865 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord,
2866 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
2867 else
2868 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord,
2869 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
2870 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2871 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
2872 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
2873 #endif
2874 }
2875
2876 pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;
2877
2878 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));
2879 }
2880
2881
2882
2883 #define DP_BB_REG_NUM 7
2884 #define DP_RF_REG_NUM 1
2885 #define DP_RETRY_LIMIT 10
2886 #define DP_PATH_NUM 2
2887 #define DP_DPK_NUM 3
2888 #define DP_DPK_VALUE_NUM 2
2889
2890
2891
2892 //IQK version:V2.5 20140123
2893 //IQK is controlled by Is2ant, RF path
2894 VOID
PHY_IQCalibrate_8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bReCovery,IN BOOLEAN bRestore,IN BOOLEAN Is2ant,IN u1Byte RF_Path)2895 PHY_IQCalibrate_8723B(
2896 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2897 IN PDM_ODM_T pDM_Odm,
2898 #else
2899 IN PADAPTER pAdapter,
2900 #endif
2901 IN BOOLEAN bReCovery,
2902 IN BOOLEAN bRestore,
2903 IN BOOLEAN Is2ant, //false:1ant, true:2-ant
2904 IN u1Byte RF_Path //0:S1, 1:S0
2905 )
2906 {
2907 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2908 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2909
2910 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2911 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
2912 #else // (DM_ODM_SUPPORT_TYPE == ODM_CE)
2913 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
2914 #endif
2915
2916 #if (MP_DRIVER == 1)
2917 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2918 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
2919 #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
2920 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2921 #endif
2922 #endif//(MP_DRIVER == 1)
2923 #endif
2924
2925 s4Byte result[4][8]; //last is final result
2926 u1Byte i, final_candidate, Indexforchannel;
2927 BOOLEAN bPathAOK, bPathBOK;
2928 s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
2929 BOOLEAN is12simular, is13simular, is23simular;
2930 BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
2931 u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
2932 rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
2933 rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
2934 rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
2935 rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
2936 rOFDM0_RxIQExtAnta};
2937 // u4Byte Path_SEL_BB = 0;
2938 u4Byte GNT_BT_default;
2939 u4Byte StartTime;
2940 s4Byte ProgressingTime;
2941
2942 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) )
2943 if (ODM_CheckPowerStatus(pAdapter) == FALSE)
2944 return;
2945 #else
2946 prtl8192cd_priv priv = pDM_Odm->priv;
2947
2948 #ifdef MP_TEST
2949 if(priv->pshare->rf_ft_var.mp_specific)
2950 {
2951 if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))
2952 return;
2953 }
2954 #endif
2955
2956 if(priv->pshare->IQK_88E_done)
2957 bReCovery= 1;
2958 priv->pshare->IQK_88E_done = 1;
2959
2960 #endif
2961
2962 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2963 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
2964 {
2965 return;
2966 }
2967 #endif
2968
2969 #if MP_DRIVER == 1
2970 bStartContTx = pMptCtx->bStartContTx;
2971 bSingleTone = pMptCtx->bSingleTone;
2972 bCarrierSuppression = pMptCtx->bCarrierSuppression;
2973 #endif
2974
2975 // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
2976 if(bSingleTone || bCarrierSuppression)
2977 return;
2978
2979 #if DISABLE_BB_RF
2980 return;
2981 #endif
2982 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
2983 return;
2984
2985
2986 ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
2987 pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE;
2988 ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
2989
2990 if (bRestore) {
2991 u4Byte offset, data;
2992 u1Byte path, bResult = SUCCESS;
2993 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
2994
2995 //#define PATH_S0 1 // RF_PATH_B
2996 //#define PATH_S1 0 // RF_PATH_A
2997
2998 path = (RF_Path == 0 ? ODM_RF_PATH_A : ODM_RF_PATH_B);
2999
3000 // Restore TX IQK
3001 for (i = 0; i < 3; ++i) {
3002 offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0];
3003 data = pRFCalibrateInfo->TxIQC_8723B[path][i][1];
3004 if ((offset == 0) || (i == 1 && data == 0)) { /* 0xc80, 0xc88 ==> index=1 */
3005 DBG_871X("%s =>path:%s Restore TX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B");
3006 bResult = FAIL;
3007 break;
3008 }
3009 //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data));
3010 ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data);
3011 }
3012
3013 // Restore RX IQK
3014 for (i = 0; i < 2; ++i) {
3015 offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0];
3016 data = pRFCalibrateInfo->RxIQC_8723B[path][i][1];
3017 if ((offset == 0) || (i == 0 && data == 0)) { /* 0xc14, 0xc1c ==> index=0 */
3018 DBG_871X("%s =>path:%s Restore RX IQK result failed\n", __func__, (path == ODM_RF_PATH_A) ? "A" : "B");
3019 bResult = FAIL;
3020 break;
3021 }
3022 //RT_TRACE(_module_mp_, _drv_notice_,("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data));
3023 ODM_SetBBReg(pDM_Odm,offset, bMaskDWord, data);
3024 }
3025
3026 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] ==0) {
3027 DBG_871X("%s => Restore Path-A TxLOK result failed \n",__FUNCTION__);
3028 bResult = FAIL;
3029 } else {
3030 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]);
3031 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]);
3032 }
3033
3034 if (bResult == SUCCESS)
3035 goto out;
3036 }
3037
3038 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))
3039 if(bReCovery)
3040 #else//for ODM_WIN
3041 if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405
3042 #endif
3043 {
3044 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n"));
3045 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3046 _PHY_ReloadADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
3047 #else
3048 _PHY_ReloadADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
3049 #endif
3050 goto out;
3051 }
3052 StartTime = ODM_GetCurrentTime( pDM_Odm);
3053 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
3054
3055 //save default GNT_BT
3056 GNT_BT_default = ODM_GetBBReg(pDM_Odm, 0x764, bMaskDWord);
3057 // Save RF Path
3058 // Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord);
3059 // Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff);
3060
3061 //set GNT_BT=0, pause BT traffic
3062 // ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0);
3063 // ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x1);
3064
3065
3066 for(i = 0; i < 8; i++)
3067 {
3068 result[0][i] = 0;
3069 result[1][i] = 0;
3070 result[2][i] = 0;
3071 result[3][i] = 0;
3072 }
3073 final_candidate = 0xff;
3074 bPathAOK = FALSE;
3075 bPathBOK = FALSE;
3076 is12simular = FALSE;
3077 is23simular = FALSE;
3078 is13simular = FALSE;
3079
3080
3081 for (i=0; i<3; i++)
3082 {
3083 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3084 phy_IQCalibrate_8723B(pAdapter, result, i, Is2ant, RF_Path);
3085 #else
3086 phy_IQCalibrate_8723B(pDM_Odm, result, i, Is2ant, RF_Path);
3087 #endif
3088
3089 if(i == 1)
3090 {
3091 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3092 is12simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 1);
3093 #else
3094 is12simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 1);
3095 #endif
3096 if(is12simular)
3097 {
3098 final_candidate = 0;
3099 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));
3100 break;
3101 }
3102 }
3103
3104 if(i == 2)
3105 {
3106 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3107 is13simular = phy_SimularityCompare_8723B(pAdapter, result, 0, 2);
3108 #else
3109 is13simular = phy_SimularityCompare_8723B(pDM_Odm, result, 0, 2);
3110 #endif
3111 if(is13simular)
3112 {
3113 final_candidate = 0;
3114 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));
3115
3116 break;
3117 }
3118 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3119 is23simular = phy_SimularityCompare_8723B(pAdapter, result, 1, 2);
3120 #else
3121 is23simular = phy_SimularityCompare_8723B(pDM_Odm, result, 1, 2);
3122 #endif
3123 if(is23simular)
3124 {
3125 final_candidate = 1;
3126 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));
3127 }
3128 else
3129 {
3130 for(i = 0; i < 8; i++)
3131 RegTmp += result[3][i];
3132
3133 if(RegTmp != 0)
3134 final_candidate = 3;
3135 else
3136 final_candidate = 0xFF;
3137 }
3138 }
3139 }
3140 // RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));
3141
3142 for (i=0; i<4; i++)
3143 {
3144 RegE94 = result[i][0];
3145 RegE9C = result[i][1];
3146 RegEA4 = result[i][2];
3147 RegEAC = result[i][3];
3148 RegEB4 = result[i][4];
3149 RegEBC = result[i][5];
3150 RegEC4 = result[i][6];
3151 RegECC = result[i][7];
3152 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
3153 }
3154
3155 if(final_candidate != 0xff)
3156 {
3157 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
3158 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
3159 RegEA4 = result[final_candidate][2];
3160 RegEAC = result[final_candidate][3];
3161 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
3162 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
3163 RegEC4 = result[final_candidate][6];
3164 RegECC = result[final_candidate][7];
3165 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate));
3166 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
3167 bPathAOK = bPathBOK = TRUE;
3168 }
3169 else
3170 {
3171 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n"));
3172
3173 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value
3174 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value
3175 }
3176
3177 #if MP_DRIVER == 1
3178 if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE))
3179 #endif
3180 {
3181 if (RegE94 != 0)
3182 {
3183 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3184 _PHY_PathAFillIQKMatrix8723B(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
3185 #else
3186 _PHY_PathAFillIQKMatrix8723B(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));
3187 #endif
3188 }
3189 }
3190
3191 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3192 #if MP_DRIVER == 1
3193 if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || (pDM_Odm->mp_mode == FALSE))
3194 #endif
3195 {
3196 if (RegEB4 != 0)
3197 {
3198 _PHY_PathBFillIQKMatrix8723B(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
3199 }
3200 }
3201 #endif
3202
3203 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3204 Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
3205 #else
3206 Indexforchannel = 0;
3207 #endif
3208
3209 //To Fix BSOD when final_candidate is 0xff
3210 //by sherry 20120321
3211 if(final_candidate < 4)
3212 {
3213 for(i = 0; i < IQK_Matrix_REG_NUM; i++)
3214 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
3215 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;
3216 }
3217 //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
3218 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
3219 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3220
3221 _PHY_SaveADDARegisters8723B(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
3222 #else
3223 _PHY_SaveADDARegisters8723B(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);
3224 #endif
3225
3226 //restore GNT_BT
3227 ODM_SetBBReg(pDM_Odm, 0x764, bMaskDWord, GNT_BT_default);
3228 // Restore RF Path
3229 // ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB);
3230 // ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF);
3231
3232 //Resotr RX mode table parameter
3233 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1 );
3234 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000 );
3235 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f );
3236 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177 );
3237 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x20, 0x1 );
3238 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd );
3239
3240 //set GNT_BT= HW control
3241 // ODM_SetBBReg(pDM_Odm, 0x764, BIT12, 0x0);
3242 // ODM_SetBBReg(pDM_Odm, 0x764, BIT11, 0x0);
3243
3244 if (Is2ant) {
3245 if (RF_Path == 0x0) //S1
3246 ODM_SetIQCbyRFpath(pDM_Odm, 0);
3247 else //S0
3248 ODM_SetIQCbyRFpath(pDM_Odm, 1);
3249 }
3250
3251 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
3252 ProgressingTime = ODM_GetProgressingTime(pDM_Odm, StartTime);
3253 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime));
3254
3255 out:
3256 ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
3257 pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;
3258 ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
3259 }
3260
3261
3262 VOID
PHY_LCCalibrate_8723B(PVOID pDM_VOID)3263 PHY_LCCalibrate_8723B(
3264 PVOID pDM_VOID
3265 )
3266 {
3267 BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
3268 u4Byte timeout = 2000, timecount = 0;
3269 u4Byte StartTime;
3270 s4Byte ProgressingTime;
3271 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
3272 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3273 PADAPTER pAdapter = pDM_Odm->Adapter;
3274
3275 #if (MP_DRIVER == 1)
3276 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3277 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
3278 #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
3279 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
3280 #endif
3281 #endif//(MP_DRIVER == 1)
3282 #endif
3283
3284
3285
3286
3287 #if MP_DRIVER == 1
3288 bStartContTx = pMptCtx->bStartContTx;
3289 bSingleTone = pMptCtx->bSingleTone;
3290 bCarrierSuppression = pMptCtx->bCarrierSuppression;
3291 #endif
3292
3293
3294 #if DISABLE_BB_RF
3295 return;
3296 #endif
3297
3298 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3299 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
3300 {
3301 return;
3302 }
3303 #endif
3304 // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
3305 if(bSingleTone || bCarrierSuppression)
3306 return;
3307
3308 StartTime = ODM_GetCurrentTime( pDM_Odm);
3309 while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)
3310 {
3311 ODM_delay_ms(50);
3312 timecount += 50;
3313 }
3314
3315 pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;
3316
3317
3318 phy_LCCalibrate_8723B(pDM_Odm, FALSE);
3319
3320
3321 pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;
3322
3323 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));
3324 ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);
3325 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime));
3326 }
3327
3328 VOID
PHY_APCalibrate_8723B(IN PDM_ODM_T pDM_Odm,IN s1Byte delta)3329 PHY_APCalibrate_8723B(
3330 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3331 IN PDM_ODM_T pDM_Odm,
3332 #else
3333 IN PADAPTER pAdapter,
3334 #endif
3335 IN s1Byte delta
3336 )
3337 {
3338 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3339 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3340 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3341 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3342 #endif
3343 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3344 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3345 #endif
3346 #endif
3347 #if DISABLE_BB_RF
3348 return;
3349 #endif
3350
3351 return;
3352 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3353 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
3354 {
3355 return;
3356 }
3357 #endif
3358
3359 #if FOR_BRAZIL_PRETEST != 1
3360 if(pDM_Odm->RFCalibrateInfo.bAPKdone)
3361 #endif
3362 return;
3363
3364 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3365 if(IS_2T2R( pHalData->VersionID)){
3366 phy_APCalibrate_8723B(pAdapter, delta, TRUE);
3367 }
3368 else
3369 #endif
3370 {
3371 // For 88C 1T1R
3372 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3373 phy_APCalibrate_8723B(pAdapter, delta, FALSE);
3374 #else
3375 phy_APCalibrate_8723B(pDM_Odm, delta, FALSE);
3376 #endif
3377 }
3378 }
phy_SetRFPathSwitch_8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bMain,IN BOOLEAN is2T)3379 VOID phy_SetRFPathSwitch_8723B(
3380 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3381 IN PDM_ODM_T pDM_Odm,
3382 #else
3383 IN PADAPTER pAdapter,
3384 #endif
3385 IN BOOLEAN bMain,
3386 IN BOOLEAN is2T
3387 )
3388 {
3389 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3390 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3391 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3392 #endif
3393 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3394 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3395 #endif
3396
3397 if(bMain) // Left antenna
3398 {
3399 ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1);
3400 }
3401 else
3402 {
3403 ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2);
3404 }
3405 }
PHY_SetRFPathSwitch_8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bMain)3406 VOID PHY_SetRFPathSwitch_8723B(
3407 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3408 IN PDM_ODM_T pDM_Odm,
3409 #else
3410 IN PADAPTER pAdapter,
3411 #endif
3412 IN BOOLEAN bMain
3413 )
3414 {
3415
3416 #if DISABLE_BB_RF
3417 return;
3418 #endif
3419
3420 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3421 phy_SetRFPathSwitch_8723B(pAdapter, bMain, TRUE);
3422 #endif
3423
3424 }
3425
3426 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3427 //digital predistortion
3428 VOID
phy_DigitalPredistortion8723B(IN PADAPTER pAdapter,IN BOOLEAN is2T)3429 phy_DigitalPredistortion8723B(
3430 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3431 IN PADAPTER pAdapter,
3432 #else
3433 IN PDM_ODM_T pDM_Odm,
3434 #endif
3435 IN BOOLEAN is2T
3436 )
3437 {
3438 #if (RT_PLATFORM == PLATFORM_WINDOWS)
3439 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3440 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3441 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3442 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3443 #endif
3444 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3445 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3446 #endif
3447 #endif
3448
3449 u4Byte tmpReg, tmpReg2, index, i;
3450 u1Byte path, pathbound = PATH_NUM;
3451 u4Byte AFE_backup[IQK_ADDA_REG_NUM];
3452 u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
3453 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
3454 rRx_Wait_CCA, rTx_CCK_RFON,
3455 rTx_CCK_BBON, rTx_OFDM_RFON,
3456 rTx_OFDM_BBON, rTx_To_Rx,
3457 rTx_To_Tx, rRx_CCK,
3458 rRx_OFDM, rRx_Wait_RIFS,
3459 rRx_TO_Rx, rStandby,
3460 rSleep, rPMPD_ANAEN };
3461
3462 u4Byte BB_backup[DP_BB_REG_NUM];
3463 u4Byte BB_REG[DP_BB_REG_NUM] = {
3464 rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
3465 rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
3466 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
3467 rFPGA0_XB_RFInterfaceOE};
3468 u4Byte BB_settings[DP_BB_REG_NUM] = {
3469 0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
3470 0x0, 0x0, 0x0};
3471
3472 u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
3473 u4Byte RF_REG[DP_RF_REG_NUM] = {
3474 RF_TXBIAS_A};
3475
3476 u4Byte MAC_backup[IQK_MAC_REG_NUM];
3477 u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
3478 REG_TXPAUSE, REG_BCN_CTRL,
3479 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
3480
3481 u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
3482 {0x1e1e1e1e, 0x03901e1e},
3483 {0x18181818, 0x03901818},
3484 {0x0e0e0e0e, 0x03900e0e}
3485 };
3486
3487 u4Byte AFE_on_off[PATH_NUM] = {
3488 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
3489
3490 u1Byte RetryCount = 0;
3491
3492
3493 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8723B()\n"));
3494
3495 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8723B for %s\n", (is2T ? "2T2R" : "1T1R")));
3496
3497 //save BB default value
3498 for(index=0; index<DP_BB_REG_NUM; index++)
3499 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
3500
3501 //save MAC default value
3502 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3503 _PHY_SaveMACRegisters8723B(pAdapter, BB_REG, MAC_backup);
3504 #else
3505 _PHY_SaveMACRegisters8723B(pDM_Odm, BB_REG, MAC_backup);
3506 #endif
3507
3508 //save RF default value
3509 for(path=0; path<DP_PATH_NUM; path++)
3510 {
3511 for(index=0; index<DP_RF_REG_NUM; index++)
3512 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3513 RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
3514 #else
3515 RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
3516 #endif
3517 }
3518
3519 //save AFE default value
3520 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3521 _PHY_SaveADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
3522 #else
3523 _PHY_SaveADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
3524 #endif
3525
3526 //Path A/B AFE all on
3527 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
3528 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);
3529
3530 //BB register setting
3531 for(index = 0; index < DP_BB_REG_NUM; index++)
3532 {
3533 if(index < 4)
3534 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);
3535 else if (index == 4)
3536 ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
3537 else
3538 ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);
3539 }
3540
3541 //MAC register setting
3542 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3543 _PHY_MACSettingCalibration8723B(pAdapter, MAC_REG, MAC_backup);
3544 #else
3545 _PHY_MACSettingCalibration8723B(pDM_Odm, MAC_REG, MAC_backup);
3546 #endif
3547
3548 //PAGE-E IQC setting
3549 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
3550 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
3551 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
3552 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
3553
3554 //path_A DPK
3555 //Path B to standby mode
3556 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
3557
3558 // PA gain = 11 & PAD1 => tx_agc 1f ~11
3559 // PA gain = 11 & PAD2 => tx_agc 10~0e
3560 // PA gain = 01 => tx_agc 0b~0d
3561 // PA gain = 00 => tx_agc 0a~00
3562 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
3563 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
3564 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3565
3566 //do inner loopback DPK 3 times
3567 for(i = 0; i < 3; i++)
3568 {
3569 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
3570 for(index = 0; index < 3; index++)
3571 ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);
3572 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);
3573 for(index = 0; index < 4; index++)
3574 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);
3575
3576 // PAGE_B for Path-A inner loopback DPK setting
3577 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);
3578 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
3579 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
3580 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
3581
3582 //----send one shot signal----//
3583 // Path A
3584 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);
3585 ODM_delay_ms(1);
3586 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);
3587 ODM_delay_ms(50);
3588 }
3589
3590 //PA gain = 11 => tx_agc = 1a
3591 for(index = 0; index < 3; index++)
3592 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);
3593 ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);
3594 for(index = 0; index < 4; index++)
3595 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);
3596
3597 //====================================
3598 // PAGE_B for Path-A DPK setting
3599 //====================================
3600 // open inner loopback @ b00[19]:10 od 0xb00 0x01097018
3601 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);
3602 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
3603 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
3604 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
3605
3606 //rf_lpbk_setup
3607 //1.rf 00:5205a, rf 0d:0e52c
3608 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);
3609 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);
3610 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );
3611
3612 //----send one shot signal----//
3613 // Path A
3614 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
3615 ODM_delay_ms(1);
3616 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
3617 ODM_delay_ms(50);
3618
3619 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)
3620 {
3621 //----read back measurement results----//
3622 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);
3623 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);
3624 ODM_delay_ms(10);
3625 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);
3626 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);
3627 ODM_delay_ms(10);
3628
3629 tmpReg = (tmpReg & bMaskHWord) >> 16;
3630 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
3631 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )
3632 {
3633 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
3634
3635 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);
3636 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3637 ODM_delay_ms(1);
3638 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
3639 ODM_delay_ms(1);
3640 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
3641 ODM_delay_ms(50);
3642 RetryCount++;
3643 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));
3644 }
3645 else
3646 {
3647 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
3648 pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;
3649 break;
3650 }
3651 }
3652 RetryCount = 0;
3653
3654 //DPP path A
3655 if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)
3656 {
3657 // DP settings
3658 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);
3659 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);
3660 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
3661 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
3662 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
3663
3664 for(i=rPdp_AntA; i<=0xb3c; i+=4)
3665 {
3666 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
3667 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
3668 }
3669
3670 //pwsf
3671 ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);
3672 ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);
3673 ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);
3674
3675 for(i=0xb4c; i<=0xb5c; i+=4)
3676 {
3677 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
3678 }
3679
3680 //TX_AGC boundary
3681 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
3682 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3683 }
3684 else
3685 {
3686 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);
3687 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);
3688 }
3689
3690 //DPK path B
3691 if(is2T)
3692 {
3693 //Path A to standby mode
3694 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
3695
3696 // LUTs => tx_agc
3697 // PA gain = 11 & PAD1, => tx_agc 1f ~11
3698 // PA gain = 11 & PAD2, => tx_agc 10 ~0e
3699 // PA gain = 01 => tx_agc 0b ~0d
3700 // PA gain = 00 => tx_agc 0a ~00
3701 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
3702 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
3703 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3704
3705 //do inner loopback DPK 3 times
3706 for(i = 0; i < 3; i++)
3707 {
3708 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
3709 for(index = 0; index < 4; index++)
3710 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);
3711 for(index = 0; index < 2; index++)
3712 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);
3713 for(index = 0; index < 2; index++)
3714 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);
3715
3716 // PAGE_B for Path-A inner loopback DPK setting
3717 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);
3718 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
3719 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
3720 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
3721
3722 //----send one shot signal----//
3723 // Path B
3724 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);
3725 ODM_delay_ms(1);
3726 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);
3727 ODM_delay_ms(50);
3728 }
3729
3730 // PA gain = 11 => tx_agc = 1a
3731 for(index = 0; index < 4; index++)
3732 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);
3733 for(index = 0; index < 2; index++)
3734 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);
3735 for(index = 0; index < 2; index++)
3736 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);
3737
3738 // PAGE_B for Path-B DPK setting
3739 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
3740 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
3741 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
3742 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
3743
3744 // RF lpbk switches on
3745 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);
3746 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);
3747
3748 //Path-B RF lpbk
3749 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);
3750 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);
3751 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a);
3752
3753 //----send one shot signal----//
3754 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
3755 ODM_delay_ms(1);
3756 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
3757 ODM_delay_ms(50);
3758
3759 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)
3760 {
3761 //----read back measurement results----//
3762 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);
3763 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);
3764 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);
3765 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);
3766
3767 tmpReg = (tmpReg & bMaskHWord) >> 16;
3768 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
3769
3770 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)
3771 {
3772 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
3773
3774 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);
3775 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3776 ODM_delay_ms(1);
3777 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
3778 ODM_delay_ms(1);
3779 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
3780 ODM_delay_ms(50);
3781 RetryCount++;
3782 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));
3783 }
3784 else
3785 {
3786 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
3787 pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;
3788 break;
3789 }
3790 }
3791
3792 //DPP path B
3793 if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)
3794 {
3795 // DP setting
3796 // LUT by SRAM
3797 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);
3798 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);
3799 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
3800 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
3801
3802 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
3803 for(i=0xb60; i<=0xb9c; i+=4)
3804 {
3805 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
3806 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
3807 }
3808
3809 // PWSF
3810 ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);
3811 ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);
3812 ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);
3813
3814 for(i=0xbac; i<=0xbbc; i+=4)
3815 {
3816 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
3817 }
3818
3819 // tx_agc boundary
3820 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
3821 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3822
3823 }
3824 else
3825 {
3826 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);
3827 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);
3828 }
3829 }
3830
3831 //reload BB default value
3832 for(index=0; index<DP_BB_REG_NUM; index++)
3833 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
3834
3835 //reload RF default value
3836 for(path = 0; path<DP_PATH_NUM; path++)
3837 {
3838 for( i = 0 ; i < DP_RF_REG_NUM ; i++){
3839 ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);
3840 }
3841 }
3842 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode
3843 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off
3844
3845 //reload AFE default value
3846 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3847 _PHY_ReloadADDARegisters8723B(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
3848
3849 //reload MAC default value
3850 _PHY_ReloadMACRegisters8723B(pAdapter, MAC_REG, MAC_backup);
3851 #else
3852 _PHY_ReloadADDARegisters8723B(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
3853
3854 //reload MAC default value
3855 _PHY_ReloadMACRegisters8723B(pDM_Odm, MAC_REG, MAC_backup);
3856 #endif
3857
3858 pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;
3859 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8723B()\n"));
3860 #endif
3861 }
3862
3863 VOID
PHY_DigitalPredistortion_8723B(IN PADAPTER pAdapter)3864 PHY_DigitalPredistortion_8723B(
3865 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3866 IN PADAPTER pAdapter
3867 #else
3868 IN PDM_ODM_T pDM_Odm
3869 #endif
3870 )
3871 {
3872 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3873 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3874 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3875 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3876 #endif
3877 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3878 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3879 #endif
3880 #endif
3881 #if DISABLE_BB_RF
3882 return;
3883 #endif
3884
3885 return;
3886
3887 if(pDM_Odm->RFCalibrateInfo.bDPdone)
3888 return;
3889 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3890
3891 if(IS_2T2R( pHalData->VersionID)){
3892 phy_DigitalPredistortion8723B(pAdapter, TRUE);
3893 }
3894 else
3895 #endif
3896 {
3897 // For 88C 1T1R
3898 phy_DigitalPredistortion8723B(pAdapter, FALSE);
3899 }
3900 }
3901
3902
3903
3904 //return value TRUE => Main; FALSE => Aux
3905
phy_QueryRFPathSwitch_8723B(IN PDM_ODM_T pDM_Odm,IN BOOLEAN is2T)3906 BOOLEAN phy_QueryRFPathSwitch_8723B(
3907 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3908 IN PDM_ODM_T pDM_Odm,
3909 #else
3910 IN PADAPTER pAdapter,
3911 #endif
3912 IN BOOLEAN is2T
3913 )
3914 {
3915 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3916 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3917 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3918 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3919 #endif
3920 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3921 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3922 #endif
3923 #endif
3924
3925
3926 if(ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01)
3927 return TRUE;
3928 else
3929 return FALSE;
3930
3931 }
3932
3933
3934
3935 //return value TRUE => Main; FALSE => Aux
PHY_QueryRFPathSwitch_8723B(IN PDM_ODM_T pDM_Odm)3936 BOOLEAN PHY_QueryRFPathSwitch_8723B(
3937 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3938 IN PDM_ODM_T pDM_Odm
3939 #else
3940 IN PADAPTER pAdapter
3941 #endif
3942 )
3943 {
3944 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3945
3946 #if DISABLE_BB_RF
3947 return TRUE;
3948 #endif
3949
3950 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3951 return phy_QueryRFPathSwitch_8723B(pAdapter, FALSE);
3952 #else
3953 return phy_QueryRFPathSwitch_8723B(pDM_Odm, FALSE);
3954 #endif
3955
3956 }
3957 #endif
3958