1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 #include "mp_precomp.h"
22 #include "../phydm_precomp.h"
23
24
25
26 /*---------------------------Define Local Constant---------------------------*/
27 // 2010/04/25 MH Define the max tx power tracking tx agc power.
28 #define ODM_TXPWRTRACK_MAX_IDX_88E 6
29
30 /*---------------------------Define Local Constant---------------------------*/
31
32
33 //3============================================================
34 //3 Tx Power Tracking
35 //3============================================================
36
37
setIqkMatrix_8188E(PDM_ODM_T pDM_Odm,u1Byte OFDM_index,u1Byte RFPath,s4Byte IqkResult_X,s4Byte IqkResult_Y)38 void setIqkMatrix_8188E(
39 PDM_ODM_T pDM_Odm,
40 u1Byte OFDM_index,
41 u1Byte RFPath,
42 s4Byte IqkResult_X,
43 s4Byte IqkResult_Y
44 )
45 {
46 s4Byte ele_A=0, ele_D, ele_C=0, value32;
47
48 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
49
50 //new element A = element D x X
51 if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
52 {
53 if ((IqkResult_X & 0x00000200) != 0) //consider minus
54 IqkResult_X = IqkResult_X | 0xFFFFFC00;
55 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
56
57 //new element C = element D x Y
58 if ((IqkResult_Y & 0x00000200) != 0)
59 IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
60 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
61
62 //if (RFPath == ODM_RF_PATH_A)
63 switch (RFPath)
64 {
65 case ODM_RF_PATH_A:
66 //wirte new elements A, C, D to regC80 and regC94, element B is always 0
67 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
68 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
69
70 value32 = (ele_C&0x000003C0)>>6;
71 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
72
73 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
74 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
75 break;
76 case ODM_RF_PATH_B:
77 //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
78 value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
79 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
80
81 value32 = (ele_C&0x000003C0)>>6;
82 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
83
84 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
85 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
86
87 break;
88 default:
89 break;
90 }
91 }
92 else
93 {
94 switch (RFPath)
95 {
96 case ODM_RF_PATH_A:
97 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
98 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
99 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);
100 break;
101
102 case ODM_RF_PATH_B:
103 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
104 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
105 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);
106 break;
107
108 default:
109 break;
110 }
111 }
112
113 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
114 (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));
115 }
116
DoIQK_8188E(PVOID pDM_VOID,u1Byte DeltaThermalIndex,u1Byte ThermalValue,u1Byte Threshold)117 void DoIQK_8188E(
118 PVOID pDM_VOID,
119 u1Byte DeltaThermalIndex,
120 u1Byte ThermalValue,
121 u1Byte Threshold
122 )
123 {
124 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
125 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
126 PADAPTER Adapter = pDM_Odm->Adapter;
127 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
128 #endif
129
130 ODM_ResetIQKResult(pDM_Odm);
131
132 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
133 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
134 #if USE_WORKITEM
135 PlatformAcquireMutex(&pHalData->mxChnlBwControl);
136 #else
137 PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
138 #endif
139 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
140 PlatformAcquireMutex(&pHalData->mxChnlBwControl);
141 #endif
142 #endif
143
144
145 pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;
146 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
147 PHY_IQCalibrate_8188E(pDM_Odm, FALSE);
148 #else
149 PHY_IQCalibrate_8188E(Adapter, FALSE);
150 #endif
151
152 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
153 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
154 #if USE_WORKITEM
155 PlatformReleaseMutex(&pHalData->mxChnlBwControl);
156 #else
157 PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
158 #endif
159 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
160 PlatformReleaseMutex(&pHalData->mxChnlBwControl);
161 #endif
162 #endif
163 }
164
165 /*-----------------------------------------------------------------------------
166 * Function: odm_TxPwrTrackSetPwr88E()
167 *
168 * Overview: 88E change all channel tx power accordign to flag.
169 * OFDM & CCK are all different.
170 *
171 * Input: NONE
172 *
173 * Output: NONE
174 *
175 * Return: NONE
176 *
177 * Revised History:
178 * When Who Remark
179 * 04/23/2012 MHC Create Version 0.
180 *
181 *---------------------------------------------------------------------------*/
182 VOID
ODM_TxPwrTrackSetPwr88E(IN PVOID pDM_VOID,PWRTRACK_METHOD Method,u1Byte RFPath,u1Byte ChannelMappedIndex)183 ODM_TxPwrTrackSetPwr88E(
184 IN PVOID pDM_VOID,
185 PWRTRACK_METHOD Method,
186 u1Byte RFPath,
187 u1Byte ChannelMappedIndex
188 )
189 {
190 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
191 PADAPTER Adapter = pDM_Odm->Adapter;
192 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
193 u1Byte PwrTrackingLimit_OFDM = 30; //+0dB
194 u1Byte PwrTrackingLimit_CCK= 28; //-2dB
195 u1Byte TxRate = 0xFF;
196 u1Byte Final_OFDM_Swing_Index = 0;
197 u1Byte Final_CCK_Swing_Index = 0;
198 u1Byte i = 0;
199 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
200 if (pDM_Odm->mp_mode == TRUE)
201 {
202 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))
203 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
204 PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
205 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
206 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
207 #endif
208 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
209 #endif
210 }
211 else
212 {
213 u2Byte rate = *(pDM_Odm->pForcedDataRate);
214
215 if(!rate) //auto rate
216 {
217 if(pDM_Odm->TxRate != 0xFF)
218 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
219 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
220 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
221 TxRate = HwRateToMRate(pDM_Odm->TxRate);
222 #endif
223 }
224 else //force rate
225 {
226 TxRate = (u1Byte)rate;
227 }
228 }
229
230 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n"));
231
232 if(TxRate != 0xFF)
233 {
234 //2 CCK
235 if((TxRate >= MGN_1M)&&(TxRate <= MGN_11M))
236 PwrTrackingLimit_CCK = 28; //-2dB
237 //2 OFDM
238 else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M))
239 PwrTrackingLimit_OFDM= 36; //+3dB
240 else if(TxRate == MGN_54M)
241 PwrTrackingLimit_OFDM= 34; //+2dB
242
243 //2 HT
244 else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK
245 PwrTrackingLimit_OFDM= 38; //+4dB
246 else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM
247 PwrTrackingLimit_OFDM= 36; //+3dB
248 else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM
249 PwrTrackingLimit_OFDM= 34; //+2dB
250
251 else
252 PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; /*Default OFDM index = 30*/
253 }
254 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM));
255
256 if (Method == TXAGC)
257 {
258 u4Byte pwr = 0, TxAGC = 0;
259 PADAPTER Adapter = pDM_Odm->Adapter;
260
261 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; /*Remnant index equal to aboslute compensate value.*/
262
263 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel)));
264
265 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))
266
267 if (pDM_Odm->mp_mode == TRUE)
268 {
269 pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);
270 pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A];
271 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr);
272 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
273 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskH3Bytes, TxAGC);
274 //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC));
275
276 pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);
277 pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[RF_PATH_A]);
278 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
279 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
280 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
281 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
282 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
283 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
284 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
285 //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC));
286 }
287 else
288 {
289 //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel);
290 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;
291 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;
292
293 if (RFPath == ODM_RF_PATH_A)
294 {
295 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );
296 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
297 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
298 }
299 }
300
301
302 #endif
303 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
304 //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
305 //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
306 #endif
307
308 }
309 else if (Method == BBSWING)
310 {
311 Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
312 Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
313
314 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
315 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
316 else if (Final_OFDM_Swing_Index <= 0)
317 Final_OFDM_Swing_Index = 0;
318
319 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
320 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
321 else if (pRFCalibrateInfo->BbSwingIdxCck <= 0)
322 Final_CCK_Swing_Index = 0;
323
324 // Adjust BB swing by OFDM IQ matrix
325 if (RFPath == ODM_RF_PATH_A)
326 {
327 setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A,
328 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
329 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
330 // Adjust BB swing by CCK filter coefficient
331 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){
332 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]);
333 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]);
334 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]);
335 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]);
336 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]);
337 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]);
338 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]);
339 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]);
340 }
341 else
342 {
343 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]);
344 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]);
345 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]);
346 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]);
347 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]);
348 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]);
349 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]);
350 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]);
351 }
352 }
353 }
354 else if (Method == MIX_MODE)
355 {
356 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pRFCalibrateInfo->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
357 pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath));
358
359 Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
360 Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
361
362 if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit
363 {
364 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
365
366 setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A,
367 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
368 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
369
370 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;
371
372 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
373 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
374
375 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]));
376 }
377 else if (Final_OFDM_Swing_Index <= 0)
378 {
379 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index;
380
381 setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A,
382 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
383 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
384
385 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE;
386
387 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
388 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
389
390 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]));
391 }
392 else
393 {
394 setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A,
395 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
396 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
397
398 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index));
399
400 if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) /*If TxAGC has changed, reset TxAGC again*/
401 {
402 pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0;
403
404 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM);
405 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7);
406
407 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE;
408
409 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE\n"));
410 }
411 }
412
413 if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK)
414 {
415 pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
416
417 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx));
418
419 // Adjust BB swing by CCK filter coefficient
420
421 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
422 {
423 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]);
424 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]);
425 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]);
426 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]);
427 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]);
428 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]);
429 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]);
430 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]);
431 }
432 else
433 {
434 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]);
435 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]);
436 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]);
437 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]);
438 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]);
439 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]);
440 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]);
441 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]);
442 }
443
444 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;
445
446 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK);
447
448 }
449 else if(Final_CCK_Swing_Index <= 0) // Lowest CCK Index = 0
450 {
451 pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
452
453 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d\n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx));
454
455 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
456 {
457 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]);
458 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]);
459 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]);
460 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]);
461 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]);
462 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]);
463 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]);
464 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]);
465 }
466 else
467 {
468 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]);
469 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]);
470 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]);
471 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]);
472 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]);
473 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]);
474 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]);
475 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]);
476 }
477
478 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE;
479
480 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK);
481
482 }
483 else
484 {
485 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index));
486
487 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
488 {
489 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]);
490 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]);
491 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]);
492 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]);
493 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]);
494 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]);
495 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]);
496 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]);
497 }
498 else
499 {
500 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]);
501 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]);
502 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]);
503 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]);
504 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]);
505 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]);
506 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]);
507 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]);
508 }
509
510 if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK) /*If TxAGC has changed, reset TxAGC again*/
511 {
512 pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;
513 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK);
514 pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = FALSE;
515
516 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE\n"));
517 }
518 }
519 }
520 else
521 {
522 return;
523 }
524 } // odm_TxPwrTrackSetPwr88E
525
526 VOID
GetDeltaSwingTable_8188E(IN PVOID pDM_VOID,OUT pu1Byte * TemperatureUP_A,OUT pu1Byte * TemperatureDOWN_A,OUT pu1Byte * TemperatureUP_B,OUT pu1Byte * TemperatureDOWN_B)527 GetDeltaSwingTable_8188E(
528 IN PVOID pDM_VOID,
529 OUT pu1Byte *TemperatureUP_A,
530 OUT pu1Byte *TemperatureDOWN_A,
531 OUT pu1Byte *TemperatureUP_B,
532 OUT pu1Byte *TemperatureDOWN_B
533 )
534 {
535 *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
536 *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
537 *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
538 *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
539 }
540
ConfigureTxpowerTrack_8188E(PTXPWRTRACK_CFG pConfig)541 void ConfigureTxpowerTrack_8188E(
542 PTXPWRTRACK_CFG pConfig
543 )
544 {
545 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
546 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
547 pConfig->Threshold_IQK = IQK_THRESHOLD;
548 pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E;
549 pConfig->RfPathCount = MAX_PATH_NUM_8188E;
550 pConfig->ThermalRegAddr = RF_T_METER_88E;
551
552 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E;
553 pConfig->DoIQK = DoIQK_8188E;
554 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E;
555 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E;
556 }
557
558 //1 7. IQK
559 #define MAX_TOLERANCE 5
560 #define IQK_DELAY_TIME 1 //ms
561
562 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_IQK_8188E(IN PDM_ODM_T pDM_Odm,IN BOOLEAN configPathB)563 phy_PathA_IQK_8188E(
564 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
565 IN PDM_ODM_T pDM_Odm,
566 #else
567 IN PADAPTER pAdapter,
568 #endif
569 IN BOOLEAN configPathB
570 )
571 {
572 u4Byte regEAC, regE94, regE9C, regEA4;
573 u1Byte result = 0x00;
574 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
575 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
576 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
577 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
578 #endif
579 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
580 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
581 #endif
582 #endif
583 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
584
585 //1 Tx IQK
586 //path-A IQK setting
587 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));
588 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
589 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
590 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
591 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
592
593 //LO calibration setting
594 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
595 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
596
597 //One shot, path A LOK & IQK
598 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
599 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
600 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
601
602 // delay x ms
603 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
604 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
605 ODM_delay_ms(IQK_DELAY_TIME_88E);
606
607 // Check failed
608 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
609 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
610 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
611 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
612 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
613 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
614 regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
615 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
616
617 if(!(regEAC & BIT28) &&
618 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
619 (((regE9C & 0x03FF0000)>>16) != 0x42) )
620 result |= 0x01;
621 else //if Tx not OK, ignore Rx
622 return result;
623
624 #if 0
625 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
626 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
627 (((regEAC & 0x03FF0000)>>16) != 0x36))
628 result |= 0x02;
629 else
630 RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
631 #endif
632
633 return result;
634
635
636 }
637
638 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK(IN PDM_ODM_T pDM_Odm,IN BOOLEAN configPathB)639 phy_PathA_RxIQK(
640 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
641 IN PDM_ODM_T pDM_Odm,
642 #else
643 IN PADAPTER pAdapter,
644 #endif
645 IN BOOLEAN configPathB
646 )
647 {
648 u4Byte regEAC, regE94, regE9C, regEA4, u4tmp;
649 u1Byte result = 0x00;
650 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
651 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
652 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
653 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
654 #endif
655 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
656 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
657 #endif
658 #endif
659 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));
660
661 //1 Get TXIMR setting
662 //modify RXIQK mode table
663 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));
664 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
665 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );
666 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
667 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );
668 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B );
669 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
670
671 //IQK setting
672 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
673 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
674
675 //path-A IQK setting
676 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
677 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
678 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804);
679 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
680
681 //LO calibration setting
682 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
683 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
684
685 //One shot, path A LOK & IQK
686 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
687 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
688 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
689
690 // delay x ms
691 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
692 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
693 ODM_delay_ms(IQK_DELAY_TIME_88E);
694
695
696 // Check failed
697 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
698 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
699 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
700 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
701 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
702 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
703
704 if(!(regEAC & BIT28) &&
705 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
706 (((regE9C & 0x03FF0000)>>16) != 0x42) )
707 result |= 0x01;
708 else //if Tx not OK, ignore Rx
709 return result;
710
711 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
712 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);
713 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));
714
715
716 //1 RX IQK
717 //modify RXIQK mode table
718 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
719 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
720 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );
721 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
722 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );
723 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa );
724 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
725
726 //IQK setting
727 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
728
729 //path-A IQK setting
730 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
731 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
732 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
733 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05);
734
735 //LO calibration setting
736 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
737 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
738
739 //One shot, path A LOK & IQK
740 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
741 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
742 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
743
744 // delay x ms
745 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
746 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
747 ODM_delay_ms(IQK_DELAY_TIME_88E);
748
749 // Check failed
750 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
751 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
752 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
753 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
754 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
755 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
756 regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
757 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
758
759 #if 0
760 if(!(regEAC & BIT28) &&
761 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
762 (((regE9C & 0x03FF0000)>>16) != 0x42) )
763 result |= 0x01;
764 else //if Tx not OK, ignore Rx
765 return result;
766 #endif
767
768 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
769 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
770 (((regEAC & 0x03FF0000)>>16) != 0x36))
771 result |= 0x02;
772 else
773 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n"));
774
775 return result;
776
777
778 }
779
780 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathB_IQK_8188E(IN PDM_ODM_T pDM_Odm)781 phy_PathB_IQK_8188E(
782 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
783 IN PDM_ODM_T pDM_Odm
784 #else
785 IN PADAPTER pAdapter
786 #endif
787 )
788 {
789 u4Byte regEAC, regEB4, regEBC, regEC4, regECC;
790 u1Byte result = 0x00;
791 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
792 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
793 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
794 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
795 #endif
796 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
797 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
798 #endif
799 #endif
800 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
801
802 //One shot, path B LOK & IQK
803 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
804 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
805 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
806
807 // delay x ms
808 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));
809 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
810 ODM_delay_ms(IQK_DELAY_TIME_88E);
811
812 // Check failed
813 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
814 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
815 regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord);
816 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4));
817 regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord);
818 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC));
819 regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord);
820 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4));
821 regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord);
822 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC));
823
824 if(!(regEAC & BIT31) &&
825 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
826 (((regEBC & 0x03FF0000)>>16) != 0x42))
827 result |= 0x01;
828 else
829 return result;
830
831 if(!(regEAC & BIT30) &&
832 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
833 (((regECC & 0x03FF0000)>>16) != 0x36))
834 result |= 0x02;
835 else
836 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
837
838
839 return result;
840
841 }
842
843 VOID
_PHY_PathAFillIQKMatrix(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bIQKOK,IN s4Byte result[][8],IN u1Byte final_candidate,IN BOOLEAN bTxOnly)844 _PHY_PathAFillIQKMatrix(
845 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
846 IN PDM_ODM_T pDM_Odm,
847 #else
848 IN PADAPTER pAdapter,
849 #endif
850 IN BOOLEAN bIQKOK,
851 IN s4Byte result[][8],
852 IN u1Byte final_candidate,
853 IN BOOLEAN bTxOnly
854 )
855 {
856 u4Byte Oldval_0, X, TX0_A, reg;
857 s4Byte Y, TX0_C;
858 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
859 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
860 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
861 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
862 #endif
863 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
864 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
865 #endif
866 #endif
867 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
868
869 if(final_candidate == 0xFF)
870 return;
871
872 else if(bIQKOK)
873 {
874 Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
875
876 X = result[final_candidate][0];
877 if ((X & 0x00000200) != 0)
878 X = X | 0xFFFFFC00;
879 TX0_A = (X * Oldval_0) >> 8;
880 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
881 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
882
883 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
884
885 Y = result[final_candidate][1];
886 if ((Y & 0x00000200) != 0)
887 Y = Y | 0xFFFFFC00;
888
889
890 TX0_C = (Y * Oldval_0) >> 8;
891 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
892 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
893 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
894
895 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
896
897 if(bTxOnly)
898 {
899 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n"));
900 return;
901 }
902
903 reg = result[final_candidate][2];
904 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
905 if( RTL_ABS(reg ,0x100) >= 16)
906 reg = 0x100;
907 #endif
908 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);
909
910 reg = result[final_candidate][3] & 0x3F;
911 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);
912
913 reg = (result[final_candidate][3] >> 6) & 0xF;
914 ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
915 }
916 }
917
918 VOID
_PHY_PathBFillIQKMatrix(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bIQKOK,IN s4Byte result[][8],IN u1Byte final_candidate,IN BOOLEAN bTxOnly)919 _PHY_PathBFillIQKMatrix(
920 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
921 IN PDM_ODM_T pDM_Odm,
922 #else
923 IN PADAPTER pAdapter,
924 #endif
925 IN BOOLEAN bIQKOK,
926 IN s4Byte result[][8],
927 IN u1Byte final_candidate,
928 IN BOOLEAN bTxOnly //do Tx only
929 )
930 {
931 u4Byte Oldval_1, X, TX1_A, reg;
932 s4Byte Y, TX1_C;
933 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
934 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
935 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
936 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
937 #endif
938 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
939 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
940 #endif
941 #endif
942 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
943
944 if(final_candidate == 0xFF)
945 return;
946
947 else if(bIQKOK)
948 {
949 Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
950
951 X = result[final_candidate][4];
952 if ((X & 0x00000200) != 0)
953 X = X | 0xFFFFFC00;
954 TX1_A = (X * Oldval_1) >> 8;
955 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
956 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
957
958 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
959
960 Y = result[final_candidate][5];
961 if ((Y & 0x00000200) != 0)
962 Y = Y | 0xFFFFFC00;
963
964 TX1_C = (Y * Oldval_1) >> 8;
965 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
966 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
967 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
968
969 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
970
971 if(bTxOnly)
972 return;
973
974 reg = result[final_candidate][6];
975 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
976
977 reg = result[final_candidate][7] & 0x3F;
978 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
979
980 reg = (result[final_candidate][7] >> 6) & 0xF;
981 ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);
982 }
983 }
984
985 //
986 // 2011/07/26 MH Add an API for testing IQK fail case.
987 //
988 // MP Already declare in odm.c
989 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN)
990 BOOLEAN
ODM_CheckPowerStatus(IN PADAPTER Adapter)991 ODM_CheckPowerStatus(
992 IN PADAPTER Adapter)
993 {
994 /*
995 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
996 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
997 RT_RF_POWER_STATE rtState;
998 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
999
1000 // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
1001 if (pMgntInfo->init_adpt_in_progress == TRUE)
1002 {
1003 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
1004 return TRUE;
1005 }
1006
1007 //
1008 // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
1009 //
1010 rtw_hal_get_hwreg(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
1011 if (rtw_is_drv_stopped(padapter) || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
1012 {
1013 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to drv_stop: %s /%d/%d\n",
1014 rtw_is_drv_stopped(padapter)?"True":"False", Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
1015 return FALSE;
1016 }
1017 */
1018 return TRUE;
1019 }
1020 #endif
1021
1022 VOID
_PHY_SaveADDARegisters(IN PDM_ODM_T pDM_Odm,IN pu4Byte ADDAReg,IN pu4Byte ADDABackup,IN u4Byte RegisterNum)1023 _PHY_SaveADDARegisters(
1024 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1025 IN PDM_ODM_T pDM_Odm,
1026 #else
1027 IN PADAPTER pAdapter,
1028 #endif
1029 IN pu4Byte ADDAReg,
1030 IN pu4Byte ADDABackup,
1031 IN u4Byte RegisterNum
1032 )
1033 {
1034 u4Byte i;
1035 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1036 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1037 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1038 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1039 #endif
1040 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1041 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1042 #endif
1043
1044 if (ODM_CheckPowerStatus(pAdapter) == FALSE)
1045 return;
1046 #endif
1047
1048 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
1049 for( i = 0 ; i < RegisterNum ; i++){
1050 ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);
1051 }
1052 }
1053
1054
1055 VOID
_PHY_SaveMACRegisters(IN PDM_ODM_T pDM_Odm,IN pu4Byte MACReg,IN pu4Byte MACBackup)1056 _PHY_SaveMACRegisters(
1057 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1058 IN PDM_ODM_T pDM_Odm,
1059 #else
1060 IN PADAPTER pAdapter,
1061 #endif
1062 IN pu4Byte MACReg,
1063 IN pu4Byte MACBackup
1064 )
1065 {
1066 u4Byte i;
1067 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1068 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1069 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1070 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1071 #endif
1072 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1073 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1074 #endif
1075 #endif
1076 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
1077 for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
1078 MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
1079 }
1080 MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);
1081
1082 }
1083
1084
1085 VOID
_PHY_ReloadADDARegisters(IN PDM_ODM_T pDM_Odm,IN pu4Byte ADDAReg,IN pu4Byte ADDABackup,IN u4Byte RegiesterNum)1086 _PHY_ReloadADDARegisters(
1087 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1088 IN PDM_ODM_T pDM_Odm,
1089 #else
1090 IN PADAPTER pAdapter,
1091 #endif
1092 IN pu4Byte ADDAReg,
1093 IN pu4Byte ADDABackup,
1094 IN u4Byte RegiesterNum
1095 )
1096 {
1097 u4Byte i;
1098 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1099 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1100 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1101 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1102 #endif
1103 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1104 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1105 #endif
1106 #endif
1107
1108 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
1109 for(i = 0 ; i < RegiesterNum; i++)
1110 {
1111 ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);
1112 }
1113 }
1114
1115 VOID
_PHY_ReloadMACRegisters(IN PDM_ODM_T pDM_Odm,IN pu4Byte MACReg,IN pu4Byte MACBackup)1116 _PHY_ReloadMACRegisters(
1117 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1118 IN PDM_ODM_T pDM_Odm,
1119 #else
1120 IN PADAPTER pAdapter,
1121 #endif
1122 IN pu4Byte MACReg,
1123 IN pu4Byte MACBackup
1124 )
1125 {
1126 u4Byte i;
1127 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1128 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1129 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1130 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1131 #endif
1132 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1133 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1134 #endif
1135 #endif
1136 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
1137 for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
1138 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);
1139 }
1140 ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
1141 }
1142
1143
1144 VOID
_PHY_PathADDAOn(IN PDM_ODM_T pDM_Odm,IN pu4Byte ADDAReg,IN BOOLEAN isPathAOn,IN BOOLEAN is2T)1145 _PHY_PathADDAOn(
1146 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1147 IN PDM_ODM_T pDM_Odm,
1148 #else
1149 IN PADAPTER pAdapter,
1150 #endif
1151 IN pu4Byte ADDAReg,
1152 IN BOOLEAN isPathAOn,
1153 IN BOOLEAN is2T
1154 )
1155 {
1156 u4Byte pathOn;
1157 u4Byte i;
1158 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1159 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1160 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1161 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1162 #endif
1163 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1164 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1165 #endif
1166 #endif
1167 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
1168
1169 pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
1170 if(FALSE == is2T){
1171 pathOn = 0x0bdb25a0;
1172 ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
1173 }
1174 else{
1175 ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);
1176 }
1177
1178 for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
1179 ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);
1180 }
1181
1182 }
1183
1184 VOID
_PHY_MACSettingCalibration(IN PDM_ODM_T pDM_Odm,IN pu4Byte MACReg,IN pu4Byte MACBackup)1185 _PHY_MACSettingCalibration(
1186 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1187 IN PDM_ODM_T pDM_Odm,
1188 #else
1189 IN PADAPTER pAdapter,
1190 #endif
1191 IN pu4Byte MACReg,
1192 IN pu4Byte MACBackup
1193 )
1194 {
1195 u4Byte i = 0;
1196 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1197 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1198 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1199 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1200 #endif
1201 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1202 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1203 #endif
1204 #endif
1205 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
1206
1207 ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
1208
1209 for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
1210 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));
1211 }
1212 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5)));
1213
1214 }
1215
1216 VOID
_PHY_PathAStandBy(IN PDM_ODM_T pDM_Odm)1217 _PHY_PathAStandBy(
1218 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1219 IN PDM_ODM_T pDM_Odm
1220 #else
1221 IN PADAPTER pAdapter
1222 #endif
1223 )
1224 {
1225 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1226 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1227 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1228 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1229 #endif
1230 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1231 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1232 #endif
1233 #endif
1234 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n"));
1235
1236 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x0);
1237 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);
1238 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1239 }
1240
1241 VOID
_PHY_PIModeSwitch(IN PDM_ODM_T pDM_Odm,IN BOOLEAN PIMode)1242 _PHY_PIModeSwitch(
1243 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1244 IN PDM_ODM_T pDM_Odm,
1245 #else
1246 IN PADAPTER pAdapter,
1247 #endif
1248 IN BOOLEAN PIMode
1249 )
1250 {
1251 u4Byte mode;
1252 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1253 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1254 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1255 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1256 #endif
1257 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1258 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1259 #endif
1260 #endif
1261 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
1262
1263 mode = PIMode ? 0x01000100 : 0x01000000;
1264 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
1265 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
1266 }
1267
1268 BOOLEAN
phy_SimularityCompare_8188E(IN PDM_ODM_T pDM_Odm,IN s4Byte result[][8],IN u1Byte c1,IN u1Byte c2)1269 phy_SimularityCompare_8188E(
1270 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1271 IN PDM_ODM_T pDM_Odm,
1272 #else
1273 IN PADAPTER pAdapter,
1274 #endif
1275 IN s4Byte result[][8],
1276 IN u1Byte c1,
1277 IN u1Byte c2
1278 )
1279 {
1280 u4Byte i, j, diff, SimularityBitMap, bound = 0;
1281 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1282 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1283 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1284 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1285 #endif
1286 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1287 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1288 #endif
1289 #endif
1290 u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
1291 BOOLEAN bResult = TRUE;
1292 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1293 BOOLEAN is2T = IS_2T2R( pHalData->VersionID);
1294 #else
1295 BOOLEAN is2T = 0;
1296 #endif
1297
1298 if(is2T)
1299 bound = 8;
1300 else
1301 bound = 4;
1302
1303 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2));
1304
1305
1306 SimularityBitMap = 0;
1307
1308 for( i = 0; i < bound; i++ )
1309 {
1310 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
1311 if (diff > MAX_TOLERANCE)
1312 {
1313 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i]));
1314
1315 if((i == 2 || i == 6) && !SimularityBitMap)
1316 {
1317 if(result[c1][i]+result[c1][i+1] == 0)
1318 final_candidate[(i/4)] = c2;
1319 else if (result[c2][i]+result[c2][i+1] == 0)
1320 final_candidate[(i/4)] = c1;
1321 else
1322 SimularityBitMap = SimularityBitMap|(1<<i);
1323 }
1324 else
1325 SimularityBitMap = SimularityBitMap|(1<<i);
1326 }
1327 }
1328
1329 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E SimularityBitMap %d !!!\n", SimularityBitMap));
1330
1331 if ( SimularityBitMap == 0)
1332 {
1333 for( i = 0; i < (bound/4); i++ )
1334 {
1335 if(final_candidate[i] != 0xFF)
1336 {
1337 for( j = i*4; j < (i+1)*4-2; j++)
1338 result[3][j] = result[final_candidate[i]][j];
1339 bResult = FALSE;
1340 }
1341 }
1342 return bResult;
1343 }
1344 else if (!(SimularityBitMap & 0x0F)) //path A OK
1345 {
1346 for(i = 0; i < 4; i++)
1347 result[3][i] = result[c1][i];
1348 return FALSE;
1349 }
1350 else if (!(SimularityBitMap & 0xF0) && is2T) //path B OK
1351 {
1352 for(i = 4; i < 8; i++)
1353 result[3][i] = result[c1][i];
1354 return FALSE;
1355 }
1356 else
1357 return FALSE;
1358
1359 }
1360
1361
1362
1363 VOID
phy_IQCalibrate_8188E(IN PDM_ODM_T pDM_Odm,IN s4Byte result[][8],IN u1Byte t,IN BOOLEAN is2T)1364 phy_IQCalibrate_8188E(
1365 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1366 IN PDM_ODM_T pDM_Odm,
1367 #else
1368 IN PADAPTER pAdapter,
1369 #endif
1370 IN s4Byte result[][8],
1371 IN u1Byte t,
1372 IN BOOLEAN is2T
1373 )
1374 {
1375 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1376 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1377 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1378 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1379 #endif
1380 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1381 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1382 #endif
1383 #endif
1384 u4Byte i;
1385 u1Byte PathAOK=0, PathBOK=0;
1386 u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
1387 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
1388 rRx_Wait_CCA, rTx_CCK_RFON,
1389 rTx_CCK_BBON, rTx_OFDM_RFON,
1390 rTx_OFDM_BBON, rTx_To_Rx,
1391 rTx_To_Tx, rRx_CCK,
1392 rRx_OFDM, rRx_Wait_RIFS,
1393 rRx_TO_Rx, rStandby,
1394 rSleep, rPMPD_ANAEN };
1395 u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
1396 REG_TXPAUSE, REG_BCN_CTRL,
1397 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1398
1399 //since 92C & 92D have the different define in IQK_BB_REG
1400 u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
1401 rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
1402 rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
1403 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
1404 rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting
1405 };
1406
1407 u4Byte retryCount = 2;
1408
1409 if (pDM_Odm->mp_mode == TRUE)
1410 retryCount = 9;
1411
1412 // Note: IQ calibration must be performed after loading
1413 // PHY_REG.txt , and radio_a, radio_b.txt
1414
1415 //u4Byte bbvalue;
1416
1417 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
1418 #ifdef MP_TEST
1419 if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
1420 retryCount = 9;
1421 #endif
1422 #endif
1423
1424
1425 if(t==0)
1426 {
1427 // bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
1428 // RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));
1429
1430 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
1431
1432 // Save ADDA parameters, turn Path A ADDA on
1433 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1434 _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1435 _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1436 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1437 #else
1438 _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1439 _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1440 _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1441 #endif
1442 }
1443 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
1444
1445 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1446
1447 _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
1448 #else
1449 _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T);
1450 #endif
1451
1452
1453 if(t==0)
1454 {
1455 pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
1456 }
1457
1458 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
1459 // Switch BB to PI mode to do IQ Calibration.
1460 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1461 _PHY_PIModeSwitch(pAdapter, TRUE);
1462 #else
1463 _PHY_PIModeSwitch(pDM_Odm, TRUE);
1464 #endif
1465 }
1466
1467
1468 //MAC settings
1469 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1470 _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1471 #else
1472 _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1473 #endif
1474
1475 //BB setting
1476 //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);
1477 ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf);
1478 ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
1479 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
1480 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
1481
1482
1483 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
1484 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
1485 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
1486 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
1487
1488
1489 if(is2T)
1490 {
1491 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
1492 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
1493 }
1494
1495 //Page B init
1496 //AP or IQK
1497 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1498
1499 if(is2T)
1500 {
1501 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);
1502 }
1503
1504 // IQ calibration setting
1505 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));
1506 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000);
1507 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1508 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
1509
1510 for(i = 0 ; i < retryCount ; i++){
1511 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1512 PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);
1513 #else
1514 PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T);
1515 #endif
1516 // if(PathAOK == 0x03){
1517 if(PathAOK == 0x01){
1518 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
1519 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1520 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1521 break;
1522 }
1523 #if 0
1524 else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
1525 {
1526 RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
1527
1528 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1529 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1530 }
1531 #endif
1532 }
1533
1534 for(i = 0 ; i < retryCount ; i++){
1535 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1536 PathAOK = phy_PathA_RxIQK(pAdapter, is2T);
1537 #else
1538 PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T);
1539 #endif
1540 if(PathAOK == 0x03){
1541 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
1542 // result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1543 // result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
1544 result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1545 result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
1546 break;
1547 }
1548 else
1549 {
1550 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
1551 }
1552 }
1553
1554 if(0x00 == PathAOK){
1555 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
1556 }
1557
1558 if(is2T){
1559 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1560 _PHY_PathAStandBy(pAdapter);
1561
1562 // Turn Path B ADDA on
1563 _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
1564 #else
1565 _PHY_PathAStandBy(pDM_Odm);
1566
1567 // Turn Path B ADDA on
1568 _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T);
1569 #endif
1570
1571 for(i = 0 ; i < retryCount ; i++){
1572 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1573 PathBOK = phy_PathB_IQK_8188E(pAdapter);
1574 #else
1575 PathBOK = phy_PathB_IQK_8188E(pDM_Odm);
1576 #endif
1577 if(PathBOK == 0x03){
1578 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));
1579 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1580 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1581 result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
1582 result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
1583 break;
1584 }
1585 else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK
1586 {
1587 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n"));
1588 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1589 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
1590 }
1591 }
1592
1593 if(0x00 == PathBOK){
1594 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
1595 }
1596 }
1597
1598 //Back to BB mode, load original value
1599 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
1600 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);
1601
1602 if(t!=0)
1603 {
1604 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
1605 // Switch back BB to SI mode after finish IQ Calibration.
1606 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1607 _PHY_PIModeSwitch(pAdapter, FALSE);
1608 #else
1609 _PHY_PIModeSwitch(pDM_Odm, FALSE);
1610 #endif
1611 }
1612 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1613
1614 // Reload ADDA power saving parameters
1615 _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1616
1617 // Reload MAC parameters
1618 _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1619
1620 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1621 #else
1622 // Reload ADDA power saving parameters
1623 _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
1624
1625 // Reload MAC parameters
1626 _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
1627
1628 _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
1629 #endif
1630
1631
1632 // Restore RX initial gain
1633 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
1634 if(is2T){
1635 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
1636 }
1637
1638 //load 0xe30 IQC default value
1639 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1640 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
1641
1642 }
1643 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n"));
1644
1645 }
1646
1647
1648 VOID
phy_LCCalibrate_8188E(IN PDM_ODM_T pDM_Odm,IN BOOLEAN is2T)1649 phy_LCCalibrate_8188E(
1650 IN PDM_ODM_T pDM_Odm,
1651 IN BOOLEAN is2T
1652 )
1653 {
1654 u1Byte tmpReg;
1655 u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
1656 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1657 PADAPTER pAdapter = pDM_Odm->Adapter;
1658 #endif
1659 //Check continuous TX and Packet TX
1660 tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);
1661
1662 if((tmpReg&0x70) != 0) //Deal with contisuous TX case
1663 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX
1664 else // Deal with Packet TX case
1665 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues
1666
1667 if((tmpReg&0x70) != 0)
1668 {
1669 //1. Read original RF mode
1670 //Path-A
1671 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1672 RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);
1673
1674 //Path-B
1675 if(is2T)
1676 RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits);
1677 #else
1678 RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits);
1679
1680 //Path-B
1681 if(is2T)
1682 RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits);
1683 #endif
1684
1685 //2. Set RF mode = standby mode
1686 //Path-A
1687 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
1688
1689 //Path-B
1690 if(is2T)
1691 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
1692 }
1693
1694 //3. Read RF reg18
1695 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1696 LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
1697 #else
1698 LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
1699 #endif
1700
1701 //4. Set LC calibration begin bit15
1702 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
1703
1704 ODM_delay_ms(100);
1705
1706
1707 //Restore original situation
1708 if((tmpReg&0x70) != 0) //Deal with contisuous TX case
1709 {
1710 //Path-A
1711 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);
1712 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
1713
1714 //Path-B
1715 if(is2T)
1716 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
1717 }
1718 else // Deal with Packet TX case
1719 {
1720 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
1721 }
1722 }
1723
1724 //Analog Pre-distortion calibration
1725 #define APK_BB_REG_NUM 8
1726 #define APK_CURVE_REG_NUM 4
1727 #define PATH_NUM 2
1728
1729 VOID
phy_APCalibrate_8188E(IN PDM_ODM_T pDM_Odm,IN s1Byte delta,IN BOOLEAN is2T)1730 phy_APCalibrate_8188E(
1731 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1732 IN PDM_ODM_T pDM_Odm,
1733 #else
1734 IN PADAPTER pAdapter,
1735 #endif
1736 IN s1Byte delta,
1737 IN BOOLEAN is2T
1738 )
1739 {
1740 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1741 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1742 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1743 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1744 #endif
1745 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1746 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
1747 #endif
1748 #endif
1749 u4Byte regD[PATH_NUM];
1750 u4Byte tmpReg, index, offset, apkbound;
1751 u1Byte path, i, pathbound = PATH_NUM;
1752 u4Byte BB_backup[APK_BB_REG_NUM];
1753 u4Byte BB_REG[APK_BB_REG_NUM] = {
1754 rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
1755 rFPGA0_RFMOD, rOFDM0_TRMuxPar,
1756 rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
1757 rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
1758 u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
1759 0x00000020, 0x00a05430, 0x02040000,
1760 0x000800e4, 0x00204000 };
1761 u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = {
1762 0x00000020, 0x00a05430, 0x02040000,
1763 0x000800e4, 0x22204000 };
1764
1765 u4Byte AFE_backup[IQK_ADDA_REG_NUM];
1766 u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
1767 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
1768 rRx_Wait_CCA, rTx_CCK_RFON,
1769 rTx_CCK_BBON, rTx_OFDM_RFON,
1770 rTx_OFDM_BBON, rTx_To_Rx,
1771 rTx_To_Tx, rRx_CCK,
1772 rRx_OFDM, rRx_Wait_RIFS,
1773 rRx_TO_Rx, rStandby,
1774 rSleep, rPMPD_ANAEN };
1775
1776 u4Byte MAC_backup[IQK_MAC_REG_NUM];
1777 u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
1778 REG_TXPAUSE, REG_BCN_CTRL,
1779 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
1780
1781 u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1782 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1783 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1784 };
1785
1786 u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1787 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
1788 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1789 };
1790
1791 u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1792 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1793 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1794 };
1795
1796 u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1797 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
1798 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1799 };
1800
1801 u4Byte AFE_on_off[PATH_NUM] = {
1802 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
1803
1804 u4Byte APK_offset[PATH_NUM] = {
1805 rConfig_AntA, rConfig_AntB};
1806
1807 u4Byte APK_normal_offset[PATH_NUM] = {
1808 rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
1809
1810 u4Byte APK_value[PATH_NUM] = {
1811 0x92fc0000, 0x12fc0000};
1812
1813 u4Byte APK_normal_value[PATH_NUM] = {
1814 0x92680000, 0x12680000};
1815
1816 s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = {
1817 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1818 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1819 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1820 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1821 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1822 };
1823
1824 u4Byte APK_normal_setting_value_1[13] = {
1825 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1826 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1827 0x12680000, 0x00880000, 0x00880000
1828 };
1829
1830 u4Byte APK_normal_setting_value_2[16] = {
1831 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1832 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1833 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1834 0x00050006
1835 };
1836
1837 u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
1838 // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
1839
1840 s4Byte BB_offset, delta_V, delta_offset;
1841
1842 #if MP_DRIVER == 1
1843 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1844 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
1845 #else
1846 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
1847 #endif
1848
1849 if (pDM_Odm->mp_mode == TRUE)
1850 {
1851 pMptCtx->APK_bound[0] = 45;
1852 pMptCtx->APK_bound[1] = 52;
1853 }
1854 #endif
1855
1856 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
1857 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
1858 if(!is2T)
1859 pathbound = 1;
1860
1861 //2 FOR NORMAL CHIP SETTINGS
1862
1863 // Temporarily do not allow normal driver to do the following settings because these offset
1864 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
1865 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
1866 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
1867 //#if MP_DRIVER != 1
1868 if (pDM_Odm->mp_mode == FALSE)
1869 return;
1870 //#endif
1871 //settings adjust for normal chip
1872 for(index = 0; index < PATH_NUM; index ++)
1873 {
1874 APK_offset[index] = APK_normal_offset[index];
1875 APK_value[index] = APK_normal_value[index];
1876 AFE_on_off[index] = 0x6fdb25a4;
1877 }
1878
1879 for(index = 0; index < APK_BB_REG_NUM; index ++)
1880 {
1881 for(path = 0; path < pathbound; path++)
1882 {
1883 APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
1884 APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
1885 }
1886 BB_AP_MODE[index] = BB_normal_AP_MODE[index];
1887 }
1888
1889 apkbound = 6;
1890
1891 //save BB default value
1892 for(index = 0; index < APK_BB_REG_NUM ; index++)
1893 {
1894 if(index == 0) //skip
1895 continue;
1896 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
1897 }
1898
1899 //save MAC default value
1900 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1901 _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
1902
1903 //save AFE default value
1904 _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
1905 #else
1906 _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
1907
1908 //save AFE default value
1909 _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
1910 #endif
1911
1912 for(path = 0; path < pathbound; path++)
1913 {
1914
1915
1916 if(path == ODM_RF_PATH_A)
1917 {
1918 //path A APK
1919 //load APK setting
1920 //path-A
1921 offset = rPdp_AntA;
1922 for(index = 0; index < 11; index ++)
1923 {
1924 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1925 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
1926
1927 offset += 0x04;
1928 }
1929
1930 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
1931
1932 offset = rConfig_AntA;
1933 for(; index < 13; index ++)
1934 {
1935 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1936 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
1937
1938 offset += 0x04;
1939 }
1940
1941 //page-B1
1942 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
1943
1944 //path A
1945 offset = rPdp_AntA;
1946 for(index = 0; index < 16; index++)
1947 {
1948 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
1949 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
1950
1951 offset += 0x04;
1952 }
1953 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
1954 }
1955 else if(path == ODM_RF_PATH_B)
1956 {
1957 //path B APK
1958 //load APK setting
1959 //path-B
1960 offset = rPdp_AntB;
1961 for(index = 0; index < 10; index ++)
1962 {
1963 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1964 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
1965
1966 offset += 0x04;
1967 }
1968 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
1969 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
1970 PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
1971 #else
1972 PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
1973 #endif
1974
1975 offset = rConfig_AntA;
1976 index = 11;
1977 for(; index < 13; index ++) //offset 0xb68, 0xb6c
1978 {
1979 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
1980 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
1981
1982 offset += 0x04;
1983 }
1984
1985 //page-B1
1986 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
1987
1988 //path B
1989 offset = 0xb60;
1990 for(index = 0; index < 16; index++)
1991 {
1992 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
1993 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
1994
1995 offset += 0x04;
1996 }
1997 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0);
1998 }
1999
2000 //save RF default value
2001 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2002 regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);
2003 #else
2004 regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord);
2005 #endif
2006
2007 //Path A AFE all on, path B AFE All off or vise versa
2008 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
2009 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
2010 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));
2011
2012 //BB to AP mode
2013 if(path == 0)
2014 {
2015 for(index = 0; index < APK_BB_REG_NUM ; index++)
2016 {
2017
2018 if(index == 0) //skip
2019 continue;
2020 else if (index < 5)
2021 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
2022 else if (BB_REG[index] == 0x870)
2023 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
2024 else
2025 ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);
2026 }
2027
2028 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2029 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2030 }
2031 else //path B
2032 {
2033 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
2034 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
2035
2036 }
2037
2038 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));
2039
2040 //MAC settings
2041 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2042 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
2043 #else
2044 _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
2045 #endif
2046
2047 if(path == ODM_RF_PATH_A) //Path B to standby mode
2048 {
2049 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
2050 }
2051 else //Path A to standby mode
2052 {
2053 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
2054 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
2055 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);
2056 }
2057
2058 delta_offset = ((delta+14)/2);
2059 if(delta_offset < 0)
2060 delta_offset = 0;
2061 else if (delta_offset > 12)
2062 delta_offset = 12;
2063
2064 //AP calibration
2065 for(index = 0; index < APK_BB_REG_NUM; index++)
2066 {
2067 if(index != 1) //only DO PA11+PAD01001, AP RF setting
2068 continue;
2069
2070 tmpReg = APK_RF_init_value[path][index];
2071 #if 1
2072 if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)
2073 {
2074 BB_offset = (tmpReg & 0xF0000) >> 16;
2075
2076 if(!(tmpReg & BIT15)) //sign bit 0
2077 {
2078 BB_offset = -BB_offset;
2079 }
2080
2081 delta_V = APK_delta_mapping[index][delta_offset];
2082
2083 BB_offset += delta_V;
2084
2085 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));
2086
2087 if(BB_offset < 0)
2088 {
2089 tmpReg = tmpReg & (~BIT15);
2090 BB_offset = -BB_offset;
2091 }
2092 else
2093 {
2094 tmpReg = tmpReg | BIT15;
2095 }
2096 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
2097 }
2098 #endif
2099
2100 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e);
2101 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2102 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));
2103 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
2104 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));
2105 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg);
2106 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));
2107 #else
2108 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));
2109 ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
2110 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));
2111 ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);
2112 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));
2113 #endif
2114
2115 // PA11+PAD01111, one shot
2116 i = 0;
2117 do
2118 {
2119 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);
2120 {
2121 ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);
2122 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
2123 ODM_delay_ms(3);
2124 ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);
2125 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
2126
2127 ODM_delay_ms(20);
2128 }
2129 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2130
2131 if(path == ODM_RF_PATH_A)
2132 tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);
2133 else
2134 tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);
2135 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));
2136
2137
2138 i++;
2139 }
2140 while(tmpReg > apkbound && i < 4);
2141
2142 APK_result[path][index] = tmpReg;
2143 }
2144 }
2145
2146 //reload MAC default value
2147 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2148 _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
2149 #else
2150 _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
2151 #endif
2152
2153 //reload BB default value
2154 for(index = 0; index < APK_BB_REG_NUM ; index++)
2155 {
2156
2157 if(index == 0) //skip
2158 continue;
2159 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
2160 }
2161
2162 //reload AFE default value
2163 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2164 _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2165 #else
2166 _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2167 #endif
2168
2169 //reload RF path default value
2170 for(path = 0; path < pathbound; path++)
2171 {
2172 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]);
2173 if(path == ODM_RF_PATH_B)
2174 {
2175 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
2176 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
2177 }
2178
2179 //note no index == 0
2180 if (APK_result[path][1] > 6)
2181 APK_result[path][1] = 6;
2182 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
2183 }
2184
2185 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
2186
2187
2188 for(path = 0; path < pathbound; path++)
2189 {
2190 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord,
2191 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
2192 if(path == ODM_RF_PATH_A)
2193 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord,
2194 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
2195 else
2196 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord,
2197 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
2198 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2199 if(!IS_HARDWARE_TYPE_8723A(pAdapter))
2200 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
2201 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
2202 #endif
2203 }
2204
2205 pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;
2206
2207 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));
2208 }
2209
2210
2211
2212 #define DP_BB_REG_NUM 7
2213 #define DP_RF_REG_NUM 1
2214 #define DP_RETRY_LIMIT 10
2215 #define DP_PATH_NUM 2
2216 #define DP_DPK_NUM 3
2217 #define DP_DPK_VALUE_NUM 2
2218
2219
2220
2221
2222
2223 VOID
PHY_IQCalibrate_8188E(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bReCovery)2224 PHY_IQCalibrate_8188E(
2225 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2226 IN PDM_ODM_T pDM_Odm,
2227 #else
2228 IN PADAPTER pAdapter,
2229 #endif
2230 IN BOOLEAN bReCovery
2231 )
2232 {
2233 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2234 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2235
2236 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2237 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
2238 #else // (DM_ODM_SUPPORT_TYPE == ODM_CE)
2239 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
2240 #endif
2241
2242 #if (MP_DRIVER == 1)
2243 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2244 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
2245 #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
2246 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2247 #endif
2248 #endif//(MP_DRIVER == 1)
2249 #endif
2250
2251 s4Byte result[4][8]; //last is final result
2252 u1Byte i, final_candidate, Indexforchannel;
2253 u1Byte channelToIQK = 7;
2254 BOOLEAN bPathAOK, bPathBOK;
2255 s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
2256 BOOLEAN is12simular, is13simular, is23simular;
2257 BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
2258 u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
2259 rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
2260 rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
2261 rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
2262 rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
2263 rOFDM0_RxIQExtAnta};
2264 u4Byte StartTime;
2265 s4Byte ProgressingTime;
2266
2267 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) )
2268 if (ODM_CheckPowerStatus(pAdapter) == FALSE)
2269 return;
2270 #else
2271 prtl8192cd_priv priv = pDM_Odm->priv;
2272
2273 #ifdef MP_TEST
2274 if(priv->pshare->rf_ft_var.mp_specific)
2275 {
2276 if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))
2277 return;
2278 }
2279 #endif
2280
2281 if(priv->pshare->IQK_88E_done)
2282 bReCovery= 1;
2283 priv->pshare->IQK_88E_done = 1;
2284
2285 #endif
2286
2287 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2288 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
2289 {
2290 return;
2291 }
2292 #endif
2293
2294 #if MP_DRIVER == 1
2295 if (pDM_Odm->mp_mode == TRUE)
2296 {
2297 bStartContTx = pMptCtx->bStartContTx;
2298 bSingleTone = pMptCtx->bSingleTone;
2299 bCarrierSuppression = pMptCtx->bCarrierSuppression;
2300 }
2301 #endif
2302
2303 // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
2304 if(bSingleTone || bCarrierSuppression)
2305 return;
2306
2307 #if DISABLE_BB_RF
2308 return;
2309 #endif
2310
2311 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
2312 return;
2313
2314 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))
2315 if (bReCovery)
2316 #else//for ODM_WIN
2317 if (bReCovery && (!pAdapter->bInHctTest)) /* YJ,add for PowerTest,120405 */
2318 #endif
2319 {
2320 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n"));
2321 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2322 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
2323 #else
2324 _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
2325 #endif
2326 return;
2327 }
2328
2329
2330 ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
2331 pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE;
2332 ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
2333
2334
2335
2336 StartTime = ODM_GetCurrentTime( pDM_Odm);
2337 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
2338
2339
2340
2341 for(i = 0; i < 8; i++)
2342 {
2343 result[0][i] = 0;
2344 result[1][i] = 0;
2345 result[2][i] = 0;
2346 result[3][i] = 0;
2347 }
2348 final_candidate = 0xff;
2349 bPathAOK = FALSE;
2350 bPathBOK = FALSE;
2351 is12simular = FALSE;
2352 is23simular = FALSE;
2353 is13simular = FALSE;
2354
2355
2356 for (i=0; i<3; i++)
2357 {
2358 {
2359 // For 88C 1T1R
2360 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2361 phy_IQCalibrate_8188E(pAdapter, result, i, FALSE);
2362 #else
2363 phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE);
2364 #endif
2365 }
2366
2367 if(i == 1)
2368 {
2369 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2370 is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1);
2371 #else
2372 is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1);
2373 #endif
2374 if(is12simular)
2375 {
2376 final_candidate = 0;
2377 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));
2378 break;
2379 }
2380 }
2381
2382 if(i == 2)
2383 {
2384 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2385 is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2);
2386 #else
2387 is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2);
2388 #endif
2389 if(is13simular)
2390 {
2391 final_candidate = 0;
2392 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));
2393
2394 break;
2395 }
2396 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2397 is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2);
2398 #else
2399 is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2);
2400 #endif
2401 if(is23simular)
2402 {
2403 final_candidate = 1;
2404 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));
2405 }
2406 else
2407 {
2408 for(i = 0; i < 8; i++)
2409 RegTmp += result[3][i];
2410
2411 if(RegTmp != 0)
2412 final_candidate = 3;
2413 else
2414 final_candidate = 0xFF;
2415 }
2416 }
2417 }
2418 // RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));
2419
2420 for (i=0; i<4; i++)
2421 {
2422 RegE94 = result[i][0];
2423 RegE9C = result[i][1];
2424 RegEA4 = result[i][2];
2425 RegEAC = result[i][3];
2426 RegEB4 = result[i][4];
2427 RegEBC = result[i][5];
2428 RegEC4 = result[i][6];
2429 RegECC = result[i][7];
2430 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
2431 }
2432
2433 if(final_candidate != 0xff)
2434 {
2435 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
2436 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
2437 RegEA4 = result[final_candidate][2];
2438 RegEAC = result[final_candidate][3];
2439 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
2440 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
2441 RegEC4 = result[final_candidate][6];
2442 RegECC = result[final_candidate][7];
2443 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate));
2444 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
2445 bPathAOK = bPathBOK = TRUE;
2446 }
2447 else
2448 {
2449 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n"));
2450
2451 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value
2452 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value
2453 }
2454
2455 if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
2456 {
2457 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2458 _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
2459 #else
2460 _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));
2461 #endif
2462 }
2463
2464 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2465 Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
2466 #else
2467 Indexforchannel = 0;
2468 #endif
2469
2470 //To Fix BSOD when final_candidate is 0xff
2471 //by sherry 20120321
2472 if(final_candidate < 4)
2473 {
2474 for(i = 0; i < IQK_Matrix_REG_NUM; i++)
2475 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
2476 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;
2477 }
2478 //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
2479 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
2480 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2481
2482 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
2483 #else
2484 _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);
2485 #endif
2486
2487 ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
2488 pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;
2489 ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
2490
2491 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
2492 ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);
2493 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime));
2494
2495 }
2496
2497
2498 VOID
PHY_LCCalibrate_8188E(PVOID pDM_VOID)2499 PHY_LCCalibrate_8188E(
2500 PVOID pDM_VOID
2501 )
2502 {
2503 BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
2504 u4Byte timeout = 2000, timecount = 0;
2505 u4Byte StartTime;
2506 s4Byte ProgressingTime;
2507 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
2508
2509
2510 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2511 PADAPTER pAdapter = pDM_Odm->Adapter;
2512 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2513
2514 #if (MP_DRIVER == 1)
2515 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2516 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
2517 #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
2518 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2519 #endif
2520 #endif//(MP_DRIVER == 1)
2521 #endif
2522
2523 #if MP_DRIVER == 1
2524 if (pDM_Odm->mp_mode == TRUE)
2525 {
2526 bStartContTx = pMptCtx->bStartContTx;
2527 bSingleTone = pMptCtx->bSingleTone;
2528 bCarrierSuppression = pMptCtx->bCarrierSuppression;
2529 }
2530 #endif
2531
2532
2533 #if DISABLE_BB_RF
2534 return;
2535 #endif
2536
2537 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2538 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
2539 {
2540 return;
2541 }
2542 #endif
2543 // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
2544 if(bSingleTone || bCarrierSuppression)
2545 return;
2546
2547 StartTime = ODM_GetCurrentTime( pDM_Odm);
2548 while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)
2549 {
2550 ODM_delay_ms(50);
2551 timecount += 50;
2552 }
2553
2554 pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;
2555
2556 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount));
2557 phy_LCCalibrate_8188E(pDM_Odm, FALSE);
2558
2559 pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;
2560
2561 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));
2562 ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);
2563 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime));
2564 }
2565
2566 #if 0
2567 VOID
2568 PHY_APCalibrate_8188E(
2569 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2570 IN PDM_ODM_T pDM_Odm,
2571 #else
2572 IN PADAPTER pAdapter,
2573 #endif
2574 IN s1Byte delta
2575 )
2576 {
2577 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2578 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2579 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2580 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
2581 #endif
2582 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2583 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
2584 #endif
2585 #endif
2586 #if DISABLE_BB_RF
2587 return;
2588 #endif
2589
2590 #if 0
2591 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2592 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
2593 {
2594 return;
2595 }
2596 #endif
2597
2598 #if FOR_BRAZIL_PRETEST != 1
2599 if(pDM_Odm->RFCalibrateInfo.bAPKdone)
2600 #endif
2601 return;
2602
2603 {
2604 // For 88C 1T1R
2605 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2606 phy_APCalibrate_8188E(pAdapter, delta, FALSE);
2607 #else
2608 phy_APCalibrate_8188E(pDM_Odm, delta, FALSE);
2609 #endif
2610 }
2611 #endif
2612 }
2613 #endif
2614
phy_SetRFPathSwitch_8188E(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bMain,IN BOOLEAN is2T)2615 VOID phy_SetRFPathSwitch_8188E(
2616 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2617 IN PDM_ODM_T pDM_Odm,
2618 #else
2619 IN PADAPTER pAdapter,
2620 #endif
2621 IN BOOLEAN bMain,
2622 IN BOOLEAN is2T
2623 )
2624 {
2625 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2626 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2627 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2628 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
2629 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2630 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
2631 #endif
2632
2633 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2634 if(!pAdapter->bHWInitReady)
2635 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2636 if (!rtw_is_hw_init_completed(pAdapter))
2637 #endif
2638 {
2639 u1Byte u1bTmp;
2640 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
2641 ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
2642 //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);
2643 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
2644 }
2645
2646 #endif
2647
2648 if(is2T) //92C
2649 {
2650 if(bMain)
2651 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
2652 else
2653 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
2654 }
2655 else //88C
2656 {
2657
2658 // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0),
2659 // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW)
2660 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0);
2661 ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table
2662
2663 if(bMain)
2664 {
2665 //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna)
2666 //4 [ Tx ]
2667 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna)
2668
2669 //4 [ Rx ]
2670 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna
2671 if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
2672 ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna
2673
2674 }
2675 else
2676 {
2677 //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna)
2678 //4 [ Tx ]
2679 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna)
2680
2681 //4 [ Rx ]
2682 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna
2683 if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
2684 ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna
2685 }
2686
2687 }
2688 }
PHY_SetRFPathSwitch_8188E(IN PDM_ODM_T pDM_Odm,IN BOOLEAN bMain)2689 VOID PHY_SetRFPathSwitch_8188E(
2690 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
2691 IN PDM_ODM_T pDM_Odm,
2692 #else
2693 IN PADAPTER pAdapter,
2694 #endif
2695 IN BOOLEAN bMain
2696 )
2697 {
2698 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2699 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2700 #endif
2701
2702 #if DISABLE_BB_RF
2703 return;
2704 #endif
2705
2706 {
2707 // For 88C 1T1R
2708 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2709 phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE);
2710 #else
2711 phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE);
2712 #endif
2713 }
2714 }
2715
2716 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2717 //digital predistortion
2718 VOID
phy_DigitalPredistortion(IN PADAPTER pAdapter,IN BOOLEAN is2T)2719 phy_DigitalPredistortion(
2720 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2721 IN PADAPTER pAdapter,
2722 #else
2723 IN PDM_ODM_T pDM_Odm,
2724 #endif
2725 IN BOOLEAN is2T
2726 )
2727 {
2728 #if (RT_PLATFORM == PLATFORM_WINDOWS)
2729 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2730 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2731 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2732 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
2733 #endif
2734 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2735 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
2736 #endif
2737 #endif
2738
2739 u4Byte tmpReg, tmpReg2, index, i;
2740 u1Byte path, pathbound = PATH_NUM;
2741 u4Byte AFE_backup[IQK_ADDA_REG_NUM];
2742 u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
2743 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
2744 rRx_Wait_CCA, rTx_CCK_RFON,
2745 rTx_CCK_BBON, rTx_OFDM_RFON,
2746 rTx_OFDM_BBON, rTx_To_Rx,
2747 rTx_To_Tx, rRx_CCK,
2748 rRx_OFDM, rRx_Wait_RIFS,
2749 rRx_TO_Rx, rStandby,
2750 rSleep, rPMPD_ANAEN };
2751
2752 u4Byte BB_backup[DP_BB_REG_NUM];
2753 u4Byte BB_REG[DP_BB_REG_NUM] = {
2754 rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
2755 rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
2756 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
2757 rFPGA0_XB_RFInterfaceOE};
2758 u4Byte BB_settings[DP_BB_REG_NUM] = {
2759 0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
2760 0x0, 0x0, 0x0};
2761
2762 u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
2763 u4Byte RF_REG[DP_RF_REG_NUM] = {
2764 RF_TXBIAS_A};
2765
2766 u4Byte MAC_backup[IQK_MAC_REG_NUM];
2767 u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
2768 REG_TXPAUSE, REG_BCN_CTRL,
2769 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
2770
2771 u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
2772 {0x1e1e1e1e, 0x03901e1e},
2773 {0x18181818, 0x03901818},
2774 {0x0e0e0e0e, 0x03900e0e}
2775 };
2776
2777 u4Byte AFE_on_off[PATH_NUM] = {
2778 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
2779
2780 u1Byte RetryCount = 0;
2781
2782
2783 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n"));
2784
2785 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R")));
2786
2787 //save BB default value
2788 for(index=0; index<DP_BB_REG_NUM; index++)
2789 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
2790
2791 //save MAC default value
2792 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2793 _PHY_SaveMACRegisters(pAdapter, BB_REG, MAC_backup);
2794 #else
2795 _PHY_SaveMACRegisters(pDM_Odm, BB_REG, MAC_backup);
2796 #endif
2797
2798 //save RF default value
2799 for(path=0; path<DP_PATH_NUM; path++)
2800 {
2801 for(index=0; index<DP_RF_REG_NUM; index++)
2802 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2803 RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
2804 #else
2805 RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
2806 #endif
2807 }
2808
2809 //save AFE default value
2810 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2811 _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2812 #else
2813 _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
2814 #endif
2815
2816 //Path A/B AFE all on
2817 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
2818 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);
2819
2820 //BB register setting
2821 for(index = 0; index < DP_BB_REG_NUM; index++)
2822 {
2823 if(index < 4)
2824 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);
2825 else if (index == 4)
2826 ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
2827 else
2828 ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);
2829 }
2830
2831 //MAC register setting
2832 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
2833 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
2834 #else
2835 _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
2836 #endif
2837
2838 //PAGE-E IQC setting
2839 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2840 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
2841 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
2842 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
2843
2844 //path_A DPK
2845 //Path B to standby mode
2846 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
2847
2848 // PA gain = 11 & PAD1 => tx_agc 1f ~11
2849 // PA gain = 11 & PAD2 => tx_agc 10~0e
2850 // PA gain = 01 => tx_agc 0b~0d
2851 // PA gain = 00 => tx_agc 0a~00
2852 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
2853 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
2854 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2855
2856 //do inner loopback DPK 3 times
2857 for(i = 0; i < 3; i++)
2858 {
2859 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
2860 for(index = 0; index < 3; index++)
2861 ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);
2862 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);
2863 for(index = 0; index < 4; index++)
2864 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);
2865
2866 // PAGE_B for Path-A inner loopback DPK setting
2867 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);
2868 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
2869 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
2870 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
2871
2872 //----send one shot signal----//
2873 // Path A
2874 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);
2875 ODM_delay_ms(1);
2876 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);
2877 ODM_delay_ms(50);
2878 }
2879
2880 //PA gain = 11 => tx_agc = 1a
2881 for(index = 0; index < 3; index++)
2882 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);
2883 ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);
2884 for(index = 0; index < 4; index++)
2885 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);
2886
2887 //====================================
2888 // PAGE_B for Path-A DPK setting
2889 //====================================
2890 // open inner loopback @ b00[19]:10 od 0xb00 0x01097018
2891 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);
2892 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
2893 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
2894 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
2895
2896 //rf_lpbk_setup
2897 //1.rf 00:5205a, rf 0d:0e52c
2898 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);
2899 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);
2900 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );
2901
2902 //----send one shot signal----//
2903 // Path A
2904 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
2905 ODM_delay_ms(1);
2906 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
2907 ODM_delay_ms(50);
2908
2909 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)
2910 {
2911 //----read back measurement results----//
2912 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);
2913 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);
2914 ODM_delay_ms(10);
2915 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);
2916 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);
2917 ODM_delay_ms(10);
2918
2919 tmpReg = (tmpReg & bMaskHWord) >> 16;
2920 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
2921 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )
2922 {
2923 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
2924
2925 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);
2926 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2927 ODM_delay_ms(1);
2928 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
2929 ODM_delay_ms(1);
2930 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
2931 ODM_delay_ms(50);
2932 RetryCount++;
2933 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));
2934 }
2935 else
2936 {
2937 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
2938 pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;
2939 break;
2940 }
2941 }
2942 RetryCount = 0;
2943
2944 //DPP path A
2945 if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)
2946 {
2947 // DP settings
2948 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);
2949 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);
2950 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
2951 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
2952 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
2953
2954 for(i=rPdp_AntA; i<=0xb3c; i+=4)
2955 {
2956 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
2957 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
2958 }
2959
2960 //pwsf
2961 ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);
2962 ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);
2963 ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);
2964
2965 for(i=0xb4c; i<=0xb5c; i+=4)
2966 {
2967 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
2968 }
2969
2970 //TX_AGC boundary
2971 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
2972 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2973 }
2974 else
2975 {
2976 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);
2977 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);
2978 }
2979
2980 //DPK path B
2981 if(is2T)
2982 {
2983 //Path A to standby mode
2984 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
2985
2986 // LUTs => tx_agc
2987 // PA gain = 11 & PAD1, => tx_agc 1f ~11
2988 // PA gain = 11 & PAD2, => tx_agc 10 ~0e
2989 // PA gain = 01 => tx_agc 0b ~0d
2990 // PA gain = 00 => tx_agc 0a ~00
2991 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
2992 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
2993 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
2994
2995 //do inner loopback DPK 3 times
2996 for(i = 0; i < 3; i++)
2997 {
2998 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
2999 for(index = 0; index < 4; index++)
3000 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);
3001 for(index = 0; index < 2; index++)
3002 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);
3003 for(index = 0; index < 2; index++)
3004 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);
3005
3006 // PAGE_B for Path-A inner loopback DPK setting
3007 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);
3008 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
3009 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
3010 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
3011
3012 //----send one shot signal----//
3013 // Path B
3014 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);
3015 ODM_delay_ms(1);
3016 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);
3017 ODM_delay_ms(50);
3018 }
3019
3020 // PA gain = 11 => tx_agc = 1a
3021 for(index = 0; index < 4; index++)
3022 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);
3023 for(index = 0; index < 2; index++)
3024 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);
3025 for(index = 0; index < 2; index++)
3026 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);
3027
3028 // PAGE_B for Path-B DPK setting
3029 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
3030 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
3031 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
3032 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
3033
3034 // RF lpbk switches on
3035 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);
3036 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);
3037
3038 //Path-B RF lpbk
3039 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);
3040 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);
3041 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a);
3042
3043 //----send one shot signal----//
3044 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
3045 ODM_delay_ms(1);
3046 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
3047 ODM_delay_ms(50);
3048
3049 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)
3050 {
3051 //----read back measurement results----//
3052 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);
3053 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);
3054 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);
3055 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);
3056
3057 tmpReg = (tmpReg & bMaskHWord) >> 16;
3058 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
3059
3060 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)
3061 {
3062 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
3063
3064 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000);
3065 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3066 ODM_delay_ms(1);
3067 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
3068 ODM_delay_ms(1);
3069 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
3070 ODM_delay_ms(50);
3071 RetryCount++;
3072 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));
3073 }
3074 else
3075 {
3076 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
3077 pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;
3078 break;
3079 }
3080 }
3081
3082 //DPP path B
3083 if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)
3084 {
3085 // DP setting
3086 // LUT by SRAM
3087 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);
3088 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);
3089 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
3090 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
3091
3092 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000);
3093 for(i=0xb60; i<=0xb9c; i+=4)
3094 {
3095 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
3096 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
3097 }
3098
3099 // PWSF
3100 ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);
3101 ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);
3102 ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);
3103
3104 for(i=0xbac; i<=0xbbc; i+=4)
3105 {
3106 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
3107 }
3108
3109 // tx_agc boundary
3110 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
3111 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
3112
3113 }
3114 else
3115 {
3116 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);
3117 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);
3118 }
3119 }
3120
3121 //reload BB default value
3122 for(index=0; index<DP_BB_REG_NUM; index++)
3123 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
3124
3125 //reload RF default value
3126 for(path = 0; path<DP_PATH_NUM; path++)
3127 {
3128 for( i = 0 ; i < DP_RF_REG_NUM ; i++){
3129 ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);
3130 }
3131 }
3132 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode
3133 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off
3134
3135 //reload AFE default value
3136 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3137 _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
3138
3139 //reload MAC default value
3140 _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
3141 #else
3142 _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
3143
3144 //reload MAC default value
3145 _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
3146 #endif
3147
3148 pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;
3149 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n"));
3150 #endif
3151 }
3152
3153 VOID
PHY_DigitalPredistortion_8188E(IN PADAPTER pAdapter)3154 PHY_DigitalPredistortion_8188E(
3155 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3156 IN PADAPTER pAdapter
3157 #else
3158 IN PDM_ODM_T pDM_Odm
3159 #endif
3160 )
3161 {
3162 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3163 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3164 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3165 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3166 #endif
3167 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3168 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3169 #endif
3170 #endif
3171 #if DISABLE_BB_RF
3172 return;
3173 #endif
3174
3175 return;
3176
3177 if(pDM_Odm->RFCalibrateInfo.bDPdone)
3178 return;
3179 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3180
3181 if(pDM_Odm->RFType == ODM_2T2R){
3182 phy_DigitalPredistortion(pAdapter, TRUE);
3183 }
3184 else
3185 #endif
3186 {
3187 // For 88C 1T1R
3188 phy_DigitalPredistortion(pAdapter, FALSE);
3189 }
3190 }
3191
3192
3193
3194 //return value TRUE => Main; FALSE => Aux
3195
phy_QueryRFPathSwitch_8188E(IN PDM_ODM_T pDM_Odm,IN BOOLEAN is2T)3196 BOOLEAN phy_QueryRFPathSwitch_8188E(
3197 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3198 IN PDM_ODM_T pDM_Odm,
3199 #else
3200 IN PADAPTER pAdapter,
3201 #endif
3202 IN BOOLEAN is2T
3203 )
3204 {
3205 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3206 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3207 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3208 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
3209 #endif
3210 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3211 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
3212 #endif
3213 #endif
3214 if(!pAdapter->bHWInitReady)
3215 {
3216 u1Byte u1bTmp;
3217 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
3218 ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
3219 //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);
3220 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
3221 }
3222
3223 if(is2T) //
3224 {
3225 if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
3226 return TRUE;
3227 else
3228 return FALSE;
3229 }
3230 else
3231 {
3232 if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1))
3233 return TRUE;
3234 else
3235 return FALSE;
3236 }
3237 }
3238
3239
3240
3241 //return value TRUE => Main; FALSE => Aux
PHY_QueryRFPathSwitch_8188E(IN PDM_ODM_T pDM_Odm)3242 BOOLEAN PHY_QueryRFPathSwitch_8188E(
3243 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3244 IN PDM_ODM_T pDM_Odm
3245 #else
3246 IN PADAPTER pAdapter
3247 #endif
3248 )
3249 {
3250 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3251
3252 #if DISABLE_BB_RF
3253 return TRUE;
3254 #endif
3255 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3256 if(IS_2T2R( pHalData->VersionID)){
3257 return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE);
3258 }
3259 else
3260 #endif
3261 {
3262 // For 88C 1T1R
3263 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3264 return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE);
3265 #else
3266 return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE);
3267 #endif
3268 }
3269 }
3270 #endif
3271
3272