1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 *
5 * Max Schwarz <max.schwarz@online.de>
6 * based on the patches by Rockchip Inc.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/i2c.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/spinlock.h>
22 #include <linux/clk.h>
23 #include <linux/wait.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/regmap.h>
26 #include <linux/math64.h>
27 #include <linux/reboot.h>
28 #include <linux/delay.h>
29 #include <linux/soc/rockchip/rockchip_thunderboot_service.h>
30
31
32 /* Register Map */
33 #define REG_CON 0x00 /* control register */
34 #define REG_CLKDIV 0x04 /* clock divisor register */
35 #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
36 #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
37 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
38 #define REG_MRXCNT 0x14 /* number of bytes to be received */
39 #define REG_IEN 0x18 /* interrupt enable */
40 #define REG_IPD 0x1c /* interrupt pending */
41 #define REG_FCNT 0x20 /* finished count */
42 #define REG_CON1 0x228 /* control register1 */
43
44 /* Data buffer offsets */
45 #define TXBUFFER_BASE 0x100
46 #define RXBUFFER_BASE 0x200
47
48 /* REG_CON bits */
49 #define REG_CON_EN BIT(0)
50 enum {
51 REG_CON_MOD_TX = 0, /* transmit data */
52 REG_CON_MOD_REGISTER_TX, /* select register and restart */
53 REG_CON_MOD_RX, /* receive data */
54 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
55 * register addr */
56 };
57 #define REG_CON_MOD(mod) ((mod) << 1)
58 #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
59 #define REG_CON_START BIT(3)
60 #define REG_CON_STOP BIT(4)
61 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
62 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
63
64 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
65
66 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
67 #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
68 #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
69
70 enum {
71 RK_I2C_VERSION0 = 0,
72 RK_I2C_VERSION1,
73 RK_I2C_VERSION5 = 5,
74 };
75
76 #define REG_CON_VERSION GENMASK_ULL(24, 16)
77 #define REG_CON_VERSION_SHIFT 16
78
79 /* REG_MRXADDR bits */
80 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
81
82 /* REG_IEN/REG_IPD bits */
83 #define REG_INT_BTF BIT(0) /* a byte was transmitted */
84 #define REG_INT_BRF BIT(1) /* a byte was received */
85 #define REG_INT_MBTF BIT(2) /* master data transmit finished */
86 #define REG_INT_MBRF BIT(3) /* master data receive finished */
87 #define REG_INT_START BIT(4) /* START condition generated */
88 #define REG_INT_STOP BIT(5) /* STOP condition generated */
89 #define REG_INT_NAKRCV BIT(6) /* NACK received */
90 #define REG_INT_ALL 0xff
91
92 /* Disable i2c all irqs */
93 #define IEN_ALL_DISABLE 0
94
95 #define REG_CON1_AUTO_STOP BIT(0)
96 #define REG_CON1_TRANSFER_AUTO_STOP BIT(1)
97 #define REG_CON1_NACK_AUTO_STOP BIT(2)
98
99 /* Constants */
100 #define WAIT_TIMEOUT 1000 /* ms */
101 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
102
103 /**
104 * struct i2c_spec_values:
105 * @min_hold_start_ns: min hold time (repeated) START condition
106 * @min_low_ns: min LOW period of the SCL clock
107 * @min_high_ns: min HIGH period of the SCL cloc
108 * @min_setup_start_ns: min set-up time for a repeated START conditio
109 * @max_data_hold_ns: max data hold time
110 * @min_data_setup_ns: min data set-up time
111 * @min_setup_stop_ns: min set-up time for STOP condition
112 * @min_hold_buffer_ns: min bus free time between a STOP and
113 * START condition
114 */
115 struct i2c_spec_values {
116 unsigned long min_hold_start_ns;
117 unsigned long min_low_ns;
118 unsigned long min_high_ns;
119 unsigned long min_setup_start_ns;
120 unsigned long max_data_hold_ns;
121 unsigned long min_data_setup_ns;
122 unsigned long min_setup_stop_ns;
123 unsigned long min_hold_buffer_ns;
124 };
125
126 static const struct i2c_spec_values standard_mode_spec = {
127 .min_hold_start_ns = 4000,
128 .min_low_ns = 4700,
129 .min_high_ns = 4000,
130 .min_setup_start_ns = 4700,
131 .max_data_hold_ns = 3450,
132 .min_data_setup_ns = 250,
133 .min_setup_stop_ns = 4000,
134 .min_hold_buffer_ns = 4700,
135 };
136
137 static const struct i2c_spec_values fast_mode_spec = {
138 .min_hold_start_ns = 600,
139 .min_low_ns = 1300,
140 .min_high_ns = 600,
141 .min_setup_start_ns = 600,
142 .max_data_hold_ns = 900,
143 .min_data_setup_ns = 100,
144 .min_setup_stop_ns = 600,
145 .min_hold_buffer_ns = 1300,
146 };
147
148 static const struct i2c_spec_values fast_mode_plus_spec = {
149 .min_hold_start_ns = 260,
150 .min_low_ns = 500,
151 .min_high_ns = 260,
152 .min_setup_start_ns = 260,
153 .max_data_hold_ns = 400,
154 .min_data_setup_ns = 50,
155 .min_setup_stop_ns = 260,
156 .min_hold_buffer_ns = 500,
157 };
158
159 /**
160 * struct rk3x_i2c_calced_timings:
161 * @div_low: Divider output for low
162 * @div_high: Divider output for high
163 * @tuning: Used to adjust setup/hold data time,
164 * setup/hold start time and setup stop time for
165 * v1's calc_timings, the tuning should all be 0
166 * for old hardware anyone using v0's calc_timings.
167 */
168 struct rk3x_i2c_calced_timings {
169 unsigned long div_low;
170 unsigned long div_high;
171 unsigned int tuning;
172 };
173
174 enum rk3x_i2c_state {
175 STATE_IDLE,
176 STATE_READ,
177 STATE_WRITE,
178 STATE_STOP
179 };
180
181 /**
182 * struct rk3x_i2c_soc_data:
183 * @grf_offset: offset inside the grf regmap for setting the i2c type
184 * @calc_timings: Callback function for i2c timing information calculated
185 */
186 struct rk3x_i2c_soc_data {
187 int grf_offset;
188 int (*calc_timings)(unsigned long, struct i2c_timings *,
189 struct rk3x_i2c_calced_timings *);
190 };
191
192 /**
193 * struct rk3x_i2c - private data of the controller
194 * @adap: corresponding I2C adapter
195 * @dev: device for this controller
196 * @soc_data: related soc data struct
197 * @regs: virtual memory area
198 * @clk: function clk for rk3399 or function & Bus clks for others
199 * @pclk: Bus clk for rk3399
200 * @clk_rate_nb: i2c clk rate change notify
201 * @t: I2C known timing information
202 * @lock: spinlock for the i2c bus
203 * @wait: the waitqueue to wait for i2c transfer
204 * @busy: the condition for the event to wait for
205 * @msg: current i2c message
206 * @addr: addr of i2c slave device
207 * @mode: mode of i2c transfer
208 * @is_last_msg: flag determines whether it is the last msg in this transfer
209 * @state: state of i2c transfer
210 * @processed: byte length which has been send or received
211 * @error: error code for i2c transfer
212 * @i2c_restart_nb: make sure the i2c transfer to be finished
213 * @system_restarting: true if system is restarting
214 * @tb_cl: client for rockchip thunder boot service
215 */
216 struct rk3x_i2c {
217 struct i2c_adapter adap;
218 struct device *dev;
219 const struct rk3x_i2c_soc_data *soc_data;
220
221 /* Hardware resources */
222 void __iomem *regs;
223 struct clk *clk;
224 struct clk *pclk;
225 struct notifier_block clk_rate_nb;
226 bool autostop_supported;
227
228 /* Settings */
229 struct i2c_timings t;
230
231 /* Synchronization & notification */
232 spinlock_t lock;
233 wait_queue_head_t wait;
234 bool busy;
235
236 /* Current message */
237 struct i2c_msg *msg;
238 u8 addr;
239 unsigned int mode;
240 bool is_last_msg;
241
242 /* I2C state machine */
243 enum rk3x_i2c_state state;
244 unsigned int processed;
245 int error;
246 unsigned int suspended:1;
247
248 struct notifier_block i2c_restart_nb;
249 bool system_restarting;
250 struct rk_tb_client tb_cl;
251 int irq;
252 };
253
254 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c);
255 static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sended);
256
rk3x_i2c_wake_up(struct rk3x_i2c * i2c)257 static inline void rk3x_i2c_wake_up(struct rk3x_i2c *i2c)
258 {
259 if (!i2c->system_restarting)
260 wake_up(&i2c->wait);
261 }
262
i2c_writel(struct rk3x_i2c * i2c,u32 value,unsigned int offset)263 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
264 unsigned int offset)
265 {
266 writel(value, i2c->regs + offset);
267 }
268
i2c_readl(struct rk3x_i2c * i2c,unsigned int offset)269 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
270 {
271 return readl(i2c->regs + offset);
272 }
273
274 /* Reset all interrupt pending bits */
rk3x_i2c_clean_ipd(struct rk3x_i2c * i2c)275 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
276 {
277 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
278 }
279
rk3x_i2c_disable_irq(struct rk3x_i2c * i2c)280 static inline void rk3x_i2c_disable_irq(struct rk3x_i2c *i2c)
281 {
282 i2c_writel(i2c, IEN_ALL_DISABLE, REG_IEN);
283 }
284
rk3x_i2c_disable(struct rk3x_i2c * i2c)285 static inline void rk3x_i2c_disable(struct rk3x_i2c *i2c)
286 {
287 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
288
289 i2c_writel(i2c, val, REG_CON);
290 }
291
rk3x_i2c_auto_stop(struct rk3x_i2c * i2c)292 static bool rk3x_i2c_auto_stop(struct rk3x_i2c *i2c)
293 {
294 unsigned int len, con1 = 0;
295
296 if (!i2c->autostop_supported)
297 return false;
298
299 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
300 con1 = REG_CON1_NACK_AUTO_STOP | REG_CON1_AUTO_STOP;
301
302 if (!i2c->is_last_msg)
303 goto out;
304
305 len = i2c->msg->len - i2c->processed;
306
307 if (len > 32)
308 goto out;
309
310 i2c->state = STATE_STOP;
311
312 con1 |= REG_CON1_TRANSFER_AUTO_STOP | REG_CON1_AUTO_STOP;
313 i2c_writel(i2c, con1, REG_CON1);
314 if (con1 & REG_CON1_NACK_AUTO_STOP)
315 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
316 else
317 i2c_writel(i2c, REG_INT_STOP | REG_INT_NAKRCV, REG_IEN);
318
319 return true;
320
321 out:
322 i2c_writel(i2c, con1, REG_CON1);
323 return false;
324 }
325
326 /**
327 * Generate a START condition, which triggers a REG_INT_START interrupt.
328 */
rk3x_i2c_start(struct rk3x_i2c * i2c)329 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
330 {
331 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
332 bool auto_stop = rk3x_i2c_auto_stop(i2c);
333 int length = 0;
334
335 /* enable appropriate interrupts */
336 if (i2c->mode == REG_CON_MOD_TX) {
337 if (!auto_stop) {
338 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
339 i2c->state = STATE_WRITE;
340 }
341 length = rk3x_i2c_fill_transmit_buf(i2c, false);
342 } else {
343 /* in any other case, we are going to be reading. */
344 if (!auto_stop) {
345 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
346 i2c->state = STATE_READ;
347 }
348 }
349
350 /* enable adapter with correct mode, send START condition */
351 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
352
353 /* if we want to react to NACK, set ACTACK bit */
354 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
355 val |= REG_CON_ACTACK;
356
357 i2c_writel(i2c, val, REG_CON);
358
359 /* enable transition */
360 if (i2c->mode == REG_CON_MOD_TX)
361 i2c_writel(i2c, length, REG_MTXCNT);
362 else
363 rk3x_i2c_prepare_read(i2c);
364 }
365
366 /**
367 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
368 *
369 * @error: Error code to return in rk3x_i2c_xfer
370 */
rk3x_i2c_stop(struct rk3x_i2c * i2c,int error)371 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
372 {
373 unsigned int ctrl;
374
375 i2c->processed = 0;
376 i2c->msg = NULL;
377 i2c->error = error;
378
379 if (i2c->is_last_msg) {
380 /* Enable stop interrupt */
381 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
382
383 i2c->state = STATE_STOP;
384
385 ctrl = i2c_readl(i2c, REG_CON);
386 ctrl |= REG_CON_STOP;
387 ctrl &= ~REG_CON_START;
388 i2c_writel(i2c, ctrl, REG_CON);
389 } else {
390 /* Signal rk3x_i2c_xfer to start the next message. */
391 i2c->busy = false;
392 i2c->state = STATE_IDLE;
393
394 /*
395 * The HW is actually not capable of REPEATED START. But we can
396 * get the intended effect by resetting its internal state
397 * and issuing an ordinary START.
398 */
399 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
400 i2c_writel(i2c, ctrl, REG_CON);
401
402 /* signal that we are finished with the current msg */
403 rk3x_i2c_wake_up(i2c);
404 }
405 }
406
407 /**
408 * Setup a read according to i2c->msg
409 */
rk3x_i2c_prepare_read(struct rk3x_i2c * i2c)410 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
411 {
412 unsigned int len = i2c->msg->len - i2c->processed;
413 u32 con;
414
415 con = i2c_readl(i2c, REG_CON);
416
417 /*
418 * The hw can read up to 32 bytes at a time. If we need more than one
419 * chunk, send an ACK after the last byte of the current chunk.
420 */
421 if (len > 32) {
422 len = 32;
423 con &= ~REG_CON_LASTACK;
424 } else {
425 con |= REG_CON_LASTACK;
426 }
427
428 /* make sure we are in plain RX mode if we read a second chunk */
429 if (i2c->processed != 0) {
430 con &= ~REG_CON_MOD_MASK;
431 con |= REG_CON_MOD(REG_CON_MOD_RX);
432 if (con & REG_CON_START)
433 con &= ~REG_CON_START;
434 }
435
436 i2c_writel(i2c, con, REG_CON);
437 i2c_writel(i2c, len, REG_MRXCNT);
438 }
439
440 /**
441 * Fill the transmit buffer with data from i2c->msg
442 */
rk3x_i2c_fill_transmit_buf(struct rk3x_i2c * i2c,bool sendend)443 static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sendend)
444 {
445 unsigned int i, j;
446 u32 cnt = 0;
447 u32 val;
448 u8 byte;
449
450 for (i = 0; i < 8; ++i) {
451 val = 0;
452 for (j = 0; j < 4; ++j) {
453 if ((i2c->processed == i2c->msg->len) && (cnt != 0))
454 break;
455
456 if (i2c->processed == 0 && cnt == 0)
457 byte = (i2c->addr & 0x7f) << 1;
458 else
459 byte = i2c->msg->buf[i2c->processed++];
460
461 val |= byte << (j * 8);
462 cnt++;
463 }
464
465 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
466
467 if (i2c->processed == i2c->msg->len)
468 break;
469 }
470
471 if (sendend)
472 i2c_writel(i2c, cnt, REG_MTXCNT);
473
474 return cnt;
475 }
476
477
478 /* IRQ handlers for individual states */
479
rk3x_i2c_handle_write(struct rk3x_i2c * i2c,unsigned int ipd)480 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
481 {
482 if (!(ipd & REG_INT_MBTF)) {
483 rk3x_i2c_stop(i2c, -EIO);
484 dev_warn_ratelimited(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
485 rk3x_i2c_clean_ipd(i2c);
486 return;
487 }
488
489 /* ack interrupt */
490 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
491
492 rk3x_i2c_auto_stop(i2c);
493 /* are we finished? */
494 if (i2c->processed == i2c->msg->len)
495 rk3x_i2c_stop(i2c, i2c->error);
496 else
497 rk3x_i2c_fill_transmit_buf(i2c, true);
498 }
499
rk3x_i2c_read(struct rk3x_i2c * i2c)500 static void rk3x_i2c_read(struct rk3x_i2c *i2c)
501 {
502 unsigned int i;
503 unsigned int len = i2c->msg->len - i2c->processed;
504 u32 val;
505 u8 byte;
506
507 /* Can only handle a maximum of 32 bytes at a time */
508 if (len > 32)
509 len = 32;
510
511 /* read the data from receive buffer */
512 for (i = 0; i < len; ++i) {
513 if (i % 4 == 0)
514 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
515
516 byte = (val >> ((i % 4) * 8)) & 0xff;
517 i2c->msg->buf[i2c->processed++] = byte;
518 }
519 }
520
rk3x_i2c_handle_read(struct rk3x_i2c * i2c,unsigned int ipd)521 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
522 {
523 /* we only care for MBRF here. */
524 if (!(ipd & REG_INT_MBRF))
525 return;
526
527 /* ack interrupt (read also produces a spurious START flag, clear it too) */
528 i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD);
529
530 /* read the data from receive buffer */
531 rk3x_i2c_read(i2c);
532
533 rk3x_i2c_auto_stop(i2c);
534 /* are we finished? */
535 if (i2c->processed == i2c->msg->len)
536 rk3x_i2c_stop(i2c, i2c->error);
537 else
538 rk3x_i2c_prepare_read(i2c);
539 }
540
rk3x_i2c_handle_stop(struct rk3x_i2c * i2c,unsigned int ipd)541 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
542 {
543 unsigned int con;
544
545 if (!(ipd & REG_INT_STOP)) {
546 rk3x_i2c_stop(i2c, -EIO);
547 dev_warn_ratelimited(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
548 rk3x_i2c_clean_ipd(i2c);
549 return;
550 }
551
552 if (i2c->autostop_supported && !i2c->error) {
553 if (i2c->mode != REG_CON_MOD_TX && i2c->msg) {
554 if ((i2c->msg->len - i2c->processed) > 0)
555 rk3x_i2c_read(i2c);
556 }
557
558 i2c->processed = 0;
559 i2c->msg = NULL;
560 }
561
562 /* ack interrupt */
563 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
564
565 /* disable STOP bit */
566 con = i2c_readl(i2c, REG_CON);
567 con &= ~REG_CON_STOP;
568 if (i2c->autostop_supported)
569 con &= ~REG_CON_START;
570 i2c_writel(i2c, con, REG_CON);
571
572 i2c->busy = false;
573 i2c->state = STATE_IDLE;
574
575 /* signal rk3x_i2c_xfer that we are finished */
576 rk3x_i2c_wake_up(i2c);
577 }
578
rk3x_i2c_irq(int irqno,void * dev_id)579 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
580 {
581 struct rk3x_i2c *i2c = dev_id;
582 unsigned int ipd;
583
584 spin_lock(&i2c->lock);
585
586 ipd = i2c_readl(i2c, REG_IPD);
587 if (i2c->state == STATE_IDLE) {
588 dev_warn_ratelimited(i2c->dev,
589 "irq in STATE_IDLE, ipd = 0x%x\n",
590 ipd);
591 rk3x_i2c_clean_ipd(i2c);
592 goto out;
593 }
594
595 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
596
597 /* Clean interrupt bits we don't care about */
598 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
599
600 if (ipd & REG_INT_NAKRCV) {
601 /*
602 * We got a NACK in the last operation. Depending on whether
603 * IGNORE_NAK is set, we have to stop the operation and report
604 * an error.
605 */
606 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
607
608 ipd &= ~REG_INT_NAKRCV;
609
610 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
611 if (i2c->autostop_supported) {
612 i2c->error = -ENXIO;
613 i2c->state = STATE_STOP;
614 } else {
615 rk3x_i2c_stop(i2c, -ENXIO);
616 goto out;
617 }
618 }
619 }
620
621 /* is there anything left to handle? */
622 if ((ipd & REG_INT_ALL) == 0)
623 goto out;
624
625 switch (i2c->state) {
626 case STATE_WRITE:
627 rk3x_i2c_handle_write(i2c, ipd);
628 break;
629 case STATE_READ:
630 rk3x_i2c_handle_read(i2c, ipd);
631 break;
632 case STATE_STOP:
633 rk3x_i2c_handle_stop(i2c, ipd);
634 break;
635 case STATE_IDLE:
636 break;
637 }
638
639 out:
640 spin_unlock(&i2c->lock);
641 return IRQ_HANDLED;
642 }
643
644 /**
645 * Get timing values of I2C specification
646 *
647 * @speed: Desired SCL frequency
648 *
649 * Returns: Matched i2c spec values.
650 */
rk3x_i2c_get_spec(unsigned int speed)651 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
652 {
653 if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
654 return &standard_mode_spec;
655 else if (speed <= I2C_MAX_FAST_MODE_FREQ)
656 return &fast_mode_spec;
657 else
658 return &fast_mode_plus_spec;
659 }
660
661 /**
662 * Calculate divider values for desired SCL frequency
663 *
664 * @clk_rate: I2C input clock rate
665 * @t: Known I2C timing information
666 * @t_calc: Caculated rk3x private timings that would be written into regs
667 *
668 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
669 * a best-effort divider value is returned in divs. If the target rate is
670 * too high, we silently use the highest possible rate.
671 */
rk3x_i2c_v0_calc_timings(unsigned long clk_rate,struct i2c_timings * t,struct rk3x_i2c_calced_timings * t_calc)672 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
673 struct i2c_timings *t,
674 struct rk3x_i2c_calced_timings *t_calc)
675 {
676 unsigned long min_low_ns, min_high_ns;
677 unsigned long max_low_ns, min_total_ns;
678
679 unsigned long clk_rate_khz, scl_rate_khz;
680
681 unsigned long min_low_div, min_high_div;
682 unsigned long max_low_div;
683
684 unsigned long min_div_for_hold, min_total_div;
685 unsigned long extra_div, extra_low_div, ideal_low_div;
686
687 unsigned long data_hold_buffer_ns = 50;
688 const struct i2c_spec_values *spec;
689 int ret = 0;
690
691 /* Only support standard-mode and fast-mode */
692 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ))
693 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
694
695 /* prevent scl_rate_khz from becoming 0 */
696 if (WARN_ON(t->bus_freq_hz < 1000))
697 t->bus_freq_hz = 1000;
698
699 /*
700 * min_low_ns: The minimum number of ns we need to hold low to
701 * meet I2C specification, should include fall time.
702 * min_high_ns: The minimum number of ns we need to hold high to
703 * meet I2C specification, should include rise time.
704 * max_low_ns: The maximum number of ns we can hold low to meet
705 * I2C specification.
706 *
707 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
708 * This is because the i2c host on Rockchip holds the data line
709 * for half the low time.
710 */
711 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
712 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
713
714 /*
715 * Timings for repeated start:
716 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
717 * - controller appears to keep SCL high for 2x programmed clk high.
718 *
719 * We need to account for those rules in picking our "high" time so
720 * we meet tSU;STA and tHD;STA times.
721 */
722 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
723 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
724 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
725 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
726 spec->min_high_ns), 2));
727
728 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
729 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
730 min_total_ns = min_low_ns + min_high_ns;
731
732 /* Adjust to avoid overflow */
733 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
734 scl_rate_khz = t->bus_freq_hz / 1000;
735
736 /*
737 * We need the total div to be >= this number
738 * so we don't clock too fast.
739 */
740 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
741
742 /* These are the min dividers needed for min hold times. */
743 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
744 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
745 min_div_for_hold = (min_low_div + min_high_div);
746
747 /*
748 * This is the maximum divider so we don't go over the maximum.
749 * We don't round up here (we round down) since this is a maximum.
750 */
751 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
752
753 if (min_low_div > max_low_div) {
754 WARN_ONCE(true,
755 "Conflicting, min_low_div %lu, max_low_div %lu\n",
756 min_low_div, max_low_div);
757 max_low_div = min_low_div;
758 }
759
760 if (min_div_for_hold > min_total_div) {
761 /*
762 * Time needed to meet hold requirements is important.
763 * Just use that.
764 */
765 t_calc->div_low = min_low_div;
766 t_calc->div_high = min_high_div;
767 } else {
768 /*
769 * We've got to distribute some time among the low and high
770 * so we don't run too fast.
771 */
772 extra_div = min_total_div - min_div_for_hold;
773
774 /*
775 * We'll try to split things up perfectly evenly,
776 * biasing slightly towards having a higher div
777 * for low (spend more time low).
778 */
779 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
780 scl_rate_khz * 8 * min_total_ns);
781
782 /* Don't allow it to go over the maximum */
783 if (ideal_low_div > max_low_div)
784 ideal_low_div = max_low_div;
785
786 /*
787 * Handle when the ideal low div is going to take up
788 * more than we have.
789 */
790 if (ideal_low_div > min_low_div + extra_div)
791 ideal_low_div = min_low_div + extra_div;
792
793 /* Give low the "ideal" and give high whatever extra is left */
794 extra_low_div = ideal_low_div - min_low_div;
795 t_calc->div_low = ideal_low_div;
796 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
797 }
798
799 /*
800 * Adjust to the fact that the hardware has an implicit "+1".
801 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
802 */
803 t_calc->div_low--;
804 t_calc->div_high--;
805
806 /* Give the tuning value 0, that would not update con register */
807 t_calc->tuning = 0;
808 /* Maximum divider supported by hw is 0xffff */
809 if (t_calc->div_low > 0xffff) {
810 t_calc->div_low = 0xffff;
811 ret = -EINVAL;
812 }
813
814 if (t_calc->div_high > 0xffff) {
815 t_calc->div_high = 0xffff;
816 ret = -EINVAL;
817 }
818
819 return ret;
820 }
821
822 /**
823 * Calculate timing values for desired SCL frequency
824 *
825 * @clk_rate: I2C input clock rate
826 * @t: Known I2C timing information
827 * @t_calc: Caculated rk3x private timings that would be written into regs
828 *
829 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
830 * a best-effort divider value is returned in divs. If the target rate is
831 * too high, we silently use the highest possible rate.
832 * The following formulas are v1's method to calculate timings.
833 *
834 * l = divl + 1;
835 * h = divh + 1;
836 * s = sda_update_config + 1;
837 * u = start_setup_config + 1;
838 * p = stop_setup_config + 1;
839 * T = Tclk_i2c;
840 *
841 * tHigh = 8 * h * T;
842 * tLow = 8 * l * T;
843 *
844 * tHD;sda = (l * s + 1) * T;
845 * tSU;sda = [(8 - s) * l + 1] * T;
846 * tI2C = 8 * (l + h) * T;
847 *
848 * tSU;sta = (8h * u + 1) * T;
849 * tHD;sta = [8h * (u + 1) - 1] * T;
850 * tSU;sto = (8h * p + 1) * T;
851 */
rk3x_i2c_v1_calc_timings(unsigned long clk_rate,struct i2c_timings * t,struct rk3x_i2c_calced_timings * t_calc)852 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
853 struct i2c_timings *t,
854 struct rk3x_i2c_calced_timings *t_calc)
855 {
856 unsigned long min_low_ns, min_high_ns;
857 unsigned long min_setup_start_ns, min_setup_data_ns;
858 unsigned long min_setup_stop_ns, max_hold_data_ns;
859
860 unsigned long clk_rate_khz, scl_rate_khz;
861
862 unsigned long min_low_div, min_high_div;
863
864 unsigned long min_div_for_hold, min_total_div;
865 unsigned long extra_div, extra_low_div;
866 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
867
868 const struct i2c_spec_values *spec;
869 int ret = 0;
870
871 /* Support standard-mode, fast-mode and fast-mode plus */
872 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ))
873 t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
874
875 /* prevent scl_rate_khz from becoming 0 */
876 if (WARN_ON(t->bus_freq_hz < 1000))
877 t->bus_freq_hz = 1000;
878
879 /*
880 * min_low_ns: The minimum number of ns we need to hold low to
881 * meet I2C specification, should include fall time.
882 * min_high_ns: The minimum number of ns we need to hold high to
883 * meet I2C specification, should include rise time.
884 */
885 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
886
887 /* calculate min-divh and min-divl */
888 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
889 scl_rate_khz = t->bus_freq_hz / 1000;
890 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
891
892 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
893 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
894
895 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
896 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
897
898 /*
899 * Final divh and divl must be greater than 0, otherwise the
900 * hardware would not output the i2c clk.
901 */
902 min_high_div = (min_high_div < 1) ? 2 : min_high_div;
903 min_low_div = (min_low_div < 1) ? 2 : min_low_div;
904
905 /* These are the min dividers needed for min hold times. */
906 min_div_for_hold = (min_low_div + min_high_div);
907
908 /*
909 * This is the maximum divider so we don't go over the maximum.
910 * We don't round up here (we round down) since this is a maximum.
911 */
912 if (min_div_for_hold >= min_total_div) {
913 /*
914 * Time needed to meet hold requirements is important.
915 * Just use that.
916 */
917 t_calc->div_low = min_low_div;
918 t_calc->div_high = min_high_div;
919 } else {
920 /*
921 * We've got to distribute some time among the low and high
922 * so we don't run too fast.
923 * We'll try to split things up by the scale of min_low_div and
924 * min_high_div, biasing slightly towards having a higher div
925 * for low (spend more time low).
926 */
927 extra_div = min_total_div - min_div_for_hold;
928 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
929 min_div_for_hold);
930
931 t_calc->div_low = min_low_div + extra_low_div;
932 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
933 }
934
935 /*
936 * calculate sda data hold count by the rules, data_upd_st:3
937 * is a appropriate value to reduce calculated times.
938 */
939 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
940 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg
941 * (t_calc->div_low) + 1)
942 * 1000000, clk_rate_khz);
943 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg)
944 * (t_calc->div_low) + 1)
945 * 1000000, clk_rate_khz);
946 if ((max_hold_data_ns < spec->max_data_hold_ns) &&
947 (min_setup_data_ns > spec->min_data_setup_ns))
948 break;
949 }
950
951 /* calculate setup start config */
952 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
953 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
954 - 1000000, 8 * 1000000 * (t_calc->div_high));
955
956 /* calculate setup stop config */
957 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
958 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
959 - 1000000, 8 * 1000000 * (t_calc->div_high));
960
961 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
962 REG_CON_STA_CFG(--stp_sta_cfg) |
963 REG_CON_STO_CFG(--stp_sto_cfg);
964
965 t_calc->div_low--;
966 t_calc->div_high--;
967
968 /* Maximum divider supported by hw is 0xffff */
969 if (t_calc->div_low > 0xffff) {
970 t_calc->div_low = 0xffff;
971 ret = -EINVAL;
972 }
973
974 if (t_calc->div_high > 0xffff) {
975 t_calc->div_high = 0xffff;
976 ret = -EINVAL;
977 }
978
979 return ret;
980 }
981
rk3x_i2c_adapt_div(struct rk3x_i2c * i2c,unsigned long clk_rate)982 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
983 {
984 struct i2c_timings *t = &i2c->t;
985 struct rk3x_i2c_calced_timings calc;
986 u64 t_low_ns, t_high_ns;
987 unsigned long flags;
988 u32 val;
989 int ret;
990
991 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
992 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
993
994 clk_enable(i2c->pclk);
995
996 spin_lock_irqsave(&i2c->lock, flags);
997 val = i2c_readl(i2c, REG_CON);
998 val &= ~REG_CON_TUNING_MASK;
999 val |= calc.tuning;
1000 i2c_writel(i2c, val, REG_CON);
1001 i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
1002 REG_CLKDIV);
1003 spin_unlock_irqrestore(&i2c->lock, flags);
1004
1005 clk_disable(i2c->pclk);
1006
1007 t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate);
1008 t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000,
1009 clk_rate);
1010 dev_dbg(i2c->dev,
1011 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
1012 clk_rate / 1000,
1013 1000000000 / t->bus_freq_hz,
1014 t_low_ns, t_high_ns);
1015 }
1016
1017 /**
1018 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
1019 * @nb: Pointer to notifier block
1020 * @event: Notification reason
1021 * @data: Pointer to notification data object
1022 *
1023 * The callback checks whether a valid bus frequency can be generated after the
1024 * change. If so, the change is acknowledged, otherwise the change is aborted.
1025 * New dividers are written to the HW in the pre- or post change notification
1026 * depending on the scaling direction.
1027 *
1028 * Code adapted from i2c-cadence.c.
1029 *
1030 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1031 * to acknowledge the change, NOTIFY_DONE if the notification is
1032 * considered irrelevant.
1033 */
rk3x_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)1034 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1035 event, void *data)
1036 {
1037 struct clk_notifier_data *ndata = data;
1038 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
1039 struct rk3x_i2c_calced_timings calc;
1040
1041 switch (event) {
1042 case PRE_RATE_CHANGE:
1043 /*
1044 * Try the calculation (but don't store the result) ahead of
1045 * time to see if we need to block the clock change. Timings
1046 * shouldn't actually take effect until rk3x_i2c_adapt_div().
1047 */
1048 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
1049 &calc) != 0)
1050 return NOTIFY_STOP;
1051
1052 /* scale up */
1053 if (ndata->new_rate > ndata->old_rate)
1054 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
1055
1056 return NOTIFY_OK;
1057 case POST_RATE_CHANGE:
1058 /* scale down */
1059 if (ndata->new_rate < ndata->old_rate)
1060 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
1061 return NOTIFY_OK;
1062 case ABORT_RATE_CHANGE:
1063 /* scale up */
1064 if (ndata->new_rate > ndata->old_rate)
1065 rk3x_i2c_adapt_div(i2c, ndata->old_rate);
1066 return NOTIFY_OK;
1067 default:
1068 return NOTIFY_DONE;
1069 }
1070 }
1071
1072 /**
1073 * Setup I2C registers for an I2C operation specified by msgs, num.
1074 *
1075 * Must be called with i2c->lock held.
1076 *
1077 * @msgs: I2C msgs to process
1078 * @num: Number of msgs
1079 *
1080 * returns: Number of I2C msgs processed or negative in case of error
1081 */
rk3x_i2c_setup(struct rk3x_i2c * i2c,struct i2c_msg * msgs,int num)1082 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
1083 {
1084 u32 addr = (msgs[0].addr & 0x7f) << 1;
1085 int ret = 0;
1086
1087 /*
1088 * The I2C adapter can issue a small (len < 4) write packet before
1089 * reading. This speeds up SMBus-style register reads.
1090 * The MRXADDR/MRXRADDR hold the slave address and the slave register
1091 * address in this case.
1092 */
1093
1094 if (num >= 2 && msgs[0].len < 4 &&
1095 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
1096 u32 reg_addr = 0;
1097 int i;
1098
1099 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
1100 addr >> 1);
1101
1102 /* Fill MRXRADDR with the register address(es) */
1103 for (i = 0; i < msgs[0].len; ++i) {
1104 reg_addr |= msgs[0].buf[i] << (i * 8);
1105 reg_addr |= REG_MRXADDR_VALID(i);
1106 }
1107
1108 /* msgs[0] is handled by hw. */
1109 i2c->msg = &msgs[1];
1110
1111 i2c->mode = REG_CON_MOD_REGISTER_TX;
1112
1113 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1114 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
1115
1116 ret = 2;
1117 } else {
1118 /*
1119 * We'll have to do it the boring way and process the msgs
1120 * one-by-one.
1121 */
1122
1123 if (msgs[0].flags & I2C_M_RD) {
1124 addr |= 1; /* set read bit */
1125
1126 /*
1127 * We have to transmit the slave addr first. Use
1128 * MOD_REGISTER_TX for that purpose.
1129 */
1130 i2c->mode = REG_CON_MOD_REGISTER_TX;
1131 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
1132 REG_MRXADDR);
1133 i2c_writel(i2c, 0, REG_MRXRADDR);
1134 } else {
1135 i2c->mode = REG_CON_MOD_TX;
1136 }
1137
1138 i2c->msg = &msgs[0];
1139
1140 ret = 1;
1141 }
1142
1143 i2c->addr = msgs[0].addr;
1144 i2c->busy = true;
1145 i2c->processed = 0;
1146 i2c->error = 0;
1147
1148 rk3x_i2c_clean_ipd(i2c);
1149 if (i2c->autostop_supported)
1150 i2c_writel(i2c, 0, REG_CON1);
1151
1152 return ret;
1153 }
1154
rk3x_i2c_wait_xfer_poll(struct rk3x_i2c * i2c,unsigned long xfer_time)1155 static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c, unsigned long xfer_time)
1156 {
1157 ktime_t timeout = ktime_add_ms(ktime_get(), xfer_time);
1158
1159 while (READ_ONCE(i2c->busy) &&
1160 ktime_compare(ktime_get(), timeout) < 0) {
1161 udelay(5);
1162 rk3x_i2c_irq(0, i2c);
1163 }
1164
1165 return !i2c->busy;
1166 }
1167
rk3x_i2c_xfer_common(struct i2c_adapter * adap,struct i2c_msg * msgs,int num,bool polling)1168 static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,
1169 struct i2c_msg *msgs, int num, bool polling)
1170 {
1171 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1172 unsigned long timeout, flags;
1173 u32 val;
1174 int ret = 0;
1175 int i;
1176
1177 if (i2c->suspended)
1178 return -EACCES;
1179
1180 spin_lock_irqsave(&i2c->lock, flags);
1181
1182 clk_enable(i2c->clk);
1183 clk_enable(i2c->pclk);
1184
1185 i2c->is_last_msg = false;
1186
1187 /*
1188 * Process msgs. We can handle more than one message at once (see
1189 * rk3x_i2c_setup()).
1190 */
1191 for (i = 0; i < num; i += ret) {
1192 unsigned long xfer_time = 100;
1193 int len;
1194
1195 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1196 if (ret < 0) {
1197 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1198 break;
1199 }
1200
1201 /*
1202 * Transfer time in mSec = Total bits / transfer rate + interval time
1203 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1204 */
1205 if (ret == 2)
1206 len = msgs[i + 1].len;
1207 else
1208 len = msgs[i].len;
1209 xfer_time += len / 64;
1210 xfer_time += DIV_ROUND_CLOSEST(((len * 9) + 2) * MSEC_PER_SEC,
1211 i2c->t.bus_freq_hz);
1212
1213 if (i + ret >= num)
1214 i2c->is_last_msg = true;
1215
1216 rk3x_i2c_start(i2c);
1217
1218 spin_unlock_irqrestore(&i2c->lock, flags);
1219
1220 if (!polling) {
1221 timeout = wait_event_timeout(i2c->wait, !i2c->busy,
1222 msecs_to_jiffies(xfer_time));
1223 } else {
1224 timeout = rk3x_i2c_wait_xfer_poll(i2c, xfer_time);
1225 }
1226
1227 spin_lock_irqsave(&i2c->lock, flags);
1228
1229 if (timeout == 0) {
1230 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
1231 i2c_readl(i2c, REG_IPD), i2c->state);
1232
1233 /* Force a STOP condition without interrupt */
1234 rk3x_i2c_disable_irq(i2c);
1235 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1236 val |= REG_CON_EN | REG_CON_STOP;
1237 i2c_writel(i2c, val, REG_CON);
1238
1239 i2c->state = STATE_IDLE;
1240
1241 ret = -ETIMEDOUT;
1242 break;
1243 }
1244
1245 if (i2c->error) {
1246 ret = i2c->error;
1247 break;
1248 }
1249 }
1250
1251 rk3x_i2c_disable_irq(i2c);
1252 rk3x_i2c_disable(i2c);
1253
1254 clk_disable(i2c->pclk);
1255 clk_disable(i2c->clk);
1256
1257 spin_unlock_irqrestore(&i2c->lock, flags);
1258
1259 return ret < 0 ? ret : num;
1260 }
1261
rk3x_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1262 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1263 struct i2c_msg *msgs, int num)
1264 {
1265 return rk3x_i2c_xfer_common(adap, msgs, num, false);
1266 }
1267
rk3x_i2c_xfer_polling(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1268 static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap,
1269 struct i2c_msg *msgs, int num)
1270 {
1271 return rk3x_i2c_xfer_common(adap, msgs, num, true);
1272 }
1273
rk3x_i2c_restart_notify(struct notifier_block * this,unsigned long mode,void * cmd)1274 static int rk3x_i2c_restart_notify(struct notifier_block *this,
1275 unsigned long mode, void *cmd)
1276 {
1277 struct rk3x_i2c *i2c = container_of(this, struct rk3x_i2c,
1278 i2c_restart_nb);
1279 int tmo = WAIT_TIMEOUT * USEC_PER_MSEC;
1280 u32 val;
1281
1282 if (i2c->state != STATE_IDLE) {
1283 i2c->system_restarting = true;
1284 /* complete the unfinished job */
1285 while (tmo-- && i2c->busy) {
1286 udelay(1);
1287 rk3x_i2c_irq(0, i2c);
1288 }
1289 }
1290
1291 if (tmo <= 0) {
1292 dev_err(i2c->dev, "restart timeout, ipd: 0x%02x, state: %d\n",
1293 i2c_readl(i2c, REG_IPD), i2c->state);
1294
1295 /* Force a STOP condition without interrupt */
1296 i2c_writel(i2c, 0, REG_IEN);
1297 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1298 val |= REG_CON_EN | REG_CON_STOP;
1299 i2c_writel(i2c, val, REG_CON);
1300
1301 udelay(10);
1302 i2c->state = STATE_IDLE;
1303 }
1304
1305 return NOTIFY_DONE;
1306 }
1307
rk3x_i2c_get_version(struct rk3x_i2c * i2c)1308 static unsigned int rk3x_i2c_get_version(struct rk3x_i2c *i2c)
1309 {
1310 unsigned int version;
1311
1312 clk_enable(i2c->pclk);
1313 version = i2c_readl(i2c, REG_CON) & REG_CON_VERSION;
1314 clk_disable(i2c->pclk);
1315 version >>= REG_CON_VERSION_SHIFT;
1316
1317 return version;
1318 }
1319
rk3x_i2c_of_get_bus_id(struct device * dev,struct rk3x_i2c * priv)1320 static int rk3x_i2c_of_get_bus_id(struct device *dev, struct rk3x_i2c *priv)
1321 {
1322 int bus_id = -1;
1323
1324 if (IS_ENABLED(CONFIG_OF) && dev->of_node)
1325 bus_id = of_alias_get_id(dev->of_node, "i2c");
1326
1327 return bus_id;
1328 }
1329
1330 #ifdef CONFIG_ACPI
rk3x_i2c_acpi_get_bus_id(struct device * dev,struct rk3x_i2c * priv)1331 static int rk3x_i2c_acpi_get_bus_id(struct device *dev, struct rk3x_i2c *priv)
1332 {
1333 struct acpi_device *adev;
1334 unsigned long bus_id = -1;
1335 const char *uid;
1336 int ret;
1337
1338 adev = ACPI_COMPANION(dev);
1339 if (!adev)
1340 return -ENXIO;
1341
1342 uid = acpi_device_uid(adev);
1343 if (!uid || !(*uid)) {
1344 dev_err(dev, "Cannot retrieve UID\n");
1345 return -ENODEV;
1346 }
1347
1348 ret = kstrtoul(uid, 0, &bus_id);
1349
1350 return !ret ? bus_id : -ERANGE;
1351 }
1352 #else
rk3x_i2c_acpi_get_bus_id(struct device * dev,struct rk3x_i2c * priv)1353 static int rk3x_i2c_acpi_get_bus_id(struct device *dev, struct rk3x_i2c *priv)
1354 {
1355 return -ENOENT;
1356 }
1357 #endif /* CONFIG_ACPI */
1358
rk3x_i2c_suspend_noirq(struct device * dev)1359 static __maybe_unused int rk3x_i2c_suspend_noirq(struct device *dev)
1360 {
1361 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1362
1363 /*
1364 * Below code is needed only to ensure that there are no
1365 * activities on I2C bus. if at this moment any driver
1366 * is trying to use I2C bus - this may cause i2c timeout.
1367 *
1368 * So forbid access to I2C device using i2c->suspended flag.
1369 */
1370 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1371 i2c->suspended = 1;
1372 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1373
1374 return 0;
1375 }
1376
rk3x_i2c_resume_noirq(struct device * dev)1377 static __maybe_unused int rk3x_i2c_resume_noirq(struct device *dev)
1378 {
1379 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1380
1381 rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1382
1383 /* Allow access to I2C bus */
1384 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1385 i2c->suspended = 0;
1386 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
1387
1388 return 0;
1389 }
1390
rk3x_i2c_func(struct i2c_adapter * adap)1391 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1392 {
1393 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1394 }
1395
1396 static const struct i2c_algorithm rk3x_i2c_algorithm = {
1397 .master_xfer = rk3x_i2c_xfer,
1398 .master_xfer_atomic = rk3x_i2c_xfer_polling,
1399 .functionality = rk3x_i2c_func,
1400 };
1401
1402 static const struct rk3x_i2c_soc_data rv1108_soc_data = {
1403 .grf_offset = 0x408,
1404 .calc_timings = rk3x_i2c_v1_calc_timings,
1405 };
1406
1407 static const struct rk3x_i2c_soc_data rv1126_soc_data = {
1408 .grf_offset = 0x118,
1409 .calc_timings = rk3x_i2c_v1_calc_timings,
1410 };
1411
1412 static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1413 .grf_offset = 0x154,
1414 .calc_timings = rk3x_i2c_v0_calc_timings,
1415 };
1416
1417 static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1418 .grf_offset = 0x0a4,
1419 .calc_timings = rk3x_i2c_v0_calc_timings,
1420 };
1421
1422 static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1423 .grf_offset = -1,
1424 .calc_timings = rk3x_i2c_v0_calc_timings,
1425 };
1426
1427 static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1428 .grf_offset = -1,
1429 .calc_timings = rk3x_i2c_v0_calc_timings,
1430 };
1431
1432 static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1433 .grf_offset = -1,
1434 .calc_timings = rk3x_i2c_v1_calc_timings,
1435 };
1436
1437 static const struct of_device_id rk3x_i2c_match[] = {
1438 {
1439 .compatible = "rockchip,rv1108-i2c",
1440 .data = &rv1108_soc_data
1441 },
1442 {
1443 .compatible = "rockchip,rv1126-i2c",
1444 .data = &rv1126_soc_data
1445 },
1446 {
1447 .compatible = "rockchip,rk3066-i2c",
1448 .data = &rk3066_soc_data
1449 },
1450 {
1451 .compatible = "rockchip,rk3188-i2c",
1452 .data = &rk3188_soc_data
1453 },
1454 {
1455 .compatible = "rockchip,rk3228-i2c",
1456 .data = &rk3228_soc_data
1457 },
1458 {
1459 .compatible = "rockchip,rk3288-i2c",
1460 .data = &rk3288_soc_data
1461 },
1462 {
1463 .compatible = "rockchip,rk3399-i2c",
1464 .data = &rk3399_soc_data
1465 },
1466 {},
1467 };
1468 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1469
rk3x_i2c_tb_cb(void * data)1470 static void rk3x_i2c_tb_cb(void *data)
1471 {
1472 unsigned long clk_rate;
1473 int ret;
1474 struct rk3x_i2c *i2c = (struct rk3x_i2c *)data;
1475
1476 if (i2c->clk) {
1477 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1478 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1479 if (ret != 0) {
1480 dev_err(i2c->dev, "Unable to register clock notifier\n");
1481 clk_unprepare(i2c->pclk);
1482 clk_unprepare(i2c->clk);
1483 return;
1484 }
1485 }
1486
1487 clk_rate = clk_get_rate(i2c->clk);
1488 if (!clk_rate)
1489 device_property_read_u32(i2c->dev, "i2c,clk-rate", (u32 *)&clk_rate);
1490
1491 rk3x_i2c_adapt_div(i2c, clk_rate);
1492 if (rk3x_i2c_get_version(i2c) >= RK_I2C_VERSION5)
1493 i2c->autostop_supported = true;
1494 enable_irq(i2c->irq);
1495 }
1496
rk3x_i2c_probe(struct platform_device * pdev)1497 static int rk3x_i2c_probe(struct platform_device *pdev)
1498 {
1499 struct fwnode_handle *fw = dev_fwnode(&pdev->dev);
1500 struct device_node *np = pdev->dev.of_node;
1501 struct rk3x_i2c *i2c;
1502 int ret = 0;
1503 u32 value;
1504 int irq;
1505 unsigned long clk_rate;
1506
1507 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1508 if (!i2c)
1509 return -ENOMEM;
1510
1511 i2c->soc_data = (struct rk3x_i2c_soc_data *)device_get_match_data(&pdev->dev);
1512
1513 ret = rk3x_i2c_acpi_get_bus_id(&pdev->dev, i2c);
1514 if (ret < 0) {
1515 ret = rk3x_i2c_of_get_bus_id(&pdev->dev, i2c);
1516 if (ret < 0)
1517 return ret;
1518 }
1519
1520 i2c->adap.nr = ret;
1521
1522 /* use common interface to get I2C timing properties */
1523 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1524
1525 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1526 i2c->adap.owner = THIS_MODULE;
1527 i2c->adap.algo = &rk3x_i2c_algorithm;
1528 i2c->adap.retries = 3;
1529 i2c->adap.dev.of_node = pdev->dev.of_node;
1530 i2c->adap.algo_data = i2c;
1531 i2c->adap.dev.parent = &pdev->dev;
1532 i2c->adap.dev.fwnode = fw;
1533
1534 i2c->dev = &pdev->dev;
1535
1536 spin_lock_init(&i2c->lock);
1537 init_waitqueue_head(&i2c->wait);
1538
1539 i2c->i2c_restart_nb.notifier_call = rk3x_i2c_restart_notify;
1540 i2c->i2c_restart_nb.priority = 128;
1541 ret = register_pre_restart_handler(&i2c->i2c_restart_nb);
1542 if (ret) {
1543 dev_err(&pdev->dev, "failed to setup i2c restart handler.\n");
1544 return ret;
1545 }
1546
1547 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
1548 if (IS_ERR(i2c->regs))
1549 return PTR_ERR(i2c->regs);
1550
1551 /*
1552 * Switch to new interface if the SoC also offers the old one.
1553 * The control bit is located in the GRF register space.
1554 */
1555 if (i2c->soc_data->grf_offset >= 0) {
1556 struct regmap *grf;
1557
1558 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1559 if (!IS_ERR(grf)) {
1560 int bus_nr = i2c->adap.nr;
1561
1562 if (i2c->soc_data == &rv1108_soc_data && bus_nr == 2)
1563 /* rv1108 i2c2 set grf offset-0x408, bit-10 */
1564 value = BIT(26) | BIT(10);
1565 else if (i2c->soc_data == &rv1126_soc_data &&
1566 bus_nr == 2)
1567 /* rv1126 i2c2 set pmugrf offset-0x118, bit-4 */
1568 value = BIT(20) | BIT(4);
1569 else
1570 /* rk3xxx 27+i: write mask, 11+i: value */
1571 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1572
1573 ret = regmap_write(grf, i2c->soc_data->grf_offset,
1574 value);
1575 if (ret != 0) {
1576 dev_err(i2c->dev, "Could not write to GRF: %d\n",
1577 ret);
1578 return ret;
1579 }
1580 }
1581 }
1582
1583 /* IRQ setup */
1584 irq = platform_get_irq(pdev, 0);
1585 if (irq < 0)
1586 return irq;
1587 i2c->irq = irq;
1588
1589 if (IS_ENABLED(CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE) &&
1590 device_property_read_bool(&pdev->dev, "rockchip,amp-shared")) {
1591 i2c->tb_cl.data = i2c;
1592 i2c->tb_cl.cb = rk3x_i2c_tb_cb;
1593 irq_set_status_flags(irq, IRQ_NOAUTOEN);
1594 }
1595
1596 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1597 0, dev_name(&pdev->dev), i2c);
1598 if (ret < 0) {
1599 dev_err(&pdev->dev, "cannot request IRQ\n");
1600 return ret;
1601 }
1602
1603 platform_set_drvdata(pdev, i2c);
1604
1605 if (!has_acpi_companion(&pdev->dev)) {
1606 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1607 /* Only one clock to use for bus clock and peripheral clock */
1608 i2c->clk = devm_clk_get(&pdev->dev, NULL);
1609 i2c->pclk = i2c->clk;
1610 } else {
1611 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1612 i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1613 }
1614
1615 if (IS_ERR(i2c->clk))
1616 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
1617 "Can't get bus clk\n");
1618
1619 if (IS_ERR(i2c->pclk))
1620 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
1621 "Can't get periph clk\n");
1622 }
1623
1624 ret = clk_prepare(i2c->clk);
1625 if (ret < 0) {
1626 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1627 return ret;
1628 }
1629 ret = clk_prepare(i2c->pclk);
1630 if (ret < 0) {
1631 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1632 goto err_clk;
1633 }
1634
1635 if (IS_ENABLED(CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE) && i2c->tb_cl.cb) {
1636 rk_tb_client_register_cb(&i2c->tb_cl);
1637 } else {
1638 if (i2c->clk) {
1639 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1640 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1641 if (ret != 0) {
1642 dev_err(&pdev->dev, "Unable to register clock notifier\n");
1643 goto err_pclk;
1644 }
1645 }
1646
1647 clk_rate = clk_get_rate(i2c->clk);
1648 if (!clk_rate)
1649 device_property_read_u32(&pdev->dev, "i2c,clk-rate", (u32 *)&clk_rate);
1650
1651 rk3x_i2c_adapt_div(i2c, clk_rate);
1652
1653 if (rk3x_i2c_get_version(i2c) >= RK_I2C_VERSION5)
1654 i2c->autostop_supported = true;
1655 }
1656
1657 ret = i2c_add_numbered_adapter(&i2c->adap);
1658 if (ret < 0)
1659 goto err_clk_notifier;
1660
1661 return 0;
1662
1663 err_clk_notifier:
1664 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1665 err_pclk:
1666 clk_unprepare(i2c->pclk);
1667 err_clk:
1668 clk_unprepare(i2c->clk);
1669 return ret;
1670 }
1671
rk3x_i2c_remove(struct platform_device * pdev)1672 static int rk3x_i2c_remove(struct platform_device *pdev)
1673 {
1674 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1675
1676 i2c_del_adapter(&i2c->adap);
1677
1678 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1679 unregister_pre_restart_handler(&i2c->i2c_restart_nb);
1680 clk_unprepare(i2c->pclk);
1681 clk_unprepare(i2c->clk);
1682
1683 return 0;
1684 }
1685
1686 static const struct dev_pm_ops rk3x_i2c_pm_ops = {
1687 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rk3x_i2c_suspend_noirq,
1688 rk3x_i2c_resume_noirq)
1689 };
1690
1691 static struct platform_driver rk3x_i2c_driver = {
1692 .probe = rk3x_i2c_probe,
1693 .remove = rk3x_i2c_remove,
1694 .driver = {
1695 .name = "rk3x-i2c",
1696 .of_match_table = rk3x_i2c_match,
1697 .pm = &rk3x_i2c_pm_ops,
1698 },
1699 };
1700
1701 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
rk3x_i2c_driver_init(void)1702 static int __init rk3x_i2c_driver_init(void)
1703 {
1704 return platform_driver_register(&rk3x_i2c_driver);
1705 }
1706 #ifdef CONFIG_INITCALL_ASYNC
1707 subsys_initcall_sync(rk3x_i2c_driver_init);
1708 #else
1709 subsys_initcall(rk3x_i2c_driver_init);
1710 #endif
1711
rk3x_i2c_driver_exit(void)1712 static void __exit rk3x_i2c_driver_exit(void)
1713 {
1714 platform_driver_unregister(&rk3x_i2c_driver);
1715 }
1716 module_exit(rk3x_i2c_driver_exit);
1717 #else
1718 module_platform_driver(rk3x_i2c_driver);
1719 #endif
1720
1721 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1722 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1723 MODULE_LICENSE("GPL v2");
1724