1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9 #include <stdint.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <common/debug.h>
14 #include <drivers/arm/cci.h>
15 #include <lib/mmio.h>
16
17 #define MAKE_CCI_PART_NUMBER(hi, lo) (((hi) << 8) | (lo))
18 #define CCI_PART_LO_MASK U(0xff)
19 #define CCI_PART_HI_MASK U(0xf)
20
21 /* CCI part number codes read from Peripheral ID registers 0 and 1 */
22 #define CCI400_PART_NUM 0x420
23 #define CCI500_PART_NUM 0x422
24 #define CCI550_PART_NUM 0x423
25
26 #define CCI400_SLAVE_PORTS 5
27 #define CCI500_SLAVE_PORTS 7
28 #define CCI550_SLAVE_PORTS 7
29
30 static uintptr_t cci_base;
31 static const int *cci_slave_if_map;
32
33 #if ENABLE_ASSERTIONS
34 static size_t max_master_id;
35 static int cci_num_slave_ports;
36
validate_cci_map(const int * map)37 static bool validate_cci_map(const int *map)
38 {
39 unsigned int valid_cci_map = 0U;
40 int slave_if_id;
41 size_t i;
42
43 /* Validate the map */
44 for (i = 0U; i <= max_master_id; i++) {
45 slave_if_id = map[i];
46
47 if (slave_if_id < 0) {
48 continue;
49 }
50
51 if (slave_if_id >= cci_num_slave_ports) {
52 ERROR("Slave interface ID is invalid\n");
53 return false;
54 }
55
56 if ((valid_cci_map & (1UL << slave_if_id)) != 0U) {
57 ERROR("Multiple masters are assigned same slave interface ID\n");
58 return false;
59 }
60 valid_cci_map |= 1UL << slave_if_id;
61 }
62
63 if (valid_cci_map == 0U) {
64 ERROR("No master is assigned a valid slave interface\n");
65 return false;
66 }
67
68 return true;
69 }
70
71 /*
72 * Read CCI part number from Peripheral ID registers
73 */
read_cci_part_number(uintptr_t base)74 static unsigned int read_cci_part_number(uintptr_t base)
75 {
76 unsigned int part_lo, part_hi;
77
78 part_lo = mmio_read_32(base + PERIPHERAL_ID0) & CCI_PART_LO_MASK;
79 part_hi = mmio_read_32(base + PERIPHERAL_ID1) & CCI_PART_HI_MASK;
80
81 return MAKE_CCI_PART_NUMBER(part_hi, part_lo);
82 }
83
84 /*
85 * Identify a CCI device, and return the number of slaves. Return -1 for an
86 * unidentified device.
87 */
get_slave_ports(unsigned int part_num)88 static int get_slave_ports(unsigned int part_num)
89 {
90 int num_slave_ports = -1;
91
92 switch (part_num) {
93
94 case CCI400_PART_NUM:
95 num_slave_ports = CCI400_SLAVE_PORTS;
96 break;
97 case CCI500_PART_NUM:
98 num_slave_ports = CCI500_SLAVE_PORTS;
99 break;
100 case CCI550_PART_NUM:
101 num_slave_ports = CCI550_SLAVE_PORTS;
102 break;
103 default:
104 /* Do nothing in default case */
105 break;
106 }
107
108 return num_slave_ports;
109 }
110 #endif /* ENABLE_ASSERTIONS */
111
cci_init(uintptr_t base,const int * map,size_t num_cci_masters)112 void __init cci_init(uintptr_t base, const int *map,
113 size_t num_cci_masters)
114 {
115 assert(map != NULL);
116 assert(base != 0U);
117
118 cci_base = base;
119 cci_slave_if_map = map;
120
121 #if ENABLE_ASSERTIONS
122 /*
123 * Master Id's are assigned from zero, So in an array of size n
124 * the max master id is (n - 1).
125 */
126 max_master_id = num_cci_masters - 1U;
127 cci_num_slave_ports = get_slave_ports(read_cci_part_number(base));
128 #endif
129 assert(cci_num_slave_ports >= 0);
130
131 assert(validate_cci_map(map));
132 }
133
cci_enable_snoop_dvm_reqs(size_t master_id)134 void cci_enable_snoop_dvm_reqs(size_t master_id)
135 {
136 int slave_if_id = cci_slave_if_map[master_id];
137
138 assert(master_id <= max_master_id);
139 assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
140 assert(cci_base != 0U);
141
142 /*
143 * Enable Snoops and DVM messages, no need for Read/Modify/Write as
144 * rest of bits are write ignore
145 */
146 mmio_write_32(cci_base +
147 SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
148 DVM_EN_BIT | SNOOP_EN_BIT);
149
150 /*
151 * Wait for the completion of the write to the Snoop Control Register
152 * before testing the change_pending bit
153 */
154 dsbish();
155
156 /* Wait for the dust to settle down */
157 while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) {
158 ;
159 }
160 }
161
cci_disable_snoop_dvm_reqs(size_t master_id)162 void cci_disable_snoop_dvm_reqs(size_t master_id)
163 {
164 int slave_if_id = cci_slave_if_map[master_id];
165
166 assert(master_id <= max_master_id);
167 assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
168 assert(cci_base != 0U);
169
170 /*
171 * Disable Snoops and DVM messages, no need for Read/Modify/Write as
172 * rest of bits are write ignore.
173 */
174 mmio_write_32(cci_base +
175 SLAVE_IFACE_OFFSET((u_register_t)slave_if_id) + SNOOP_CTRL_REG,
176 ~(DVM_EN_BIT | SNOOP_EN_BIT));
177
178 /*
179 * Wait for the completion of the write to the Snoop Control Register
180 * before testing the change_pending bit
181 */
182 dsbish();
183
184 /* Wait for the dust to settle down */
185 while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) {
186 ;
187 }
188 }
189
190