1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSE. Need to define if 262 platform supports RSE. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322If the AP Firmware Updater Configuration image, BL2U is used, the following 323must also be defined: 324 325- **#define : BL2U_BASE** 326 327 Defines the base address in secure memory where BL1 copies the BL2U binary 328 image. Must be aligned on a page-size boundary. 329 330- **#define : BL2U_LIMIT** 331 332 Defines the maximum address in secure memory that the BL2U image can occupy. 333 334- **#define : BL2U_IMAGE_ID** 335 336 BL2U image identifier, used by BL1 to fetch an image descriptor 337 corresponding to BL2U. 338 339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 340must also be defined: 341 342- **#define : SCP_BL2U_IMAGE_ID** 343 344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 345 corresponding to SCP_BL2U. 346 347 .. note:: 348 TF-A does not provide source code for this image. 349 350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 351also be defined: 352 353- **#define : NS_BL1U_BASE** 354 355 Defines the base address in non-secure ROM where NS_BL1U executes. 356 Must be aligned on a page-size boundary. 357 358 .. note:: 359 TF-A does not provide source code for this image. 360 361- **#define : NS_BL1U_IMAGE_ID** 362 363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS_BL1U. 365 366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 367be defined: 368 369- **#define : NS_BL2U_BASE** 370 371 Defines the base address in non-secure memory where NS_BL2U executes. 372 Must be aligned on a page-size boundary. 373 374 .. note:: 375 TF-A does not provide source code for this image. 376 377- **#define : NS_BL2U_IMAGE_ID** 378 379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 380 corresponding to NS_BL2U. 381 382For the the Firmware update capability of TRUSTED BOARD BOOT, the following 383macros may also be defined: 384 385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 386 387 Total number of images that can be loaded simultaneously. If the platform 388 doesn't specify any value, it defaults to 10. 389 390If a SCP_BL2 image is supported by the platform, the following constants must 391also be defined: 392 393- **#define : SCP_BL2_IMAGE_ID** 394 395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 396 from platform storage before being transferred to the SCP. 397 398- **#define : SCP_FW_KEY_CERT_ID** 399 400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 401 certificate (mandatory when Trusted Board Boot is enabled). 402 403- **#define : SCP_FW_CONTENT_CERT_ID** 404 405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 406 content certificate (mandatory when Trusted Board Boot is enabled). 407 408If a BL32 image is supported by the platform, the following constants must 409also be defined: 410 411- **#define : BL32_IMAGE_ID** 412 413 BL32 image identifier, used by BL2 to load BL32. 414 415- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 416 417 BL32 key certificate identifier, used by BL2 to load the BL32 key 418 certificate (mandatory when Trusted Board Boot is enabled). 419 420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 421 422 BL32 content certificate identifier, used by BL2 to load the BL32 content 423 certificate (mandatory when Trusted Board Boot is enabled). 424 425- **#define : BL32_BASE** 426 427 Defines the base address in secure memory where BL2 loads the BL32 binary 428 image. Must be aligned on a page-size boundary. 429 430- **#define : BL32_LIMIT** 431 432 Defines the maximum address that the BL32 image can occupy. 433 434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 435platform, the following constants must also be defined: 436 437- **#define : TSP_SEC_MEM_BASE** 438 439 Defines the base address of the secure memory used by the TSP image on the 440 platform. This must be at the same address or below ``BL32_BASE``. 441 442- **#define : TSP_SEC_MEM_SIZE** 443 444 Defines the size of the secure memory used by the BL32 image on the 445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 447 and ``BL32_LIMIT``. 448 449- **#define : TSP_IRQ_SEC_PHY_TIMER** 450 451 Defines the ID of the secure physical generic timer interrupt used by the 452 TSP's interrupt handling code. 453 454If the platform port uses the translation table library code, the following 455constants must also be defined: 456 457- **#define : PLAT_XLAT_TABLES_DYNAMIC** 458 459 Optional flag that can be set per-image to enable the dynamic allocation of 460 regions even when the MMU is enabled. If not defined, only static 461 functionality will be available, if defined and set to 1 it will also 462 include the dynamic functionality. 463 464- **#define : MAX_XLAT_TABLES** 465 466 Defines the maximum number of translation tables that are allocated by the 467 translation table library code. To minimize the amount of runtime memory 468 used, choose the smallest value needed to map the required virtual addresses 469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 471 as well. 472 473- **#define : MAX_MMAP_REGIONS** 474 475 Defines the maximum number of regions that are allocated by the translation 476 table library code. A region consists of physical base address, virtual base 477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 478 defined in the ``mmap_region_t`` structure. The platform defines the regions 479 that should be mapped. Then, the translation table library will create the 480 corresponding tables and descriptors at runtime. To minimize the amount of 481 runtime memory used, choose the smallest value needed to register the 482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 484 the dynamic regions as well. 485 486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 487 488 Defines the total size of the virtual address space in bytes. For example, 489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 490 491- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 492 493 Defines the total size of the physical address space in bytes. For example, 494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 495 496If the platform port uses the IO storage framework, the following constants 497must also be defined: 498 499- **#define : MAX_IO_DEVICES** 500 501 Defines the maximum number of registered IO devices. Attempting to register 502 more devices than this value using ``io_register_device()`` will fail with 503 -ENOMEM. 504 505- **#define : MAX_IO_HANDLES** 506 507 Defines the maximum number of open IO handles. Attempting to open more IO 508 entities than this value using ``io_open()`` will fail with -ENOMEM. 509 510- **#define : MAX_IO_BLOCK_DEVICES** 511 512 Defines the maximum number of registered IO block devices. Attempting to 513 register more devices this value using ``io_dev_open()`` will fail 514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 515 With this macro, multiple block devices could be supported at the same 516 time. 517 518If the platform needs to allocate data within the per-cpu data framework in 519BL31, it should define the following macro. Currently this is only required if 520the platform decides not to use the coherent memory section by undefining the 521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 522required memory within the the per-cpu data to minimize wastage. 523 524- **#define : PLAT_PCPU_DATA_SIZE** 525 526 Defines the memory (in bytes) to be reserved within the per-cpu data 527 structure for use by the platform layer. 528 529The following constants are optional. They should be defined when the platform 530memory layout implies some image overlaying like in Arm standard platforms. 531 532- **#define : BL31_PROGBITS_LIMIT** 533 534 Defines the maximum address in secure RAM that the BL31's progbits sections 535 can occupy. 536 537- **#define : TSP_PROGBITS_LIMIT** 538 539 Defines the maximum address that the TSP's progbits sections can occupy. 540 541If the platform supports OS-initiated mode, i.e. the build option 542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 544constant must be defined. 545 546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 547 548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 549 550If the platform port uses the PL061 GPIO driver, the following constant may 551optionally be defined: 552 553- **PLAT_PL061_MAX_GPIOS** 554 Maximum number of GPIOs required by the platform. This allows control how 555 much memory is allocated for PL061 GPIO controllers. The default value is 556 557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 558 559If the platform port uses the partition driver, the following constant may 560optionally be defined: 561 562- **PLAT_PARTITION_MAX_ENTRIES** 563 Maximum number of partition entries required by the platform. This allows 564 control how much memory is allocated for partition entries. The default 565 value is 128. 566 For example, define the build flag in ``platform.mk``: 567 PLAT_PARTITION_MAX_ENTRIES := 12 568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 569 570- **PLAT_PARTITION_BLOCK_SIZE** 571 The size of partition block. It could be either 512 bytes or 4096 bytes. 572 The default value is 512. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_BLOCK_SIZE := 4096 575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 576 577If the platform port uses the Arm® Ethos™-N NPU driver, the following 578configuration must be performed: 579 580- The NPU SiP service handler must be hooked up. This consists of both the 581 initial setup (``ethosn_smc_setup``) and the handler itself 582 (``ethosn_smc_handler``) 583 584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 585enabled, the following constants and configuration must also be defined: 586 587- **ETHOSN_NPU_PROT_FW_NSAID** 588 589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 590 access the protected memory that contains the NPU's firmware. 591 592- **ETHOSN_NPU_PROT_DATA_RW_NSAID** 593 594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 595 read/write access to the protected memory that contains inference data. 596 597- **ETHOSN_NPU_PROT_DATA_RO_NSAID** 598 599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 600 read-only access to the protected memory that contains inference data. 601 602- **ETHOSN_NPU_NS_RW_DATA_NSAID** 603 604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 605 read/write access to the non-protected memory. 606 607- **ETHOSN_NPU_NS_RO_DATA_NSAID** 608 609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 610 read-only access to the non-protected memory. 611 612- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** 613 614 Defines the physical address range that the NPU's firmware will be loaded 615 into and executed from. 616 617- Configure the platforms TrustZone Controller (TZC) with appropriate regions 618 of protected memory. At minimum this must include a region for the NPU's 619 firmware code and a region for protected inference data, and these must be 620 accessible using the NSAIDs defined above. 621 622- Include the NPU firmware and certificates in the FIP. 623 624- Provide FCONF entries to configure the image source for the NPU firmware 625 and certificates. 626 627- Add MMU mappings such that: 628 629 - BL2 can write the NPU firmware into the region defined by 630 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` 631 - BL31 (SiP service) can read the NPU firmware from the same region 632 633- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 634 loaded by BL2. 635 636Please see the reference implementation code for the Juno platform as an example. 637 638 639The following constant is optional. It should be defined to override the default 640behaviour of the ``assert()`` function (for example, to save memory). 641 642- **PLAT_LOG_LEVEL_ASSERT** 643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 644 ``assert()`` prints the name of the file, the line number and the asserted 645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 648 defined, it defaults to ``LOG_LEVEL``. 649 650If the platform port uses the DRTM feature, the following constants must be 651defined: 652 653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 654 655 Maximum Event Log size used by the platform. Platform can decide the maximum 656 size of the Event Log buffer, depending upon the highest hash algorithm 657 chosen and the number of components selected to measure during the DRTM 658 execution flow. 659 660- **#define : PLAT_DRTM_MMAP_ENTRIES** 661 662 Number of the MMAP entries used by the DRTM implementation to calculate the 663 size of address map region of the platform. 664 665File : plat_macros.S [mandatory] 666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 667 668Each platform must ensure a file of this name is in the system include path with 669the following macro defined. In the Arm development platforms, this file is 670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 671 672- **Macro : plat_crash_print_regs** 673 674 This macro allows the crash reporting routine to print relevant platform 675 registers in case of an unhandled exception in BL31. This aids in debugging 676 and this macro can be defined to be empty in case register reporting is not 677 desired. 678 679 For instance, GIC or interconnect registers may be helpful for 680 troubleshooting. 681 682Handling Reset 683-------------- 684 685BL1 by default implements the reset vector where execution starts from a cold 686or warm boot. BL31 can be optionally set as a reset vector using the 687``RESET_TO_BL31`` make variable. 688 689For each CPU, the reset vector code is responsible for the following tasks: 690 691#. Distinguishing between a cold boot and a warm boot. 692 693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 694 the CPU is placed in a platform-specific state until the primary CPU 695 performs the necessary steps to remove it from this state. 696 697#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 698 specific address in the BL31 image in the same processor mode as it was 699 when released from reset. 700 701The following functions need to be implemented by the platform port to enable 702reset vector code to perform the above tasks. 703 704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 706 707:: 708 709 Argument : void 710 Return : uintptr_t 711 712This function is called with the MMU and caches disabled 713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 714distinguishing between a warm and cold reset for the current CPU using 715platform-specific means. If it's a warm reset, then it returns the warm 716reset entrypoint point provided to ``plat_setup_psci_ops()`` during 717BL31 initialization. If it's a cold reset then this function must return zero. 718 719This function does not follow the Procedure Call Standard used by the 720Application Binary Interface for the Arm 64-bit architecture. The caller should 721not assume that callee saved registers are preserved across a call to this 722function. 723 724This function fulfills requirement 1 and 3 listed above. 725 726Note that for platforms that support programming the reset address, it is 727expected that a CPU will start executing code directly at the right address, 728both on a cold and warm reset. In this case, there is no need to identify the 729type of reset nor to query the warm reset entrypoint. Therefore, implementing 730this function is not required on such platforms. 731 732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735:: 736 737 Argument : void 738 739This function is called with the MMU and data caches disabled. It is responsible 740for placing the executing secondary CPU in a platform-specific state until the 741primary CPU performs the necessary actions to bring it out of that state and 742allow entry into the OS. This function must not return. 743 744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 745itself off. The primary CPU is responsible for powering up the secondary CPUs 746when normal world software requires them. When booting an EL3 payload instead, 747they stay powered on and are put in a holding pen until their mailbox gets 748populated. 749 750This function fulfills requirement 2 above. 751 752Note that for platforms that can't release secondary CPUs out of reset, only the 753primary CPU will execute the cold boot code. Therefore, implementing this 754function is not required on such platforms. 755 756Generic hold pen helpers 757~~~~~~~~~~~~~~~~~~~~~~~~ 758 759When ``COLD_BOOT_SINGLE_CPU`` is not set, TF-A provides a generic hold pen 760implementation that platforms can use for SMP secondary CPU bring-up. Each 761core gets a cache-line-aligned slot containing an entry field and two magic 762tags, avoiding common pitfalls with cache coherency during the boot handshake 763between primary and secondary CPUs. 764 765The C API consists of ``plat_hold_pen_init()``, to be called during platform 766setup (typically from ``plat_setup_psci_ops()``), ``plat_hold_pen_signal()`` 767to be called from ``pwr_domain_on()``, and the assembly macro 768``plat_hold_pen_wait_and_jump`` to be used by waking cores, usually from 769``plat_secondary_cold_boot_setup()``. Detailed documentation for each is in 770``include/plat/common/plat_hold_pen.h`` and 771``include/plat/common/plat_hold_pen.S``. See 772``plat/arm/board/corstone1000/`` and ``plat/qemu/`` for usage examples. 773 774Platforms using this helper must add ``plat/common/plat_hold_pen.c`` to 775``BL31_SOURCES``. 776 777Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 778~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 779 780:: 781 782 Argument : void 783 Return : unsigned int 784 785This function identifies whether the current CPU is the primary CPU or a 786secondary CPU. A return value of zero indicates that the CPU is not the 787primary CPU, while a non-zero return value indicates that the CPU is the 788primary CPU. 789 790Note that for platforms that can't release secondary CPUs out of reset, only the 791primary CPU will execute the cold boot code. Therefore, there is no need to 792distinguish between primary and secondary CPUs and implementing this function is 793not required. 794 795Function : platform_mem_init() [mandatory] 796~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 797 798:: 799 800 Argument : void 801 Return : void 802 803This function is called before any access to data is made by the firmware, in 804order to carry out any essential memory initialization. 805 806Function: plat_get_rotpk_info() 807~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 808 809:: 810 811 Argument : void *, void **, unsigned int *, unsigned int * 812 Return : int 813 814This function is mandatory when Trusted Board Boot is enabled. It returns a 815pointer to the ROTPK stored in the platform (or a hash of it) and its length. 816The ROTPK must be encoded in DER format according to the following ASN.1 817structure: 818 819:: 820 821 AlgorithmIdentifier ::= SEQUENCE { 822 algorithm OBJECT IDENTIFIER, 823 parameters ANY DEFINED BY algorithm OPTIONAL 824 } 825 826 SubjectPublicKeyInfo ::= SEQUENCE { 827 algorithm AlgorithmIdentifier, 828 subjectPublicKey BIT STRING 829 } 830 831In case the function returns a hash of the key: 832 833:: 834 835 DigestInfo ::= SEQUENCE { 836 digestAlgorithm AlgorithmIdentifier, 837 digest OCTET STRING 838 } 839 840The function returns 0 on success. Any other value is treated as error by the 841Trusted Board Boot. The function also reports extra information related 842to the ROTPK in the flags parameter: 843 844:: 845 846 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 847 hash. 848 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 849 verification while the platform ROTPK is not deployed. 850 When this flag is set, the function does not need to 851 return a platform ROTPK, and the authentication 852 framework uses the ROTPK in the certificate without 853 verifying it against the platform value. This flag 854 must not be used in a deployed production environment. 855 856Function: plat_get_nv_ctr() 857~~~~~~~~~~~~~~~~~~~~~~~~~~~ 858 859:: 860 861 Argument : void *, unsigned int * 862 Return : int 863 864This function is mandatory when Trusted Board Boot is enabled. It returns the 865non-volatile counter value stored in the platform in the second argument. The 866cookie in the first argument may be used to select the counter in case the 867platform provides more than one (for example, on platforms that use the default 868TBBR CoT, the cookie will correspond to the OID values defined in 869TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 870 871The function returns 0 on success. Any other value means the counter value could 872not be retrieved from the platform. 873 874Function: plat_set_nv_ctr() 875~~~~~~~~~~~~~~~~~~~~~~~~~~~ 876 877:: 878 879 Argument : void *, unsigned int 880 Return : int 881 882This function is mandatory when Trusted Board Boot is enabled. It sets a new 883counter value in the platform. The cookie in the first argument may be used to 884select the counter (as explained in plat_get_nv_ctr()). The second argument is 885the updated counter value to be written to the NV counter. 886 887The function returns 0 on success. Any other value means the counter value could 888not be updated. 889 890Function: plat_set_nv_ctr2() 891~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 892 893:: 894 895 Argument : void *, const auth_img_desc_t *, unsigned int 896 Return : int 897 898This function is optional when Trusted Board Boot is enabled. If this 899interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 900first argument passed is a cookie and is typically used to 901differentiate between a Non Trusted NV Counter and a Trusted NV 902Counter. The second argument is a pointer to an authentication image 903descriptor and may be used to decide if the counter is allowed to be 904updated or not. The third argument is the updated counter value to 905be written to the NV counter. 906 907The function returns 0 on success. Any other value means the counter value 908either could not be updated or the authentication image descriptor indicates 909that it is not allowed to be updated. 910 911Dynamic Root of Trust for Measurement support (in BL31) 912------------------------------------------------------- 913 914The functions mentioned in this section are mandatory, when platform enables 915DRTM_SUPPORT build flag. 916 917Function : plat_get_addr_mmap() 918~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 919 920:: 921 922 Argument : void 923 Return : const mmap_region_t * 924 925This function is used to return the address of the platform *address-map* table, 926which describes the regions of normal memory, memory mapped I/O 927and non-volatile memory. 928 929Function : plat_has_non_host_platforms() 930~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 931 932:: 933 934 Argument : void 935 Return : bool 936 937This function returns *true* if the platform has any trusted devices capable of 938DMA, otherwise returns *false*. 939 940Function : plat_has_unmanaged_dma_peripherals() 941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 942 943:: 944 945 Argument : void 946 Return : bool 947 948This function returns *true* if platform uses peripherals whose DMA is not 949managed by an SMMU, otherwise returns *false*. 950 951Note - 952If the platform has peripherals that are not managed by the SMMU, then the 953platform should investigate such peripherals to determine whether they can 954be trusted, and such peripherals should be moved under "Non-host platforms" 955if they can be trusted. 956 957Function : plat_get_total_num_smmus() 958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 959 960:: 961 962 Argument : void 963 Return : unsigned int 964 965This function returns the total number of SMMUs in the platform. 966 967Function : plat_enumerate_smmus() 968~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 969:: 970 971 972 Argument : void 973 Return : const uintptr_t *, size_t 974 975This function returns an array of SMMU addresses and the actual number of SMMUs 976reported by the platform. 977 978Function : plat_drtm_get_dma_prot_features() 979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 980 981:: 982 983 Argument : void 984 Return : const plat_drtm_dma_prot_features_t* 985 986This function returns the address of plat_drtm_dma_prot_features_t structure 987containing the maximum number of protected regions and bitmap with the types 988of DMA protection supported by the platform. 989For more details see section 3.3 Table 6 of `DRTM`_ specification. 990 991Function : plat_drtm_dma_prot_get_max_table_bytes() 992~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 993 994:: 995 996 Argument : void 997 Return : uint64_t 998 999This function returns the maximum size of DMA protected regions table in 1000bytes. 1001 1002Function : plat_drtm_get_tpm_features() 1003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1004 1005:: 1006 1007 Argument : void 1008 Return : const plat_drtm_tpm_features_t* 1009 1010This function returns the address of *plat_drtm_tpm_features_t* structure 1011containing PCR usage schema, TPM-based hash, and firmware hash algorithm 1012supported by the platform. 1013 1014Function : plat_drtm_get_min_size_normal_world_dce() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : uint64_t 1021 1022This function returns the size normal-world DCE of the platform. 1023 1024Function : plat_drtm_get_imp_def_dlme_region_size() 1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1026 1027:: 1028 1029 Argument : void 1030 Return : uint64_t 1031 1032This function returns the size of implementation defined DLME region 1033of the platform. 1034 1035Function : plat_drtm_get_tcb_hash_table_size() 1036~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1037 1038:: 1039 1040 Argument : void 1041 Return : uint64_t 1042 1043This function returns the size of TCB hash table of the platform. 1044 1045Function : plat_drtm_get_acpi_tables_region_size() 1046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1047 1048:: 1049 1050 Argument : void 1051 Return : uint64_t 1052 1053This function returns the size of ACPI tables region of the platform. 1054 1055Function : plat_drtm_get_tcb_hash_features() 1056~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1057 1058:: 1059 1060 Argument : void 1061 Return : uint64_t 1062 1063This function returns the Maximum number of TCB hashes recorded by the 1064platform. 1065For more details see section 3.3 Table 6 of `DRTM`_ specification. 1066 1067Function : plat_drtm_get_dlme_img_auth_features() 1068~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1069 1070:: 1071 1072 Argument : void 1073 Return : uint64_t 1074 1075This function returns the DLME image authentication features. 1076For more details see section 3.3 Table 6 of `DRTM`_ specification. 1077 1078Function : plat_drtm_validate_ns_region() 1079~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1080 1081:: 1082 1083 Argument : uintptr_t, uintptr_t 1084 Return : int 1085 1086This function validates that given region is within the Non-Secure region 1087of DRAM. This function takes a region start address and size an input 1088arguments, and returns 0 on success and -1 on failure. 1089 1090Function : plat_set_drtm_error() 1091~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1092 1093:: 1094 1095 Argument : uint64_t 1096 Return : int 1097 1098This function writes a 64 bit error code received as input into 1099non-volatile storage and returns 0 on success and -1 on failure. 1100 1101Function : plat_get_drtm_error() 1102~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1103 1104:: 1105 1106 Argument : uint64_t* 1107 Return : int 1108 1109This function reads a 64 bit error code from the non-volatile storage 1110into the received address, and returns 0 on success and -1 on failure. 1111 1112Common mandatory function modifications 1113--------------------------------------- 1114 1115The following functions are mandatory functions which need to be implemented 1116by the platform port. 1117 1118Function : plat_my_core_pos() 1119~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1120 1121:: 1122 1123 Argument : void 1124 Return : unsigned int 1125 1126This function returns the index of the calling CPU which is used as a 1127CPU-specific linear index into blocks of memory (for example while allocating 1128per-CPU stacks). This function will be invoked very early in the 1129initialization sequence which mandates that this function should be 1130implemented in assembly and should not rely on the availability of a C 1131runtime environment. This function can clobber x0 - x8 and must preserve 1132x9 - x29. 1133 1134This function plays a crucial role in the power domain topology framework in 1135PSCI and details of this can be found in 1136:ref:`PSCI Power Domain Tree Structure`. 1137 1138Function : plat_core_pos_by_mpidr() 1139~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1140 1141:: 1142 1143 Argument : u_register_t 1144 Return : int 1145 1146This function validates the ``MPIDR`` of a CPU and converts it to an index, 1147which can be used as a CPU-specific linear index into blocks of memory. In 1148case the ``MPIDR`` is invalid, this function returns -1. This function will only 1149be invoked by BL31 after the power domain topology is initialized and can 1150utilize the C runtime environment. For further details about how TF-A 1151represents the power domain topology and how this relates to the linear CPU 1152index, please refer :ref:`PSCI Power Domain Tree Structure`. 1153 1154Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1155~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1156 1157:: 1158 1159 Arguments : void **heap_addr, size_t *heap_size 1160 Return : int 1161 1162This function is invoked during Mbed TLS library initialisation to get a heap, 1163by means of a starting address and a size. This heap will then be used 1164internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1165must be able to provide a heap to it. 1166 1167A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1168which a heap is statically reserved during compile time inside every image 1169(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1170the function simply returns the address and size of this "pre-allocated" heap. 1171For a platform to use this default implementation, only a call to the helper 1172from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1173 1174However, by writting their own implementation, platforms have the potential to 1175optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1176shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1177twice. 1178 1179On success the function should return 0 and a negative error code otherwise. 1180 1181Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1183 1184:: 1185 1186 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1187 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1188 size_t img_id_len 1189 Return : int 1190 1191This function provides a symmetric key (either SSK or BSSK depending on 1192fw_enc_status) which is invoked during runtime decryption of encrypted 1193firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1194implementation for testing purposes which must be overridden by the platform 1195trying to implement a real world firmware encryption use-case. 1196 1197It also allows the platform to pass symmetric key identifier rather than 1198actual symmetric key which is useful in cases where the crypto backend provides 1199secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1200flag must be set in ``flags``. 1201 1202In addition to above a platform may also choose to provide an image specific 1203symmetric key/identifier using img_id. 1204 1205On success the function should return 0 and a negative error code otherwise. 1206 1207Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1208 1209Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1210~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1211 1212:: 1213 1214 Argument : const struct fwu_metadata *metadata 1215 Return : void 1216 1217This function is mandatory when PSA_FWU_SUPPORT is enabled. 1218It provides a means to retrieve image specification (offset in 1219non-volatile storage and length) of active/updated images using the passed 1220FWU metadata, and update I/O policies of active/updated images using retrieved 1221image specification information. 1222Further I/O layer operations such as I/O open, I/O read, etc. on these 1223images rely on this function call. 1224 1225In Arm platforms, this function is used to set an I/O policy of the FIP image, 1226container of all active/updated secure and non-secure images. 1227 1228Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1229~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1230 1231:: 1232 1233 Argument : unsigned int image_id, uintptr_t *dev_handle, 1234 uintptr_t *image_spec 1235 Return : int 1236 1237This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1238responsible for setting up the platform I/O policy of the requested metadata 1239image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1240be used to load this image from the platform's non-volatile storage. 1241 1242FWU metadata can not be always stored as a raw image in non-volatile storage 1243to define its image specification (offset in non-volatile storage and length) 1244statically in I/O policy. 1245For example, the FWU metadata image is stored as a partition inside the GUID 1246partition table image. Its specification is defined in the partition table 1247that needs to be parsed dynamically. 1248This function provides a means to retrieve such dynamic information to set 1249the I/O policy of the FWU metadata image. 1250Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1251image relies on this function call. 1252 1253It returns '0' on success, otherwise a negative error value on error. 1254Alongside, returns device handle and image specification from the I/O policy 1255of the requested FWU metadata image. 1256 1257Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1258~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1259 1260:: 1261 1262 Argument : void 1263 Return : uint32_t 1264 1265This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1266means to retrieve the boot index value from the platform. The boot index is the 1267bank from which the platform has booted the firmware images. 1268 1269By default, the platform will read the metadata structure and try to boot from 1270the active bank. If the platform fails to boot from the active bank due to 1271reasons like an Authentication failure, or on crossing a set number of watchdog 1272resets while booting from the active bank, the platform can then switch to boot 1273from a different bank. This function then returns the bank that the platform 1274should boot its images from. 1275 1276Common optional modifications 1277----------------------------- 1278 1279The following are helper functions implemented by the firmware that perform 1280common platform-specific tasks. A platform may choose to override these 1281definitions. 1282 1283Function : plat_set_my_stack() 1284~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1285 1286:: 1287 1288 Argument : void 1289 Return : void 1290 1291This function sets the current stack pointer to the normal memory stack that 1292has been allocated for the current CPU. For BL images that only require a 1293stack for the primary CPU, the UP version of the function is used. The size 1294of the stack allocated to each CPU is specified by the platform defined 1295constant ``PLATFORM_STACK_SIZE``. 1296 1297Common implementations of this function for the UP and MP BL images are 1298provided in ``plat/common/aarch64/platform_up_stack.S`` and 1299``plat/common/aarch64/platform_mp_stack.S`` 1300 1301Function : plat_get_my_stack() 1302~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1303 1304:: 1305 1306 Argument : void 1307 Return : uintptr_t 1308 1309This function returns the base address of the normal memory stack that 1310has been allocated for the current CPU. For BL images that only require a 1311stack for the primary CPU, the UP version of the function is used. The size 1312of the stack allocated to each CPU is specified by the platform defined 1313constant ``PLATFORM_STACK_SIZE``. 1314 1315Common implementations of this function for the UP and MP BL images are 1316provided in ``plat/common/aarch64/platform_up_stack.S`` and 1317``plat/common/aarch64/platform_mp_stack.S`` 1318 1319Function : plat_report_exception() 1320~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1321 1322:: 1323 1324 Argument : unsigned int 1325 Return : void 1326 1327A platform may need to report various information about its status when an 1328exception is taken, for example the current exception level, the CPU security 1329state (secure/non-secure), the exception type, and so on. This function is 1330called in the following circumstances: 1331 1332- In BL1, whenever an exception is taken. 1333- In BL2, whenever an exception is taken. 1334 1335The default implementation doesn't do anything, to avoid making assumptions 1336about the way the platform displays its status information. 1337 1338For AArch64, this function receives the exception type as its argument. 1339Possible values for exceptions types are listed in the 1340``include/common/bl_common.h`` header file. Note that these constants are not 1341related to any architectural exception code; they are just a TF-A convention. 1342 1343For AArch32, this function receives the exception mode as its argument. 1344Possible values for exception modes are listed in the 1345``include/lib/aarch32/arch.h`` header file. 1346 1347Function : plat_reset_handler() 1348~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1349 1350:: 1351 1352 Argument : void 1353 Return : void 1354 1355A platform may need to do additional initialization after reset. This function 1356allows the platform to do the platform specific initializations. Platform 1357specific errata workarounds could also be implemented here. The API should 1358preserve the values of callee saved registers x19 to x29. 1359 1360The default implementation doesn't do anything. If a platform needs to override 1361the default implementation, refer to the :ref:`Firmware Design` for general 1362guidelines. 1363 1364Function : plat_disable_acp() 1365~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1366 1367:: 1368 1369 Argument : void 1370 Return : void 1371 1372This API allows a platform to disable the Accelerator Coherency Port (if 1373present) during a cluster power down sequence. The default weak implementation 1374doesn't do anything. Since this API is called during the power down sequence, 1375it has restrictions for stack usage and it can use the registers x0 - x17 as 1376scratch registers. It should preserve the value in x18 register as it is used 1377by the caller to store the return address. 1378 1379Function : plat_error_handler() 1380~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1381 1382:: 1383 1384 Argument : int 1385 Return : void 1386 1387This API is called when the generic code encounters an error situation from 1388which it cannot continue. It allows the platform to perform error reporting or 1389recovery actions (for example, reset the system). This function must not return. 1390 1391The parameter indicates the type of error using standard codes from ``errno.h``. 1392Possible errors reported by the generic code are: 1393 1394- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1395 Board Boot is enabled) 1396- ``-ENOENT``: the requested image or certificate could not be found or an IO 1397 error was detected 1398- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1399 error is usually an indication of an incorrect array size 1400 1401The default implementation simply spins. 1402 1403Function : plat_panic_handler() 1404~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1405 1406:: 1407 1408 Argument : void 1409 Return : void 1410 1411This API is called when the generic code encounters an unexpected error 1412situation from which it cannot recover. This function must not return, 1413and must be implemented in assembly because it may be called before the C 1414environment is initialized. 1415 1416.. note:: 1417 The address from where it was called is stored in x30 (Link Register). 1418 The default implementation simply spins. 1419 1420Function : plat_get_bl_image_load_info() 1421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1422 1423:: 1424 1425 Argument : void 1426 Return : bl_load_info_t * 1427 1428This function returns pointer to the list of images that the platform has 1429populated to load. This function is invoked in BL2 to load the 1430BL3xx images. 1431 1432Function : plat_get_next_bl_params() 1433~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1434 1435:: 1436 1437 Argument : void 1438 Return : bl_params_t * 1439 1440This function returns a pointer to the shared memory that the platform has 1441kept aside to pass TF-A related information that next BL image needs. This 1442function is invoked in BL2 to pass this information to the next BL 1443image. 1444 1445Function : plat_get_stack_protector_canary() 1446~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1447 1448:: 1449 1450 Argument : void 1451 Return : u_register_t 1452 1453This function returns a random value that is used to initialize the canary used 1454when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1455value will weaken the protection as the attacker could easily write the right 1456value as part of the attack most of the time. Therefore, it should return a 1457true random number. 1458 1459.. warning:: 1460 For the protection to be effective, the global data need to be placed at 1461 a lower address than the stack bases. Failure to do so would allow an 1462 attacker to overwrite the canary as part of the stack buffer overflow attack. 1463 1464Function : plat_flush_next_bl_params() 1465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1466 1467:: 1468 1469 Argument : void 1470 Return : void 1471 1472This function flushes to main memory all the image params that are passed to 1473next image. This function is invoked in BL2 to flush this information 1474to the next BL image. 1475 1476Function : plat_log_get_prefix() 1477~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1478 1479:: 1480 1481 Argument : unsigned int 1482 Return : const char * 1483 1484This function defines the prefix string corresponding to the `log_level` to be 1485prepended to all the log output from TF-A. The `log_level` (argument) will 1486correspond to one of the standard log levels defined in debug.h. The platform 1487can override the common implementation to define a different prefix string for 1488the log output. The implementation should be robust to future changes that 1489increase the number of log levels. 1490 1491Function : plat_get_soc_version() 1492~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1493 1494:: 1495 1496 Argument : void 1497 Return : int32_t 1498 1499This function returns soc version which mainly consist of below fields 1500 1501:: 1502 1503 soc_version[30:24] = JEP-106 continuation code for the SiP 1504 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1505 soc_version[15:0] = Implementation defined SoC ID 1506 1507Function : plat_get_soc_revision() 1508~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1509 1510:: 1511 1512 Argument : void 1513 Return : int32_t 1514 1515This function returns soc revision in below format 1516 1517:: 1518 1519 soc_revision[0:30] = SOC revision of specific SOC 1520 1521Function : plat_get_soc_name() 1522~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1523 1524:: 1525 1526 Argument : char ** 1527 Return : int32_t 1528 1529The plat_get_soc_name() function allows a platform to expose the SoC name to 1530the firmware. It takes a pointer to a character pointer as an argument, which 1531must be set to point to a static, null-terminated SoC name string. The string 1532must be encoded in UTF-8 and should use only printable ASCII characters for 1533compatibility. It must not exceed 136 bytes, including the null terminator. On 1534success, the function returns SMC_ARCH_CALL_SUCCESS. If the platform does not 1535support SoC name retrieval, it returns SMC_ARCH_CALL_NOT_SUPPORTED. This API 1536allows platforms to support SoC name queries via SMCCC_ARCH_SOC_ID. 1537 1538Function : plat_is_smccc_feature_available() 1539~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1540 1541:: 1542 1543 Argument : u_register_t 1544 Return : int32_t 1545 1546This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1547the SMCCC function specified in the argument; otherwise returns 1548SMC_ARCH_CALL_NOT_SUPPORTED. 1549 1550Function : plat_can_cmo() 1551~~~~~~~~~~~~~~~~~~~~~~~~~ 1552 1553:: 1554 1555 Argument : void 1556 Return : uint64_t 1557 1558When CONDITIONAL_CMO flag is enabled: 1559 1560- This function indicates whether cache management operations should be 1561 performed. It returns 0 if CMOs should be skipped and non-zero 1562 otherwise. 1563- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1564 stack. Otherwise obey AAPCS. 1565 1566Struct: plat_try_images_ops [optional] 1567~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1568 1569This optional structure holds platform hooks for alternative images load. 1570It has to be defined in platform code and registered by calling 1571plat_setup_try_img_ops() function, passing it the address of the 1572plat_try_images_ops struct. 1573 1574Function : plat_setup_try_img_ops [optional] 1575............................................ 1576 1577:: 1578 1579 Argument : const struct plat_try_images_ops * 1580 Return : void 1581 1582This optional function is called to register platform try images ops, given 1583as argument. 1584 1585Function : plat_try_images_ops.next_instance [optional] 1586....................................................... 1587 1588:: 1589 1590 Argument : unsigned int image_id 1591 Return : int 1592 1593This optional function tries to load images from alternative places. 1594In case PSA FWU is not used, it can be any instance or media. If PSA FWU is 1595used, it is mandatory that the backup image is on the same media. 1596This is required for MTD devices like NAND. 1597The argument is the ID of the image for which we are looking for an alternative 1598place. It returns 0 in case of success and a negative errno value otherwise. 1599 1600Function : plat_setup_log_gpt_corrupted [optional] 1601.................................................. 1602 1603:: 1604 1605 Argument : const struct plat_log_gpt_corrupted * 1606 Return : void 1607 1608This optional function is called to register platform log GPT corrupted functions, 1609given as argument. 1610 1611Function : plat_setup_log_gpt_corrupted.plat_set_gpt_corruption [optional] 1612.......................................................................... 1613 1614:: 1615 1616 Argument : uintptr_t gpt_corrupted_info_ptr, uint8_t flags 1617 Return : void 1618 1619This optional function will log error information if the GPT is corrupted, by 1620setting the address passed by gpt_corrupted_info_ptr to flags value, currently 1621bit[0] is used for logging primary GPT corruption, bit[7:1] are reserved. 1622The data type passed by reference is uint8_t. 1623 1624Function : plat_setup_log_gpt_corrupted.plat_log_gpt_corruption [optional] 1625.......................................................................... 1626 1627:: 1628 1629 Argument : uintptr_t log_address, uint8_t gpt_corrupted_info 1630 Return : void 1631 1632This optional function will log if the primary GPT is corrupted, by writing 1633the value of gpt_corrupted_info to the address passed by log_address. 1634 1635Modifications specific to a Boot Loader stage 1636--------------------------------------------- 1637 1638Boot Loader Stage 1 (BL1) 1639------------------------- 1640 1641BL1 implements the reset vector where execution starts from after a cold or 1642warm boot. For each CPU, BL1 is responsible for the following tasks: 1643 1644#. Handling the reset as described in section 2.2 1645 1646#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1647 only this CPU executes the remaining BL1 code, including loading and passing 1648 control to the BL2 stage. 1649 1650#. Identifying and starting the Firmware Update process (if required). 1651 1652#. Loading the BL2 image from non-volatile storage into secure memory at the 1653 address specified by the platform defined constant ``BL2_BASE``. 1654 1655#. Populating a ``meminfo`` structure with the following information in memory, 1656 accessible by BL2 immediately upon entry. 1657 1658 :: 1659 1660 meminfo.total_base = Base address of secure RAM visible to BL2 1661 meminfo.total_size = Size of secure RAM visible to BL2 1662 1663 By default, BL1 places this ``meminfo`` structure at the end of secure 1664 memory visible to BL2. 1665 1666 It is possible for the platform to decide where it wants to place the 1667 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1668 BL2 by overriding the weak default implementation of 1669 ``bl1_plat_handle_post_image_load`` API. 1670 1671The following functions need to be implemented by the platform port to enable 1672BL1 to perform the above tasks. 1673 1674Function : bl1_early_platform_setup() [mandatory] 1675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1676 1677:: 1678 1679 Argument : void 1680 Return : void 1681 1682This function executes with the MMU and data caches disabled. It is only called 1683by the primary CPU. 1684 1685On Arm standard platforms, this function: 1686 1687- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1688 1689- Initializes a UART (PL011 console), which enables access to the ``printf`` 1690 family of functions in BL1. 1691 1692- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1693 the CCI slave interface corresponding to the cluster that includes the 1694 primary CPU. 1695 1696Function : bl1_plat_arch_setup() [mandatory] 1697~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1698 1699:: 1700 1701 Argument : void 1702 Return : void 1703 1704This function performs any platform-specific and architectural setup that the 1705platform requires. Platform-specific setup might include configuration of 1706memory controllers and the interconnect. 1707 1708In Arm standard platforms, this function enables the MMU. 1709 1710This function helps fulfill requirement 2 above. 1711 1712Function : bl1_platform_setup() [mandatory] 1713~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1714 1715:: 1716 1717 Argument : void 1718 Return : void 1719 1720This function executes with the MMU and data caches enabled. It is responsible 1721for performing any remaining platform-specific setup that can occur after the 1722MMU and data cache have been enabled. 1723 1724In Arm standard platforms, this function initializes the storage abstraction 1725layer used to load the next bootloader image. 1726 1727This function helps fulfill requirement 4 above. 1728 1729Function : bl1_plat_sec_mem_layout() [mandatory] 1730~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1731 1732:: 1733 1734 Argument : void 1735 Return : meminfo * 1736 1737This function should only be called on the cold boot path. It executes with the 1738MMU and data caches enabled. The pointer returned by this function must point to 1739a ``meminfo`` structure containing the extents and availability of secure RAM for 1740the BL1 stage. 1741 1742:: 1743 1744 meminfo.total_base = Base address of secure RAM visible to BL1 1745 meminfo.total_size = Size of secure RAM visible to BL1 1746 1747This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1748populates a similar structure to tell BL2 the extents of memory available for 1749its own use. 1750 1751This function helps fulfill requirements 4 and 5 above. 1752 1753Function : bl1_plat_prepare_exit() [optional] 1754~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1755 1756:: 1757 1758 Argument : entry_point_info_t * 1759 Return : void 1760 1761This function is called prior to exiting BL1 in response to the 1762``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1763platform specific clean up or bookkeeping operations before transferring 1764control to the next image. It receives the address of the ``entry_point_info_t`` 1765structure passed from BL2. This function runs with MMU disabled. 1766 1767Function : bl1_plat_set_ep_info() [optional] 1768~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1769 1770:: 1771 1772 Argument : unsigned int image_id, entry_point_info_t *ep_info 1773 Return : void 1774 1775This function allows platforms to override ``ep_info`` for the given ``image_id``. 1776 1777The default implementation just returns. 1778 1779Function : bl1_plat_get_next_image_id() [optional] 1780~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1781 1782:: 1783 1784 Argument : void 1785 Return : unsigned int 1786 1787This and the following function must be overridden to enable the FWU feature. 1788 1789BL1 calls this function after platform setup to identify the next image to be 1790loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1791with the normal boot sequence, which loads and executes BL2. If the platform 1792returns a different image id, BL1 assumes that Firmware Update is required. 1793 1794The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1795platforms override this function to detect if firmware update is required, and 1796if so, return the first image in the firmware update process. 1797 1798Function : bl1_plat_get_image_desc() [optional] 1799~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1800 1801:: 1802 1803 Argument : unsigned int image_id 1804 Return : image_desc_t * 1805 1806BL1 calls this function to get the image descriptor information ``image_desc_t`` 1807for the provided ``image_id`` from the platform. 1808 1809The default implementation always returns a common BL2 image descriptor. Arm 1810standard platforms return an image descriptor corresponding to BL2 or one of 1811the firmware update images defined in the Trusted Board Boot Requirements 1812specification. 1813 1814Function : bl1_plat_handle_pre_image_load() [optional] 1815~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1816 1817:: 1818 1819 Argument : unsigned int image_id 1820 Return : int 1821 1822This function can be used by the platforms to update/use image information 1823corresponding to ``image_id``. This function is invoked in BL1, both in cold 1824boot and FWU code path, before loading the image. 1825 1826Function : bl1_plat_calc_bl2_layout() [optional] 1827~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1828 1829:: 1830 1831 Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout 1832 Return : void 1833 1834This utility function calculates the memory layout of BL2, representing it in a 1835`meminfo_t` structure. The default implementation derives this layout from the 1836positioning of BL1’s RW data at the top of the memory layout. 1837 1838Function : bl1_plat_handle_post_image_load() [optional] 1839~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1840 1841:: 1842 1843 Argument : unsigned int image_id 1844 Return : int 1845 1846This function can be used by the platforms to update/use image information 1847corresponding to ``image_id``. This function is invoked in BL1, both in cold 1848boot and FWU code path, after loading and authenticating the image. 1849 1850The default weak implementation of this function calculates the amount of 1851Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1852structure at the beginning of this free memory and populates it. The address 1853of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1854information to BL2. 1855 1856Function : bl1_plat_fwu_done() [optional] 1857~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1858 1859:: 1860 1861 Argument : unsigned int image_id, uintptr_t image_src, 1862 unsigned int image_size 1863 Return : void 1864 1865BL1 calls this function when the FWU process is complete. It must not return. 1866The platform may override this function to take platform specific action, for 1867example to initiate the normal boot flow. 1868 1869The default implementation spins forever. 1870 1871Function : bl1_plat_mem_check() [mandatory] 1872~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1873 1874:: 1875 1876 Argument : uintptr_t mem_base, unsigned int mem_size, 1877 unsigned int flags 1878 Return : int 1879 1880BL1 calls this function while handling FWU related SMCs, more specifically when 1881copying or authenticating an image. Its responsibility is to ensure that the 1882region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1883that this memory corresponds to either a secure or non-secure memory region as 1884indicated by the security state of the ``flags`` argument. 1885 1886This function can safely assume that the value resulting from the addition of 1887``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1888overflow. 1889 1890This function must return 0 on success, a non-null error code otherwise. 1891 1892The default implementation of this function asserts therefore platforms must 1893override it when using the FWU feature. 1894 1895Function : bl1_plat_is_shared_nv_ctr() [optional] 1896~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1897 1898:: 1899 1900 Argument : void 1901 Return : bool 1902 1903This function inquiry the platform if the non-volatile counter is shared 1904across all secure images (BL2, BL31, BL32, etc.). It is used only in BL1 1905and when `PSA_FWU_SUPPORT` is enabled. 1906 1907Boot Loader Stage 2 (BL2) 1908------------------------- 1909 1910The BL2 stage is executed only by the primary CPU, which is determined in BL1 1911using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1912``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1913``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1914non-volatile storage to secure/non-secure RAM. After all the images are loaded 1915then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1916images to be passed to the next BL image. 1917 1918The following functions must be implemented by the platform port to enable BL2 1919to perform the above tasks. 1920 1921Function : bl2_early_platform_setup2() [mandatory] 1922~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1923 1924:: 1925 1926 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1927 Return : void 1928 1929This function executes with the MMU and data caches disabled. It is only called 1930by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1931are platform specific. 1932 1933On Arm standard platforms when RESET_TO_BL2 is not set, the arguments received 1934are : 1935 1936 arg0 - Points to load address of FW_CONFIG 1937 1938 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1939 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1940 1941On Arm standard platforms, this function also: 1942 1943- Initializes a UART (PL011 console), which enables access to the ``printf`` 1944 family of functions in BL2. 1945 1946- Initializes the storage abstraction layer used to load further bootloader 1947 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1948 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1949 1950Function : bl2_plat_arch_setup() [mandatory] 1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1952 1953:: 1954 1955 Argument : void 1956 Return : void 1957 1958This function executes with the MMU and data caches disabled. It is only called 1959by the primary CPU. 1960 1961The purpose of this function is to perform any architectural initialization 1962that varies across platforms. 1963 1964On Arm standard platforms, this function enables the MMU. 1965 1966Function : bl2_platform_setup() [mandatory] 1967~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1968 1969:: 1970 1971 Argument : void 1972 Return : void 1973 1974This function may execute with the MMU and data caches enabled if the platform 1975port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1976called by the primary CPU. 1977 1978The purpose of this function is to perform any platform initialization 1979specific to BL2. 1980 1981In Arm standard platforms, this function performs security setup, including 1982configuration of the TrustZone controller to allow non-secure masters access 1983to most of DRAM. Part of DRAM is reserved for secure world use. 1984 1985Function : bl2_plat_handle_pre_image_load() [optional] 1986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1987 1988:: 1989 1990 Argument : unsigned int 1991 Return : int 1992 1993This function can be used by the platforms to update/use image information 1994for given ``image_id``. This function is currently invoked in BL2 before 1995loading each image. 1996 1997Function : bl2_plat_handle_post_image_load() [optional] 1998~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1999 2000:: 2001 2002 Argument : unsigned int 2003 Return : int 2004 2005This function can be used by the platforms to update/use image information 2006for given ``image_id``. This function is currently invoked in BL2 after 2007loading each image. 2008 2009Function : bl2_plat_preload_setup [optional] 2010~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2011 2012:: 2013 2014 Argument : void 2015 Return : void 2016 2017This optional function performs any BL2 platform initialization 2018required before image loading, that is not done later in 2019bl2_platform_setup(). 2020 2021Boot Loader Stage 2 (BL2) at EL3 2022-------------------------------- 2023 2024When the platform has a non-TF-A Boot ROM it is desirable to jump 2025directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 2026execute at EL3 instead of executing at EL1. Also on RME enabled systems BL2 runs 2027at EL3. Refer to the :ref:`Firmware Design` document for more information. 2028 2029The existing mandatory functions of BL2 must handle BL2 running at EL3. 2030 2031FWU Boot Loader Stage 2 (BL2U) 2032------------------------------ 2033 2034The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 2035process and is executed only by the primary CPU. BL1 passes control to BL2U at 2036``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 2037 2038#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 2039 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 2040 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 2041 should be copied from. Subsequent handling of the SCP_BL2U image is 2042 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 2043 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 2044 2045#. Any platform specific setup required to perform the FWU process. For 2046 example, Arm standard platforms initialize the TZC controller so that the 2047 normal world can access DDR memory. 2048 2049The following functions must be implemented by the platform port to enable 2050BL2U to perform the tasks mentioned above. 2051 2052Function : bl2u_early_platform_setup() [mandatory] 2053~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2054 2055:: 2056 2057 Argument : meminfo *mem_info, void *plat_info 2058 Return : void 2059 2060This function executes with the MMU and data caches disabled. It is only 2061called by the primary CPU. The arguments to this function is the address 2062of the ``meminfo`` structure and platform specific info provided by BL1. 2063 2064The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2065private storage as the original memory may be subsequently overwritten by BL2U. 2066 2067On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2068to extract SCP_BL2U image information, which is then copied into a private 2069variable. 2070 2071Function : bl2u_plat_arch_setup() [mandatory] 2072~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2073 2074:: 2075 2076 Argument : void 2077 Return : void 2078 2079This function executes with the MMU and data caches disabled. It is only 2080called by the primary CPU. 2081 2082The purpose of this function is to perform any architectural initialization 2083that varies across platforms, for example enabling the MMU (since the memory 2084map differs across platforms). 2085 2086Function : bl2u_platform_setup() [mandatory] 2087~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2088 2089:: 2090 2091 Argument : void 2092 Return : void 2093 2094This function may execute with the MMU and data caches enabled if the platform 2095port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2096called by the primary CPU. 2097 2098The purpose of this function is to perform any platform initialization 2099specific to BL2U. 2100 2101In Arm standard platforms, this function performs security setup, including 2102configuration of the TrustZone controller to allow non-secure masters access 2103to most of DRAM. Part of DRAM is reserved for secure world use. 2104 2105Function : bl2u_plat_handle_scp_bl2u() [optional] 2106~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2107 2108:: 2109 2110 Argument : void 2111 Return : int 2112 2113This function is used to perform any platform-specific actions required to 2114handle the SCP firmware. Typically it transfers the image into SCP memory using 2115a platform-specific protocol and waits until SCP executes it and signals to the 2116Application Processor (AP) for BL2U execution to continue. 2117 2118This function returns 0 on success, a negative error code otherwise. 2119This function is included if SCP_BL2U_BASE is defined. 2120 2121Boot Loader Stage 3-1 (BL31) 2122---------------------------- 2123 2124During cold boot, the BL31 stage is executed only by the primary CPU. This is 2125determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2126control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2127CPUs. BL31 executes at EL3 and is responsible for: 2128 2129#. Re-initializing all architectural and platform state. Although BL1 performs 2130 some of this initialization, BL31 remains resident in EL3 and must ensure 2131 that EL3 architectural and platform state is completely initialized. It 2132 should make no assumptions about the system state when it receives control. 2133 2134#. Passing control to a normal world BL image, pre-loaded at a platform- 2135 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2136 populated by BL2 in memory to do this. 2137 2138#. Providing runtime firmware services. Currently, BL31 only implements a 2139 subset of the Power State Coordination Interface (PSCI) API as a runtime 2140 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2141 implementation. 2142 2143#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2144 specific address by BL2. BL31 exports a set of APIs that allow runtime 2145 services to specify the security state in which the next image should be 2146 executed and run the corresponding image. On ARM platforms, BL31 uses the 2147 ``bl_params`` list populated by BL2 in memory to do this. 2148 2149If BL31 is a reset vector, It also needs to handle the reset as specified in 2150section 2.2 before the tasks described above. 2151 2152The following functions must be implemented by the platform port to enable BL31 2153to perform the above tasks. 2154 2155Function : bl31_early_platform_setup2() [mandatory] 2156~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2157 2158:: 2159 2160 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2161 Return : void 2162 2163This function executes with the MMU and data caches disabled. It is only called 2164by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2165platform specific. 2166 2167In Arm standard platforms, the arguments received are : 2168 2169 arg0 - The pointer to the head of `bl_params_t` list 2170 which is list of executable images following BL31, 2171 2172 arg1 - Points to load address of SOC_FW_CONFIG if present 2173 except in case of Arm FVP and Juno platform. 2174 2175 In case of Arm FVP and Juno platform, points to load address 2176 of FW_CONFIG. 2177 2178 arg2 - Points to load address of HW_CONFIG if present 2179 2180 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2181 used in release builds. 2182 2183The function runs through the `bl_param_t` list and extracts the entry point 2184information for BL32 and BL33. It also performs the following: 2185 2186- Initialize a UART (PL011 console), which enables access to the ``printf`` 2187 family of functions in BL31. 2188 2189- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2190 CCI slave interface corresponding to the cluster that includes the primary 2191 CPU. 2192 2193Function : bl31_plat_arch_setup() [mandatory] 2194~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2195 2196:: 2197 2198 Argument : void 2199 Return : void 2200 2201This function executes with the MMU and data caches disabled. It is only called 2202by the primary CPU. 2203 2204The purpose of this function is to perform any architectural initialization 2205that varies across platforms. 2206 2207On Arm standard platforms, this function enables the MMU. 2208 2209Function : bl31_platform_setup() [mandatory] 2210~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2211 2212:: 2213 2214 Argument : void 2215 Return : void 2216 2217This function may execute with the MMU and data caches enabled if the platform 2218port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2219called by the primary CPU. 2220 2221The purpose of this function is to complete platform initialization so that both 2222BL31 runtime services and normal world software can function correctly. 2223 2224On Arm standard platforms, this function does the following: 2225 2226- Initialize the generic interrupt controller. 2227 2228 Depending on the GIC driver selected by the platform, the appropriate GICv2 2229 or GICv3 initialization will be done, which mainly consists of: 2230 2231 - Enable secure interrupts in the GIC CPU interface. 2232 - Disable the legacy interrupt bypass mechanism. 2233 - Configure the priority mask register to allow interrupts of all priorities 2234 to be signaled to the CPU interface. 2235 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2236 - Target all secure SPIs to CPU0. 2237 - Enable these secure interrupts in the GIC distributor. 2238 - Configure all other interrupts as non-secure. 2239 - Enable signaling of secure interrupts in the GIC distributor. 2240 2241- Enable system-level implementation of the generic timer counter through the 2242 memory mapped interface. 2243 2244- Grant access to the system counter timer module 2245 2246- Initialize the power controller device. 2247 2248 In particular, initialise the locks that prevent concurrent accesses to the 2249 power controller device. 2250 2251Function : bl31_plat_runtime_setup() [optional] 2252~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2253 2254:: 2255 2256 Argument : void 2257 Return : void 2258 2259The purpose of this function is to allow the platform to perform any BL31 runtime 2260setup just prior to BL31 exit during cold boot. The default weak implementation 2261of this function is empty. Any platform that needs to perform additional runtime 2262setup, before BL31 exits, will need to override this function. 2263 2264Function : bl31_plat_get_next_image_ep_info() [mandatory] 2265~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2266 2267:: 2268 2269 Argument : uint32_t 2270 Return : entry_point_info * 2271 2272This function may execute with the MMU and data caches enabled if the platform 2273port does the necessary initializations in ``bl31_plat_arch_setup()``. 2274 2275This function is called by ``bl31_main()`` to retrieve information provided by 2276BL2 for the next image in the security state specified by the argument. BL31 2277uses this information to pass control to that image in the specified security 2278state. This function must return a pointer to the ``entry_point_info`` structure 2279(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2280should return NULL otherwise. 2281 2282Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RMM == 1] 2283~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2284 2285:: 2286 2287 Argument : uintptr_t, size_t *, uintptr_t, size_t, size_t * 2288 Return : int 2289 2290This function returns the Platform attestation token. If the full token does 2291not fit in the buffer, the function will return a hunk of the token and 2292indicate how many bytes were copied and how many are pending. Multiple calls 2293to this function may be needed to retrieve the entire token. 2294 2295The parameters of the function are: 2296 2297 arg0 - A pointer to the buffer where the Platform token should be copied by 2298 this function. If the platform token does not completely fit in the 2299 buffer, the function may return a piece of the token only. 2300 2301 arg1 - Contains the size (in bytes) of the buffer passed in arg0. In 2302 addition, this parameter is used by the function to return the size 2303 of the platform token length hunk copied to the buffer. 2304 2305 arg2 - A pointer to the buffer where the challenge object is stored. 2306 2307 arg3 - The length of the challenge object in bytes. Possible values are 32, 2308 48 and 64. This argument must be zero for subsequent calls to 2309 retrieve the remaining hunks of the token. 2310 2311 arg4 - Returns the remaining length of the token (in bytes) that is yet to 2312 be returned in further calls. 2313 2314The function returns 0 on success, -EINVAL on failure and -EAGAIN if the 2315resource associated with the platform token retrieval is busy. 2316 2317Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RMM == 1] 2318~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2319 2320:: 2321 2322 Argument : uintptr_t, size_t *, unsigned int 2323 Return : int 2324 2325This function returns the delegated realm attestation key which will be used to 2326sign Realm attestation token. The API currently only supports P-384 ECC curve 2327key. 2328 2329The parameters of the function are: 2330 2331 arg0 - A pointer to the buffer where the attestation key should be copied 2332 by this function. The buffer must be big enough to hold the 2333 attestation key. 2334 2335 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2336 function returns the attestation key length in this parameter. 2337 2338 arg2 - The type of the elliptic curve to which the requested attestation key 2339 belongs. 2340 2341The function returns 0 on success, -EINVAL on failure. 2342 2343Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RMM == 1] 2344~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2345 2346:: 2347 2348 Argument : uintptr_t * 2349 Return : size_t 2350 2351This function returns the size of the shared area between EL3 and RMM (or 0 on 2352failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2353in the pointer passed as argument. 2354 2355Function : plat_rmmd_load_manifest() [when ENABLE_RMM == 1] 2356~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2357 2358:: 2359 2360 Arguments : rmm_manifest_t *manifest 2361 Return : int 2362 2363When ENABLE_RMM is enabled, this function populates a boot manifest for the 2364RMM image and stores it in the area specified by manifest. 2365 2366When ENABLE_RMM is disabled, this function is not used. 2367 2368Function : plat_rmmd_mecid_key_update() [when ENABLE_RMM == 1] 2369~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2370 2371:: 2372 2373 Argument : uint16_t, unsigned int 2374 Return : int 2375 2376This function is invoked by BL31's RMMD when there is a request from the RMM 2377monitor to update the tweak for the encryption key associated to a MECID. 2378 2379The first parameter (``uint16_t mecid``) contains the MECID for which the 2380encryption key is to be updated. The second argument specifies the reason 2381for key update. Possible values are: 0 - Realm creation, 1 - Realm destruction. 2382 2383Return value is 0 upon success and -EFAULT otherwise. 2384 2385This function needs to be implemented by a platform if it enables RME. 2386 2387Function : plat_rmmd_reserve_memory() [when ENABLE_RMM == 1] 2388~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2389 2390:: 2391 2392 Arguments : size_t size, unsigned long alignment 2393 Return : uintptr_t 2394 2395Reserve memory to be used by the RMM. This could be memory simply taken from a pool of reserved 2396memory, for instance from a carveout dedicated to RMM. 2397 2398Return value is the physical address of a memory region of at least ``size`` bytes, which needs 2399to be aligned to ``alignment`` bytes. 2400 2401This function needs to be implemented if a platform enables RME and the RMM requires the memory 2402reservation feature. 2403 2404Function : plat_rmmd_el3_token_sign_push_req() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2405~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2406 2407:: 2408 2409 Arguments : const struct el3_token_sign_request *req 2410 Return : int 2411 2412Queue realm attestation token signing request from the RMM in EL3. The interface between 2413the RMM and EL3 is modeled as a queue but the underlying implementation may be different, 2414so long as the semantics of queuing and the error codes are used as defined below. 2415 2416See :ref:`el3_token_sign_request_struct` for definition of the request structure. 2417 2418Optional interface from the RMM-EL3 interface v0.4 onwards. 2419 2420The parameters of the functions are: 2421 arg0: Pointer to the token sign request to be pushed to EL3. 2422 The structure must be located in the RMM-EL3 shared 2423 memory buffer and must be locked before use. 2424 2425Return codes: 2426 - E_RMM_OK On Success. 2427 - E_RMM_INVAL If the arguments are invalid. 2428 - E_RMM_AGAIN Indicates that the request was not queued since the 2429 queue in EL3 is full. This may also be returned for any reason 2430 or situation in the system, that prevents accepting the request 2431 from the RMM. 2432 - E_RMM_UNK If the SMC is not implemented or if interface 2433 version is < 0.4. 2434 2435Function : plat_rmmd_el3_token_sign_pull_resp() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2436~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2437 2438:: 2439 2440 Arguments : struct el3_token_sign_response *resp 2441 Return : int 2442 2443Populate the attestation signing response in the ``resp`` parameter. The interface between 2444the RMM and EL3 is modeled as a queue for responses but the underlying implementation may 2445be different, so long as the semantics of queuing and the error codes are used as defined 2446below. 2447 2448See :ref:`el3_token_sign_response_struct` for definition of the response structure. 2449 2450Optional interface from the RMM-EL3 interface v0.4 onwards. 2451 2452The parameters of the functions are: 2453 resp: Pointer to the token sign response to get from EL3. 2454 The structure must be located in the RMM-EL3 shared 2455 memory buffer and must be locked before use. 2456 2457Return: 2458 - E_RMM_OK On Success. 2459 - E_RMM_INVAL If the arguments are invalid. 2460 - E_RMM_AGAIN Indicates that a response is not ready yet. 2461 - E_RMM_UNK If the SMC is not implemented or if interface 2462 version is < 0.4. 2463 2464Function : plat_rmmd_el3_token_sign_get_rak_pub() [mandatory when RMMD_ENABLE_EL3_TOKEN_SIGN == 1] 2465~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2466 2467:: 2468 2469 Argument : uintptr_t, size_t *, unsigned int 2470 Return : int 2471 2472This function returns the public portion of the realm attestation key which will be used to 2473sign Realm attestation token. Typically, with delegated attestation, the private key is 2474returned, however, there may be platforms where the private key bits are better protected 2475in a platform specific manner such that the private key is not exposed. In such cases, 2476the RMM will only cache the public key and forward any requests such as signing, that 2477uses the private key to EL3. The API currently only supports P-384 ECC curve key. 2478 2479This is an optional interface from the RMM-EL3 interface v0.4 onwards. 2480 2481The parameters of the function are: 2482 2483 arg0 - A pointer to the buffer where the public key should be copied 2484 by this function. The buffer must be big enough to hold the 2485 attestation key. 2486 2487 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2488 function returns the attestation key length in this parameter. 2489 2490 arg2 - The type of the elliptic curve to which the requested attestation key 2491 belongs. 2492 2493The function returns E_RMM_OK on success, RMM_E_INVAL if arguments are invalid and 2494E_RMM_UNK if the SMC is not implemented or if interface version is < 0.4. 2495 2496Function : plat_rmmd_el3_ide_key_program() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2497~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2498 2499:: 2500 2501 Argument : uint64_t, uint64_t, uint64_t, struct rp_ide_key_info_t *, uint64_t, uint64_t 2502 Return : int 2503 2504This function sets the key/IV info for an IDE stream at the Root port. The key is 256 bits 2505and IV is 96 bits. The caller calls this SMC to program this key to the Rx and Tx ports 2506and for each substream corresponding to a single keyset. The platform should validate 2507the arguments `Ecam address` and `Rootport ID` before acting on it. The arguments `request ID` 2508and `cookie` are to be ignored for blocking mode and are pass-through to the response for 2509non-blocking mode. 2510 2511The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2512Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2513or non-blocking semantics. More details about IDE Setup flow can be found 2514in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2515 2516The parameters of the function are: 2517 2518 arg0 - The ecam address, to access and configure PCI devices in a system. 2519 2520 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2521 2522 arg2 - The IDE stream info associated with a physical device, this parameter packs the 2523 the keyset, direction, substream and stream ID info. 2524 2525 arg3 - Structure with key and IV info. 2526 2527 arg4 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode. 2528 2529 arg5 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking 2530 mode. 2531 2532The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT 2533if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned 2534only for non-blocking mode if the IDE-KM interface is busy or the request queue is full. 2535E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking 2536mode. 2537 2538Function : plat_rmmd_el3_ide_key_set_go() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2539~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2540 2541:: 2542 2543 Argument : uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 2544 Return : int 2545 2546This function activates the IDE stream at the Root Port once all the keys have been 2547programmed. The platform should validate the arguments `Ecam address` and `Rootport ID` 2548before acting on it. The arguments `request ID` and `cookie` are to be ignored for blocking 2549mode and are pass-through to the response for non-blocking mode. 2550 2551The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2552Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2553or non-blocking semantics. More details about IDE Setup flow can be found 2554in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2555 2556The parameters of the function are: 2557 2558 arg0 - The ecam address, to access and configure PCI devices in a system. 2559 2560 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2561 2562 arg2 - The IDE stream info associated with a physical device, this parameter packs the 2563 the keyset, direction, substream and stream ID info. 2564 2565 arg3 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode. 2566 2567 arg4 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking 2568 mode. 2569 2570The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT 2571if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned 2572only for non-blocking mode if the IDE-KM interface is busy or the request queue is full. 2573E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking 2574mode. 2575 2576Function : plat_rmmd_el3_ide_key_set_stop() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2577~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2578 2579:: 2580 2581 Argument : uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 2582 Return : int 2583 2584This function stops the IDE stream and is used to tear down the IDE stream at Root Port. 2585The platform should validate the arguments `Ecam address` and `Rootport ID` before acting 2586on it. The arguments `request ID` and `cookie` are to be ignored for blocking 2587mode and are pass-through to the response for non-blocking mode. 2588 2589The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2590Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2591or non-blocking semantics. More details about IDE Setup flow can be found 2592in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2593 2594The parameters of the function are: 2595 2596 arg0 - The ecam address, to access and configure PCI devices in a system. 2597 2598 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2599 2600 arg2 - The IDE stream info associated with a physical device, this parameter packs the 2601 the keyset, direction, substream and stream ID info. 2602 2603 arg3 - The request ID, is used in non-blocking mode only and can be ignored in blocking mode. 2604 2605 arg4 - The cookie variable, is used in non-blocking mode only and can be ignored in blocking 2606 mode. 2607 2608The function returns E_RMM_OK on success, E_RMM_INVAL if arguments are invalid, E_RMM_FAULT 2609if the key programming is unsuccesful, E_RMM_UNK for an unknown error, E_RMM_AGAIN returned 2610only for non-blocking mode if the IDE-KM interface is busy or the request queue is full. 2611E_RMM_INPROGRESS returned if the request is queued successfully and used only in non-blocking 2612mode. 2613 2614Function : plat_rmmd_el3_ide_km_pull_response() [mandatory when RMMD_ENABLE_IDE_KEY_PROG == 1] 2615~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2616 2617:: 2618 2619 Argument : uint64_t, uint64_t, uint64_t *, uint64_t *, uint64_t * 2620 Return : int 2621 2622This function retrieves a reponse for any of the prior non-blocking IDE-KM requests. The 2623caller has to identify the request and populate the accurate response. For blocking calls, 2624this function always returns E_RMM_UNK. 2625 2626The platform needs to ensure proper exclusives are in place when accessed from multiple CPUs. 2627Depending on the expected latency for IDE-KM interface, the platform should choose blocking 2628or non-blocking semantics. More details about IDE Setup flow can be found 2629in this `RFC <https://github.com/TF-RMM/tf-rmm/wiki/RFC:-EL3-RMM-IDE-KM-Interface>`_. 2630 2631The parameters of the function are: 2632 2633 arg0 - The ecam address, to access and configure PCI devices in a system. 2634 2635 arg1 - The rootport ID used to identify the PCIe rootport of a connected device. 2636 2637 arg2 - Retrieved response corresponding to the previous IDE_KM request. 2638 2639 arg3 - returns the passthrough request ID of the retrieved response. 2640 2641 arg4 - returns the passthrough cookie of the retrieved response. 2642 2643The function returns E_RMM_OK if response is retrieved successfully, E_RMM_INVAL if arguments 2644to this function are invalid, E_RMM_UNK if response retrieval failed for an unknown error or 2645IDE-KM interface is having blocking semantics, E_RMM_AGAIN if the response queue is empty. 2646 2647The `arg2` return parameter can return the following values: 2648E_RMM_OK - The previous request was successful. 2649E_RMM_FAULT - The previous request was not successful. 2650E_RMM_INVAL - Arguments to previous request were incorrect. 2651E_RMM_UNK - Previous request returned Unknown error. 2652 2653Function : bl31_plat_enable_mmu [optional] 2654~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2655 2656:: 2657 2658 Argument : uint32_t 2659 Return : void 2660 2661This function enables the MMU. The boot code calls this function with MMU and 2662caches disabled. This function should program necessary registers to enable 2663translation, and upon return, the MMU on the calling PE must be enabled. 2664 2665The function must honor flags passed in the first argument. These flags are 2666defined by the translation library, and can be found in the file 2667``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2668 2669On DynamIQ systems, this function must not use stack while enabling MMU, which 2670is how the function in xlat table library version 2 is implemented. 2671 2672Function : plat_init_apkey [optional] 2673~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2674 2675:: 2676 2677 Argument : void 2678 Return : uint128_t 2679 2680This function returns the 128-bit value which can be used to program ARMv8.3 2681pointer authentication keys. 2682 2683The value should be obtained from a reliable source of randomness. It will be 2684called each time a core powers up and it is the platform's responsibility to 2685decide when to regenerate the keys if generating them is an expensive operation. 2686 2687This function is only needed if ARMv8.3 pointer authentication is used in the 2688Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to 1, 2 or 3. 2689 2690Function : plat_get_syscnt_freq2() [mandatory] 2691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2692 2693:: 2694 2695 Argument : void 2696 Return : unsigned int 2697 2698This function is used by the architecture setup code to retrieve the counter 2699frequency for the CPU's generic timer. This value will be programmed into the 2700``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2701of the system counter, which is retrieved from the first entry in the frequency 2702modes table. 2703 2704#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2706 2707When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2708bytes) aligned to the cache line boundary that should be allocated per-cpu to 2709accommodate all the bakery locks. 2710 2711If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2712calculates the size of the ``.bakery_lock`` input section, aligns it to the 2713nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2714and stores the result in a linker symbol. This constant prevents a platform 2715from relying on the linker and provide a more efficient mechanism for 2716accessing per-cpu bakery lock information. 2717 2718If this constant is defined and its value is not equal to the value 2719calculated by the linker then a link time assertion is raised. A compile time 2720assertion is raised if the value of the constant is not aligned to the cache 2721line boundary. 2722 2723.. _porting_guide_sdei_requirements: 2724 2725SDEI porting requirements 2726~~~~~~~~~~~~~~~~~~~~~~~~~ 2727 2728The |SDEI| dispatcher requires the platform to provide the following macros 2729and functions, of which some are optional, and some others mandatory. 2730 2731Macros 2732...... 2733 2734Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2735^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2736 2737This macro must be defined to the EL3 exception priority level associated with 2738Normal |SDEI| events on the platform. This must have a higher value 2739(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2740 2741Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2742^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2743 2744This macro must be defined to the EL3 exception priority level associated with 2745Critical |SDEI| events on the platform. This must have a lower value 2746(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2747 2748**Note**: |SDEI| exception priorities must be the lowest among Secure 2749priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2750be higher than Normal |SDEI| priority. 2751 2752Functions 2753......... 2754 2755Function: int plat_sdei_validate_entry_point() [optional] 2756^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2757 2758:: 2759 2760 Argument: uintptr_t ep, unsigned int client_mode 2761 Return: int 2762 2763This function validates the entry point address of the event handler provided by 2764the client for both event registration and *Complete and Resume* |SDEI| calls. 2765The function ensures that the address is valid in the client translation regime. 2766 2767The second argument is the exception level that the client is executing in. It 2768can be Non-Secure EL1 or Non-Secure EL2. 2769 2770The function must return ``0`` for successful validation, or ``-1`` upon failure. 2771 2772The default implementation always returns ``0``. On Arm platforms, this function 2773translates the entry point address within the client translation regime and 2774further ensures that the resulting physical address is located in Non-secure 2775DRAM. 2776 2777Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2778^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2779 2780:: 2781 2782 Argument: uint64_t 2783 Argument: unsigned int 2784 Return: void 2785 2786|SDEI| specification requires that a PE comes out of reset with the events 2787masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2788|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2789time. 2790 2791Should a PE receive an interrupt that was bound to an |SDEI| event while the 2792events are masked on the PE, the dispatcher implementation invokes the function 2793``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2794interrupt and the interrupt ID are passed as parameters. 2795 2796The default implementation only prints out a warning message. 2797 2798.. _porting_guide_trng_requirements: 2799 2800TRNG porting requirements 2801~~~~~~~~~~~~~~~~~~~~~~~~~ 2802 2803The |TRNG| backend requires the platform to provide the following values 2804and mandatory functions. 2805 2806Values 2807...... 2808 2809value: uuid_t plat_trng_uuid [mandatory] 2810^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2811 2812This value must be defined to the UUID of the TRNG backend that is specific to 2813the hardware after ``plat_entropy_setup`` function is called. This value must 2814conform to the SMCCC calling convention; The most significant 32 bits of the 2815UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2816w0 indicates failure to get a TRNG source. 2817 2818Functions 2819......... 2820 2821Function: void plat_entropy_setup(void) [mandatory] 2822^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2823 2824:: 2825 2826 Argument: none 2827 Return: none 2828 2829This function is expected to do platform-specific initialization of any TRNG 2830hardware. This may include generating a UUID from a hardware-specific seed. 2831 2832Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2833^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2834 2835:: 2836 2837 Argument: uint64_t * 2838 Return: bool 2839 Out : when the return value is true, the entropy has been written into the 2840 storage pointed to 2841 2842This function writes entropy into storage provided by the caller. If no entropy 2843is available, it must return false and the storage must not be written. 2844 2845.. _psci_in_bl31: 2846 2847Power State Coordination Interface (PSCI) 2848-------------------------------------------- 2849 2850The TF-A implementation of the PSCI API is based around the concept of a 2851*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2852share some state on which power management operations can be performed as 2853specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2854a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2855*power domains* are arranged in a hierarchical tree structure and each 2856*power domain* can be identified in a system by the cpu index of any CPU that 2857is part of that domain and a *power domain level*. A processing element (for 2858example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2859logical grouping of CPUs that share some state, then level 1 is that group of 2860CPUs (for example, a cluster), and level 2 is a group of clusters (for 2861example, the system). More details on the power domain topology and its 2862organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2863 2864BL31's platform initialization code exports a pointer to the platform-specific 2865power management operations required for the PSCI implementation to function 2866correctly. This information is populated in the ``plat_psci_ops`` structure. The 2867PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2868power management operations on the power domains. For example, the target 2869CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2870handler (if present) is called for the CPU power domain. 2871 2872The ``power_state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2873describe composite power states specific to a platform. The PSCI implementation 2874defines a generic representation of the power-state parameter, which is an 2875array of local power states where each index corresponds to a power domain 2876level. Each entry contains the local power state the power domain at that power 2877level could enter. It depends on the ``validate_power_state()`` handler to 2878convert the power-state parameter (possibly encoding a composite power state) 2879passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2880 2881This 32-bit ``power_state`` parameter has two encoding formats (as described in the 2882ARM `PSCI`_ spec), controlled by the ``PSCI_EXTENDED_STATE_ID`` build option. 2883 2884The state ID field in this is entirely platform-defined. 2885Platforms must document their state ID conventions for OS developers. The 2886``power_state`` value is passed from the consumers (Like OSs) through generic PSCI 2887layers to the respective platform handler. 2888 2889The following functions form part of platform port of PSCI functionality. 2890 2891Function : plat_psci_stat_accounting_start() [optional] 2892~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2893 2894:: 2895 2896 Argument : const psci_power_state_t * 2897 Return : void 2898 2899This is an optional hook that platforms can implement for residency statistics 2900accounting before entering a low power state. The ``pwr_domain_state`` field of 2901``state_info`` (first argument) can be inspected if stat accounting is done 2902differently at CPU level versus higher levels. As an example, if the element at 2903index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2904state, special hardware logic may be programmed in order to keep track of the 2905residency statistics. For higher levels (array indices > 0), the residency 2906statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2907default implementation will use PMF to capture timestamps. 2908 2909Function : plat_psci_stat_accounting_stop() [optional] 2910~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2911 2912:: 2913 2914 Argument : const psci_power_state_t * 2915 Return : void 2916 2917This is an optional hook that platforms can implement for residency statistics 2918accounting after exiting from a low power state. The ``pwr_domain_state`` field 2919of ``state_info`` (first argument) can be inspected if stat accounting is done 2920differently at CPU level versus higher levels. As an example, if the element at 2921index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2922state, special hardware logic may be programmed in order to keep track of the 2923residency statistics. For higher levels (array indices > 0), the residency 2924statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2925default implementation will use PMF to capture timestamps. 2926 2927Function : plat_psci_stat_get_residency() [optional] 2928~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2929 2930:: 2931 2932 Argument : unsigned int, const psci_power_state_t *, unsigned int 2933 Return : u_register_t 2934 2935This is an optional interface that is is invoked after resuming from a low power 2936state and provides the time spent resident in that low power state by the power 2937domain at a particular power domain level. When a CPU wakes up from suspend, 2938all its parent power domain levels are also woken up. The generic PSCI code 2939invokes this function for each parent power domain that is resumed and it 2940identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2941argument) describes the low power state that the power domain has resumed from. 2942The current CPU is the first CPU in the power domain to resume from the low 2943power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2944CPU in the power domain to suspend and may be needed to calculate the residency 2945for that power domain. 2946 2947Function : plat_get_target_pwr_state() [optional] 2948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2949 2950:: 2951 2952 Argument : unsigned int, const plat_local_state_t *, unsigned int 2953 Return : plat_local_state_t 2954 2955The PSCI generic code uses this function to let the platform participate in 2956state coordination during a power management operation. The function is passed 2957a pointer to an array of platform specific local power state ``states`` (second 2958argument) which contains the requested power state for each CPU at a particular 2959power domain level ``lvl`` (first argument) within the power domain. The function 2960is expected to traverse this array of upto ``ncpus`` (third argument) and return 2961a coordinated target power state by the comparing all the requested power 2962states. The target power state should not be deeper than any of the requested 2963power states. 2964 2965A weak definition of this API is provided by default wherein it assumes 2966that the platform assigns a local state value in order of increasing depth 2967of the power state i.e. for two power states X & Y, if X < Y 2968then X represents a shallower power state than Y. As a result, the 2969coordinated target local power state for a power domain will be the minimum 2970of the requested local power state values. 2971 2972Function : plat_get_power_domain_tree_desc() [mandatory] 2973~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2974 2975:: 2976 2977 Argument : void 2978 Return : const unsigned char * 2979 2980This function returns a pointer to the byte array containing the power domain 2981topology tree description. The format and method to construct this array are 2982described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2983initialization code requires this array to be described by the platform, either 2984statically or dynamically, to initialize the power domain topology tree. In case 2985the array is populated dynamically, then plat_core_pos_by_mpidr() and 2986plat_my_core_pos() should also be implemented suitably so that the topology tree 2987description matches the CPU indices returned by these APIs. These APIs together 2988form the platform interface for the PSCI topology framework. 2989 2990Function : plat_setup_psci_ops() [mandatory] 2991~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2992 2993:: 2994 2995 Argument : uintptr_t, const plat_psci_ops ** 2996 Return : int 2997 2998This function may execute with the MMU and data caches enabled if the platform 2999port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 3000called by the primary CPU. 3001 3002This function is called by PSCI initialization code. Its purpose is to let 3003the platform layer know about the warm boot entrypoint through the 3004``sec_entrypoint`` (first argument) and to export handler routines for 3005platform-specific psci power management actions by populating the passed 3006pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 3007 3008A description of each member of this structure is given below. Please refer to 3009the Arm FVP specific implementation of these handlers in 3010``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 3011platform wants to support, the associated operation or operations in this 3012structure must be provided and implemented (Refer section 4 of 3013:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 3014function in a platform port, the operation should be removed from this 3015structure instead of providing an empty implementation. 3016 3017plat_psci_ops.cpu_standby() 3018........................... 3019 3020Perform the platform-specific actions to enter the standby state for a cpu 3021indicated by the passed argument. This provides a fast path for CPU standby 3022wherein overheads of PSCI state management and lock acquisition is avoided. 3023For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 3024the suspend state type specified in the ``power-state`` parameter should be 3025STANDBY and the target power domain level specified should be the CPU. The 3026handler should put the CPU into a low power retention state (usually by 3027issuing a wfi instruction) and ensure that it can be woken up from that 3028state by a normal interrupt. The generic code expects the handler to succeed. 3029 3030plat_psci_ops.pwr_domain_on() 3031............................. 3032 3033Perform the platform specific actions to power on a CPU, specified 3034by the ``MPIDR`` (first argument). The generic code expects the platform to 3035return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 3036 3037plat_psci_ops.pwr_domain_off_early() [optional] 3038............................................... 3039 3040This optional function performs the platform specific actions to check if 3041powering off the calling CPU and its higher parent power domain levels as 3042indicated by the ``target_state`` (first argument) is possible or allowed. 3043 3044The ``target_state`` encodes the platform coordinated target local power states 3045for the CPU power domain and its parent power domain levels. 3046 3047For this handler, the local power state for the CPU power domain will be a 3048power down state where as it could be either power down, retention or run state 3049for the higher power domain levels depending on the result of state 3050coordination. The generic code expects PSCI_E_DENIED return code if the 3051platform thinks that CPU_OFF should not proceed on the calling CPU. 3052 3053plat_psci_ops.pwr_domain_off() 3054.............................. 3055 3056Perform the platform specific actions to prepare to power off the calling CPU 3057and its higher parent power domain levels as indicated by the ``target_state`` 3058(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 3059 3060The ``target_state`` encodes the platform coordinated target local power states 3061for the CPU power domain and its parent power domain levels. The handler 3062needs to perform power management operation corresponding to the local state 3063at each power level. 3064 3065For this handler, the local power state for the CPU power domain will be a 3066power down state where as it could be either power down, retention or run state 3067for the higher power domain levels depending on the result of state 3068coordination. The generic code expects the handler to succeed. 3069 3070plat_psci_ops.pwr_domain_validate_suspend() [optional] 3071...................................................... 3072 3073This is an optional function that is only compiled into the build if the build 3074option ``PSCI_OS_INIT_MODE`` is enabled. 3075 3076If implemented, this function allows the platform to perform platform specific 3077validations based on hardware states. The generic code expects this function to 3078return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 3079PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 3080 3081plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 3082........................................................... 3083 3084This optional function may be used as a performance optimization to replace 3085or complement pwr_domain_suspend() on some platforms. Its calling semantics 3086are identical to pwr_domain_suspend(), except the PSCI implementation only 3087calls this function when suspending to a power down state, and it guarantees 3088that data caches are enabled. 3089 3090When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 3091before calling pwr_domain_suspend(). If the target_state corresponds to a 3092power down state and it is safe to perform some or all of the platform 3093specific actions in that function with data caches enabled, it may be more 3094efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 3095= 1, data caches remain enabled throughout, and so there is no advantage to 3096moving platform specific actions to this function. 3097 3098plat_psci_ops.pwr_domain_suspend() 3099.................................. 3100 3101Perform the platform specific actions to prepare to suspend the calling 3102CPU and its higher parent power domain levels as indicated by the 3103``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 3104API implementation. 3105 3106The ``target_state`` has a similar meaning as described in 3107the ``pwr_domain_off()`` operation. It encodes the platform coordinated 3108target local power states for the CPU power domain and its parent 3109power domain levels. The handler needs to perform power management operation 3110corresponding to the local state at each power level. The generic code 3111expects the handler to succeed. 3112 3113The difference between turning a power domain off versus suspending it is that 3114in the former case, the power domain is expected to re-initialize its state 3115when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 3116case, the power domain is expected to save enough state so that it can resume 3117execution by restoring this state when its powered on (see 3118``pwr_domain_suspend_finish()``). 3119 3120When suspending a core, the platform can also choose to power off the GICv3 3121Redistributor and ITS through an implementation-defined sequence. To achieve 3122this safely, the ITS context must be saved first. The architectural part is 3123implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 3124sequence is implementation defined and it is therefore the responsibility of 3125the platform code to implement the necessary sequence. Then the GIC 3126Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 3127Powering off the Redistributor requires the implementation to support it and it 3128is the responsibility of the platform code to execute the right implementation 3129defined sequence. 3130 3131When a system suspend is requested, the platform can also make use of the 3132``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 3133it has saved the context of the Redistributors and ITS of all the cores in the 3134system. The context of the Distributor can be large and may require it to be 3135allocated in a special area if it cannot fit in the platform's global static 3136data, for example in DRAM. The Distributor can then be powered down using an 3137implementation-defined sequence. 3138 3139plat_psci_ops.pwr_domain_pwr_down() 3140....................................... 3141 3142This is an optional function and, if implemented, is expected to perform 3143platform specific actions before the CPU is powered down. Since this function is 3144invoked outside the PSCI locks, the actions performed in this hook must be local 3145to the CPU or the platform must ensure that races between multiple CPUs cannot 3146occur. 3147 3148The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 3149operation and it encodes the platform coordinated target local power states for 3150the CPU power domain and its parent power domain levels. 3151 3152It is preferred that this function returns. The caller will invoke 3153``wfi()`` to powerdown the CPU, mitigate any powerdown errata, 3154and handle any wakeups that may arise. Previously, this function did not return 3155and instead called ``wfi`` (in an infinite loop) directly. This is still 3156possible on platforms where this is guaranteed to be terminal, however, it is 3157strongly discouraged going forward. 3158 3159Previously this function was called ``pwr_domain_pwr_down_wfi()`` and invoked 3160``psci_power_down_wfi()`` (now removed). 3161 3162plat_psci_ops.pwr_domain_on_finish() 3163.................................... 3164 3165This function is called by the PSCI implementation after the calling CPU is 3166powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 3167It performs the platform-specific setup required to initialize enough state for 3168this CPU to enter the normal world and also provide secure runtime firmware 3169services. 3170 3171The ``target_state`` (first argument) is the prior state of the power domains 3172immediately before the CPU was turned on. It indicates which power domains 3173above the CPU might require initialization due to having previously been in 3174low power states. The generic code expects the handler to succeed. 3175 3176plat_psci_ops.pwr_domain_on_finish_late() [optional] 3177........................................................... 3178 3179This optional function is called by the PSCI implementation after the calling 3180CPU is fully powered on with respective data caches enabled. The calling CPU and 3181the associated cluster are guaranteed to be participating in coherency. This 3182function gives the flexibility to perform any platform-specific actions safely, 3183such as initialization or modification of shared data structures, without the 3184overhead of explicit cache maintainace operations. 3185 3186The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 3187operation. The generic code expects the handler to succeed. 3188 3189plat_psci_ops.pwr_domain_suspend_finish() 3190......................................... 3191 3192This function is called by the PSCI implementation after the calling CPU is 3193powered on and released from reset in response to an asynchronous wakeup 3194event, for example a timer interrupt that was programmed by the CPU during the 3195``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 3196setup required to restore the saved state for this CPU to resume execution 3197in the normal world and also provide secure runtime firmware services. 3198 3199The ``target_state`` (first argument) has a similar meaning as described in 3200the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 3201to succeed. 3202 3203If the Distributor, Redistributors or ITS have been powered off as part of a 3204suspend, their context must be restored in this function in the reverse order 3205to how they were saved during suspend sequence. 3206 3207plat_psci_ops.system_off() 3208.......................... 3209 3210This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 3211call. It performs the platform-specific system poweroff sequence after 3212notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 3213function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3214 3215plat_psci_ops.system_reset() 3216............................ 3217 3218This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 3219call. It performs the platform-specific system reset sequence after 3220notifying the Secure Payload Dispatcher. The caller will call ``wfi`` if this 3221function returns, similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3222 3223plat_psci_ops.validate_power_state() 3224.................................... 3225 3226This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 3227call to validate the ``power_state`` parameter of the PSCI API and if valid, 3228populate it in ``req_state`` (second argument) array as power domain level 3229specific local states. If the ``power_state`` is invalid, the platform must 3230return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 3231normal world PSCI client. 3232 3233plat_psci_ops.validate_ns_entrypoint() 3234...................................... 3235 3236This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 3237``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 3238parameter passed by the normal world. If the ``entry_point`` is invalid, 3239the platform must return PSCI_E_INVALID_ADDRESS as error, which is 3240propagated back to the normal world PSCI client. 3241 3242plat_psci_ops.get_sys_suspend_power_state() 3243........................................... 3244 3245This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 3246call to get the ``req_state`` parameter from platform which encodes the power 3247domain level specific local states to suspend to system affinity level. The 3248``req_state`` will be utilized to do the PSCI state coordination and 3249``pwr_domain_suspend()`` will be invoked with the coordinated target state to 3250enter system suspend. 3251 3252plat_psci_ops.get_pwr_lvl_state_idx() 3253..................................... 3254 3255This is an optional function and, if implemented, is invoked by the PSCI 3256implementation to convert the ``local_state`` (first argument) at a specified 3257``pwr_lvl`` (second argument) to an index between 0 and 3258``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 3259supports more than two local power states at each power domain level, that is 3260``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 3261local power states. 3262 3263plat_psci_ops.translate_power_state_by_mpidr() 3264.............................................. 3265 3266This is an optional function and, if implemented, verifies the ``power_state`` 3267(second argument) parameter of the PSCI API corresponding to a target power 3268domain. The target power domain is identified by using both ``MPIDR`` (first 3269argument) and the power domain level encoded in ``power_state``. The power domain 3270level specific local states are to be extracted from ``power_state`` and be 3271populated in the ``output_state`` (third argument) array. The functionality 3272is similar to the ``validate_power_state`` function described above and is 3273envisaged to be used in case the validity of ``power_state`` depend on the 3274targeted power domain. If the ``power_state`` is invalid for the targeted power 3275domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 3276function is not implemented, then the generic implementation relies on 3277``validate_power_state`` function to translate the ``power_state``. 3278 3279This function can also be used in case the platform wants to support local 3280power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 3281APIs as described in Section 5.18 of `PSCI`_. 3282 3283plat_psci_ops.get_node_hw_state() 3284................................. 3285 3286This is an optional function. If implemented this function is intended to return 3287the power state of a node (identified by the first parameter, the ``MPIDR``) in 3288the power domain topology (identified by the second parameter, ``power_level``), 3289as retrieved from a power controller or equivalent component on the platform. 3290Upon successful completion, the implementation must map and return the final 3291status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 3292must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 3293appropriate. 3294 3295Implementations are not expected to handle ``power_levels`` greater than 3296``PLAT_MAX_PWR_LVL``. 3297 3298plat_psci_ops.system_reset2() 3299............................. 3300 3301This is an optional function. If implemented this function is 3302called during the ``SYSTEM_RESET2`` call to perform a reset 3303based on the first parameter ``reset_type`` as specified in 3304`PSCI`_. The parameter ``cookie`` can be used to pass additional 3305reset information. If the ``reset_type`` is not supported, the 3306function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 3307resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 3308and vendor reset can return other PSCI error codes as defined 3309in `PSCI`_. If this function returns success, the caller will call 3310``wfi`` similar to `plat_psci_ops.pwr_domain_pwr_down()`_. 3311 3312plat_psci_ops.write_mem_protect() 3313................................. 3314 3315This is an optional function. If implemented it enables or disables the 3316``MEM_PROTECT`` functionality based on the value of ``val``. 3317A non-zero value enables ``MEM_PROTECT`` and a value of zero 3318disables it. Upon encountering failures it must return a negative value 3319and on success it must return 0. 3320 3321plat_psci_ops.read_mem_protect() 3322................................ 3323 3324This is an optional function. If implemented it returns the current 3325state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 3326failures it must return a negative value and on success it must 3327return 0. 3328 3329plat_psci_ops.mem_protect_chk() 3330............................... 3331 3332This is an optional function. If implemented it checks if a memory 3333region defined by a base address ``base`` and with a size of ``length`` 3334bytes is protected by ``MEM_PROTECT``. If the region is protected 3335then it must return 0, otherwise it must return a negative number. 3336 3337.. _porting_guide_imf_in_bl31: 3338 3339Secure payload power management callback 3340~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3341 3342During PSCI power management operations, the EL3 Runtime Software may 3343need to perform some bookkeeping, and PSCI library provides 3344``spd_pm_ops_t`` callbacks for this purpose. These hooks must be 3345populated and registered by using ``psci_register_spd_pm_hook()`` PSCI 3346library interface. 3347 3348Typical bookkeeping during PSCI power management calls include save/restore 3349of the EL3 Runtime Software context. Also if the EL3 Runtime Software makes 3350use of secure interrupts, then these interrupts must also be managed 3351appropriately during CPU power down/power up. Any secure interrupt targeted 3352to the current CPU must be disabled or re-targeted to other running CPU prior 3353to power down of the current CPU. During power up, these interrupt can be 3354enabled/re-targeted back to the current CPU. 3355 3356.. code:: c 3357 3358 typedef struct spd_pm_ops { 3359 void (*svc_on)(u_register_t target_cpu); 3360 int32_t (*svc_off)(u_register_t __unused); 3361 void (*svc_suspend)(u_register_t max_off_pwrlvl); 3362 void (*svc_on_finish)(u_register_t __unused); 3363 void (*svc_suspend_finish)(u_register_t max_off_pwrlvl); 3364 int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu); 3365 int32_t (*svc_migrate_info)(u_register_t *resident_cpu); 3366 void (*svc_system_off)(void); 3367 void (*svc_system_reset)(void); 3368 } spd_pm_ops_t; 3369 3370A brief description of each callback is given below: 3371 3372- svc_on, svc_off, svc_on_finish 3373 3374 The ``svc_on``, ``svc_off`` callbacks are called during PSCI_CPU_ON, 3375 PSCI_CPU_OFF APIs respectively. The ``svc_on_finish`` is called when the 3376 target CPU of PSCI_CPU_ON API powers up and executes the 3377 ``psci_warmboot_entrypoint()`` PSCI library interface. 3378 3379- svc_suspend, svc_suspend_finish 3380 3381 The ``svc_suspend`` callback is called during power down bu either 3382 PSCI_SUSPEND or PSCI_SYSTEM_SUSPEND APIs. The ``svc_suspend_finish`` is 3383 called when the CPU wakes up from suspend and executes the 3384 ``psci_warmboot_entrypoint()`` PSCI library interface. The ``max_off_pwrlvl`` 3385 (first parameter) denotes the highest power domain level being powered down 3386 to or woken up from suspend. 3387 3388- svc_system_off, svc_system_reset 3389 3390 These callbacks are called during PSCI_SYSTEM_OFF and PSCI_SYSTEM_RESET 3391 PSCI APIs respectively. 3392 3393- svc_migrate_info 3394 3395 This callback is called in response to PSCI_MIGRATE_INFO_TYPE or 3396 PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must 3397 correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described 3398 in `PSCI`_. If the secure payload is a Uniprocessor (UP) 3399 implementation, then it must update the mpidr of the CPU it is resident in 3400 via ``resident_cpu`` (first argument). The updates to ``resident_cpu`` is 3401 ignored if the secure payload is a multiprocessor (MP) implementation. 3402 3403- svc_migrate 3404 3405 This callback is only relevant if the secure payload in EL3 Runtime 3406 Software is a Uniprocessor (UP) implementation and supports migration from 3407 the current CPU ``from_cpu`` (first argument) to another CPU ``to_cpu`` 3408 (second argument). This callback is called in response to PSCI_MIGRATE 3409 API. This callback is never called if the secure payload is a 3410 Multiprocessor (MP) implementation. 3411 3412Interrupt Management framework (in BL31) 3413---------------------------------------- 3414 3415BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 3416generated in either security state and targeted to EL1 or EL2 in the non-secure 3417state or EL3/S-EL1 in the secure state. The design of this framework is 3418described in the :ref:`Interrupt Management Framework` 3419 3420A platform should export the following APIs to support the IMF. The following 3421text briefly describes each API and its implementation in Arm standard 3422platforms. The API implementation depends upon the type of interrupt controller 3423present in the platform. Arm standard platform layer supports both 3424`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 3425and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 3426FVP can be configured to use either GICv2 or GICv3 depending on the build flag 3427``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 3428details). 3429 3430See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 3431 3432Function : plat_interrupt_type_to_line() [mandatory] 3433~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3434 3435:: 3436 3437 Argument : uint32_t, uint32_t 3438 Return : uint32_t 3439 3440The Arm processor signals an interrupt exception either through the IRQ or FIQ 3441interrupt line. The specific line that is signaled depends on how the interrupt 3442controller (IC) reports different interrupt types from an execution context in 3443either security state. The IMF uses this API to determine which interrupt line 3444the platform IC uses to signal each type of interrupt supported by the framework 3445from a given security state. This API must be invoked at EL3. 3446 3447The first parameter will be one of the ``INTR_TYPE_*`` values (see 3448:ref:`Interrupt Management Framework`) indicating the target type of the 3449interrupt, the second parameter is the security state of the originating 3450execution context. The return result is the bit position in the ``SCR_EL3`` 3451register of the respective interrupt trap: IRQ=1, FIQ=2. 3452 3453In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3454configured as FIQs and Non-secure interrupts as IRQs from either security 3455state. 3456 3457In the case of Arm standard platforms using GICv3, the interrupt line to be 3458configured depends on the security state of the execution context when the 3459interrupt is signalled and are as follows: 3460 3461- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3462 NS-EL0/1/2 context. 3463- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3464 in the NS-EL0/1/2 context. 3465- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3466 context. 3467 3468Function : plat_ic_get_pending_interrupt_type() [mandatory] 3469~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3470 3471:: 3472 3473 Argument : void 3474 Return : uint32_t 3475 3476This API returns the type of the highest priority pending interrupt at the 3477platform IC. The IMF uses the interrupt type to retrieve the corresponding 3478handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3479pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3480``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3481 3482In the case of Arm standard platforms using GICv2, the *Highest Priority 3483Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3484the pending interrupt. The type of interrupt depends upon the id value as 3485follows. 3486 3487#. id < 1022 is reported as a S-EL1 interrupt 3488#. id = 1022 is reported as a Non-secure interrupt. 3489#. id = 1023 is reported as an invalid interrupt type. 3490 3491In the case of Arm standard platforms using GICv3, the system register 3492``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3493is read to determine the id of the pending interrupt. The type of interrupt 3494depends upon the id value as follows. 3495 3496#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3497#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3498#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3499#. All other interrupt id's are reported as EL3 interrupt. 3500 3501Function : plat_ic_get_pending_interrupt_id() [mandatory] 3502~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3503 3504:: 3505 3506 Argument : void 3507 Return : uint32_t 3508 3509This API returns the id of the highest priority pending interrupt at the 3510platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3511pending. 3512 3513In the case of Arm standard platforms using GICv2, the *Highest Priority 3514Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3515pending interrupt. The id that is returned by API depends upon the value of 3516the id read from the interrupt controller as follows. 3517 3518#. id < 1022. id is returned as is. 3519#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3520 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3521 This id is returned by the API. 3522#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3523 3524In the case of Arm standard platforms using GICv3, if the API is invoked from 3525EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3526group 0 Register*, is read to determine the id of the pending interrupt. The id 3527that is returned by API depends upon the value of the id read from the 3528interrupt controller as follows. 3529 3530#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3531#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3532 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3533 Register* is read to determine the id of the group 1 interrupt. This id 3534 is returned by the API as long as it is a valid interrupt id 3535#. If the id is any of the special interrupt identifiers, 3536 ``INTR_ID_UNAVAILABLE`` is returned. 3537 3538When the API invoked from S-EL1 for GICv3 systems, the id read from system 3539register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3540Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3541``INTR_ID_UNAVAILABLE`` is returned. 3542 3543Function : plat_ic_acknowledge_interrupt() [mandatory] 3544~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3545 3546:: 3547 3548 Argument : void 3549 Return : uint32_t 3550 3551This API is used by the CPU to indicate to the platform IC that processing of 3552the highest pending interrupt has begun. It should return the raw, unmodified 3553value obtained from the interrupt controller when acknowledging an interrupt. 3554The actual interrupt number shall be extracted from this raw value using the API 3555`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3556 3557This function in Arm standard platforms using GICv2, reads the *Interrupt 3558Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3559priority pending interrupt from pending to active in the interrupt controller. 3560It returns the value read from the ``GICC_IAR``, unmodified. 3561 3562In the case of Arm standard platforms using GICv3, if the API is invoked 3563from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3564Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3565reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3566group 1*. The read changes the state of the highest pending interrupt from 3567pending to active in the interrupt controller. The value read is returned 3568unmodified. 3569 3570The TSP uses this API to start processing of the secure physical timer 3571interrupt. 3572 3573Function : plat_ic_end_of_interrupt() [mandatory] 3574~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3575 3576:: 3577 3578 Argument : uint32_t 3579 Return : void 3580 3581This API is used by the CPU to indicate to the platform IC that processing of 3582the interrupt corresponding to the id (passed as the parameter) has 3583finished. The id should be the same as the id returned by the 3584``plat_ic_acknowledge_interrupt()`` API. 3585 3586Arm standard platforms write the id to the *End of Interrupt Register* 3587(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3588system register in case of GICv3 depending on where the API is invoked from, 3589EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3590controller. 3591 3592The TSP uses this API to finish processing of the secure physical timer 3593interrupt. 3594 3595Function : plat_ic_get_interrupt_type() [mandatory] 3596~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3597 3598:: 3599 3600 Argument : uint32_t 3601 Return : uint32_t 3602 3603This API returns the type of the interrupt id passed as the parameter. 3604``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3605interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3606returned depending upon how the interrupt has been configured by the platform 3607IC. This API must be invoked at EL3. 3608 3609Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3610and Non-secure interrupts as Group1 interrupts. It reads the group value 3611corresponding to the interrupt id from the relevant *Interrupt Group Register* 3612(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3613 3614In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3615Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3616(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3617as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3618 3619Registering a console 3620--------------------- 3621 3622Platforms will need to implement the TF-A console framework to register and use 3623a console for visual data output in TF-A. These can be used for data output during 3624the different stages of the firmware boot process and also for debugging purposes. 3625 3626The console framework can be used to output data on to a console using a number of 3627TF-A supported UARTs. Multiple consoles can be registered at the same time with 3628different output scopes (BOOT, RUNTIME, CRASH) so that data can be displayed on 3629their respective consoles without unnecessary cluttering of a single console. 3630 3631Information for registering a console can be found in the :ref:`Console Framework` section 3632of the :ref:`System Design` documentation. 3633 3634Common helper functions 3635----------------------- 3636Function : elx_panic() 3637~~~~~~~~~~~~~~~~~~~~~~ 3638 3639:: 3640 3641 Argument : void 3642 Return : void 3643 3644This API is called from assembly files when reporting a critical failure 3645that has occured in lower EL and is been trapped in EL3. This call 3646**must not** return. 3647 3648Function : el3_panic() 3649~~~~~~~~~~~~~~~~~~~~~~ 3650 3651:: 3652 3653 Argument : void 3654 Return : void 3655 3656This API is called from assembly files when encountering a critical failure that 3657cannot be recovered from. This function assumes that it is invoked from a C 3658runtime environment i.e. valid stack exists. This call **must not** return. 3659 3660Function : panic() 3661~~~~~~~~~~~~~~~~~~ 3662 3663:: 3664 3665 Argument : void 3666 Return : void 3667 3668This API called from C files when encountering a critical failure that cannot 3669be recovered from. This function in turn prints backtrace (if enabled) and calls 3670el3_panic(). This call **must not** return. 3671 3672Crash Reporting mechanism (in BL31) 3673----------------------------------- 3674 3675BL31 implements a crash reporting mechanism which prints the various registers 3676of the CPU to enable quick crash analysis and debugging. This mechanism relies 3677on the platform implementing ``plat_crash_console_init``, 3678``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3679 3680The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3681implementation of all of them. Platforms may include this file to their 3682makefiles in order to benefit from them. By default, they will cause the crash 3683output to be routed over the normal console infrastructure and get printed on 3684consoles configured to output in crash state. ``console_set_scope()`` can be 3685used to control whether a console is used for crash output. 3686 3687.. note:: 3688 Platforms are responsible for making sure that they only mark consoles for 3689 use in the crash scope that are able to support this, i.e. that are written 3690 in assembly and conform with the register clobber rules for putc() 3691 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3692 3693In some cases (such as debugging very early crashes that happen before the 3694normal boot console can be set up), platforms may want to control crash output 3695more explicitly. These platforms may instead provide custom implementations for 3696these. They are executed outside of a C environment and without a stack. Many 3697console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3698that are designed to be used by these functions. See Arm platforms (like juno) 3699for an example of this. 3700 3701Function : plat_crash_console_init [mandatory] 3702~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3703 3704:: 3705 3706 Argument : void 3707 Return : int 3708 3709This API is used by the crash reporting mechanism to initialize the crash 3710console. It must only use the general purpose registers x0 through x7 to do the 3711initialization and returns 1 on success. 3712 3713Function : plat_crash_console_putc [mandatory] 3714~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3715 3716:: 3717 3718 Argument : int 3719 Return : int 3720 3721This API is used by the crash reporting mechanism to print a character on the 3722designated crash console. It must only use general purpose registers x1 and 3723x2 to do its work. The parameter and the return value are in general purpose 3724register x0. 3725 3726Function : plat_crash_console_flush [mandatory] 3727~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3728 3729:: 3730 3731 Argument : void 3732 Return : void 3733 3734This API is used by the crash reporting mechanism to force write of all buffered 3735data on the designated crash console. It should only use general purpose 3736registers x0 through x5 to do its work. 3737 3738Function : plat_setup_early_console [optional] 3739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3740 3741:: 3742 3743 Argument : void 3744 Return : void 3745 3746This API is used to setup the early console, it is required only if the flag 3747``EARLY_CONSOLE`` is enabled. 3748 3749.. _External Abort handling and RAS Support: 3750 3751External Abort handling and RAS Support 3752--------------------------------------- 3753 3754If any cores on the platform support powerdown abandon (check the "Core powerup 3755and powerdown sequence" in their TRMs), then 3756these functions should be able to handle being called with power domains off and 3757after the powerdown ``wfi``. In other words it may run after a call to 3758``pwr_domain_suspend()`` and before a call to ``pwr_domain_suspend_finish()`` 3759(and their power off counterparts). 3760 3761Should this not be desirable, or if there is no powerdown abandon support, then 3762RAS errors should be masked by writing any relevant error records in any 3763powerdown hooks to prevent deadlocks due to a RAS error after the point of no 3764return. See the core's TRM for further information. 3765 3766Function : plat_ea_handler 3767~~~~~~~~~~~~~~~~~~~~~~~~~~ 3768 3769:: 3770 3771 Argument : int 3772 Argument : uint64_t 3773 Argument : void * 3774 Argument : void * 3775 Argument : uint64_t 3776 Return : void 3777 3778This function is invoked by the runtime exception handling framework for the 3779platform to handle an External Abort received at EL3. The intention of the 3780function is to attempt to resolve the cause of External Abort and return; 3781if that's not possible then an orderly shutdown of the system is initiated. 3782 3783The first parameter (``int ea_reason``) indicates the reason for External Abort. 3784Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3785 3786The second parameter (``uint64_t syndrome``) is the respective syndrome 3787presented to EL3 after having received the External Abort. Depending on the 3788nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3789can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3790 3791The third parameter (``void *cookie``) is unused for now. The fourth parameter 3792(``void *handle``) is a pointer to the preempted context. The fifth parameter 3793(``uint64_t flags``) indicates the preempted security state. These parameters 3794are received from the top-level exception handler. 3795 3796This function must be implemented if a platform expects Firmware First handling 3797of External Aborts. 3798 3799Function : plat_handle_uncontainable_ea 3800~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3801 3802:: 3803 3804 Argument : int 3805 Argument : uint64_t 3806 Return : void 3807 3808This function is invoked by the RAS framework when an External Abort of 3809Uncontainable type is received at EL3. Due to the critical nature of 3810Uncontainable errors, the intention of this function is to initiate orderly 3811shutdown of the system, and is not expected to return. 3812 3813This function must be implemented in assembly. 3814 3815The first and second parameters are the same as that of ``plat_ea_handler``. 3816 3817The default implementation of this function calls 3818``report_unhandled_exception``. 3819 3820Function : plat_handle_double_fault 3821~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3822 3823:: 3824 3825 Argument : int 3826 Argument : uint64_t 3827 Return : void 3828 3829This function is invoked by the RAS framework when another External Abort is 3830received at EL3 while one is already being handled. I.e., a call to 3831``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3832this function is to initiate orderly shutdown of the system, and is not expected 3833recover or return. 3834 3835This function must be implemented in assembly. 3836 3837The first and second parameters are the same as that of ``plat_ea_handler``. 3838 3839The default implementation of this function calls 3840``report_unhandled_exception``. 3841 3842Function : plat_handle_el3_ea 3843~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3844 3845:: 3846 3847 Return : void 3848 3849This function is invoked when an External Abort is received while executing in 3850EL3. Due to its critical nature, the intention of this function is to initiate 3851orderly shutdown of the system, and is not expected recover or return. 3852 3853This function must be implemented in assembly. 3854 3855The default implementation of this function calls 3856``report_unhandled_exception``. 3857 3858Function : plat_handle_rng_trap 3859~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3860 3861:: 3862 3863 Argument : uint64_t 3864 Argument : cpu_context_t * 3865 Return : int 3866 3867This function is invoked by BL31's exception handler when there is a synchronous 3868system register trap caused by access to the RNDR or RNDRRS registers. It allows 3869platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3870emulate those system registers by returing back some entropy to the lower EL. 3871 3872The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3873syndrome register, which encodes the instruction that was trapped. The interesting 3874information in there is the target register (``get_sysreg_iss_rt()``). 3875 3876The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3877lower exception level, at the time when the execution of the ``mrs`` instruction 3878was trapped. Its content can be changed, to put the entropy into the target 3879register. 3880 3881The return value indicates how to proceed: 3882 3883- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3884- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3885 to the same instruction, so its execution will be repeated. 3886- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3887 to the next instruction. 3888 3889This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3890 3891Function : plat_handle_impdef_trap 3892~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3893 3894:: 3895 3896 Argument : uint64_t 3897 Argument : cpu_context_t * 3898 Return : int 3899 3900This function is invoked by BL31's exception handler when there is a synchronous 3901system register trap caused by access to the implementation defined registers. 3902It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system 3903registers choosing to program bits of their choice. If using in combination with 3904``ARCH_FEATURE_AVAILABILITY``, the macros 3905{SCR,MDCR,CPTR}_PLAT_{BITS,IGNORED,FLIPPED} should be defined to report correct 3906results. 3907 3908The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3909syndrome register, which encodes the instruction that was trapped. 3910 3911The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3912lower exception level, at the time when the execution of the ``mrs`` instruction 3913was trapped. 3914 3915The return value indicates how to proceed: 3916 3917- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3918- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3919 to the same instruction, so its execution will be repeated. 3920- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3921 to the next instruction. 3922 3923This function needs to be implemented by a platform if it enables 3924IMPDEF_SYSREG_TRAP. 3925 3926Build flags 3927----------- 3928 3929There are some build flags which can be defined by the platform to control 3930inclusion or exclusion of certain BL stages from the FIP image. These flags 3931need to be defined in the platform makefile which will get included by the 3932build system. 3933 3934- **NEED_BL33** 3935 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3936 build option should be supplied as a build option. The platform has the 3937 option of excluding the BL33 image in the ``fip`` image by defining this flag 3938 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3939 are used, this flag will be set to ``no`` automatically. 3940 3941- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR** 3942 By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``, 3943 if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and 3944 ARM_ARCH_MINOR then mandatory Architectural features available for that Arch 3945 version will be enabled by default and any optional Arch feature supported by 3946 the Architecture and available in TF-A can be enabled from platform specific 3947 makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory 3948 and optional Arch specific features. 3949 3950Platform include paths 3951---------------------- 3952 3953Platforms are allowed to add more include paths to be passed to the compiler. 3954The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3955particular for the file ``platform_def.h``. 3956 3957Example: 3958 3959.. code:: c 3960 3961 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3962 3963C Library 3964--------- 3965 3966To avoid subtle toolchain behavioral dependencies, the header files provided 3967by the compiler are not used. The software is built with the ``-nostdinc`` flag 3968to ensure no headers are included from the toolchain inadvertently. Instead the 3969required headers are included in the TF-A source tree. The library only 3970contains those C library definitions required by the local implementation. If 3971more functionality is required, the needed library functions will need to be 3972added to the local implementation. 3973 3974Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3975been written specifically for TF-A. Some implementation files have been obtained 3976from `FreeBSD`_, others have been written specifically for TF-A as well. The 3977files can be found in ``include/lib/libc`` and ``lib/libc``. 3978 3979SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3980can be obtained from http://github.com/freebsd/freebsd. 3981 3982Storage abstraction layer 3983------------------------- 3984 3985In order to improve platform independence and portability a storage abstraction 3986layer is used to load data from non-volatile platform storage. Currently 3987storage access is only required by BL1 and BL2 phases and performed inside the 3988``load_image()`` function in ``bl_common.c``. 3989 3990.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3991 3992It is mandatory to implement at least one storage driver. For the Arm 3993development platforms the Firmware Image Package (FIP) driver is provided as 3994the default means to load data from storage (see :ref:`firmware_design_fip`). 3995The storage layer is described in the header file 3996``include/drivers/io/io_storage.h``. The implementation of the common library is 3997in ``drivers/io/io_storage.c`` and the driver files are located in 3998``drivers/io/``. 3999 4000.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 4001 4002Each IO driver must provide ``io_dev_*`` structures, as described in 4003``drivers/io/io_driver.h``. These are returned via a mandatory registration 4004function that is called on platform initialization. The semi-hosting driver 4005implementation in ``io_semihosting.c`` can be used as an example. 4006 4007Each platform should register devices and their drivers via the storage 4008abstraction layer. These drivers then need to be initialized by bootloader 4009phases as required in their respective ``blx_platform_setup()`` functions. 4010 4011.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 4012 4013The storage abstraction layer provides mechanisms (``io_dev_init()``) to 4014initialize storage devices before IO operations are called. 4015 4016.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 4017 4018The basic operations supported by the layer 4019include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 4020Drivers do not have to implement all operations, but each platform must 4021provide at least one driver for a device capable of supporting generic 4022operations such as loading a bootloader image. 4023 4024The current implementation only allows for known images to be loaded by the 4025firmware. These images are specified by using their identifiers, as defined in 4026``include/plat/common/common_def.h`` (or a separate header file included from 4027there). The platform layer (``plat_get_image_source()``) then returns a reference 4028to a device and a driver-specific ``spec`` which will be understood by the driver 4029to allow access to the image data. 4030 4031The layer is designed in such a way that is it possible to chain drivers with 4032other drivers. For example, file-system drivers may be implemented on top of 4033physical block devices, both represented by IO devices with corresponding 4034drivers. In such a case, the file-system "binding" with the block device may 4035be deferred until the file-system device is initialised. 4036 4037The abstraction currently depends on structures being statically allocated 4038by the drivers and callers, as the system does not yet provide a means of 4039dynamically allocating memory. This may also have the affect of limiting the 4040amount of open resources per driver. 4041 4042Measured Boot Platform Interface 4043-------------------------------- 4044 4045Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer 4046to :ref:`Measured Boot Design` for more details. 4047 4048Live Firmware Activation Interface 4049---------------------------------- 4050 4051Function : plat_lfa_get_components() 4052~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4053 4054:: 4055 4056 Argument : plat_lfa_component_info_t ** 4057 Return : int 4058 4059This platform API provides the list of LFA components available for activation. 4060It populates a pointer to an array of ``plat_lfa_component_info_t`` structures, 4061which contain information about each component (like UUID, ID, etc.). It returns 40620 on success, or a standard error code on failure. 4063 4064Function : is_plat_lfa_activation_pending() 4065~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4066 4067:: 4068 4069 Argument : uint32_t 4070 Return : bool 4071 4072This platform API checks if the specified LFA component, identified 4073by its ``lfa_component_id``, is available for activation. It returns 4074true if available, otherwise false. 4075 4076Function : plat_lfa_cancel() 4077~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4078 4079:: 4080 4081 Argument : uint32_t 4082 Return : int 4083 4084This platform API allows the platform to cancel an ongoing update or activation 4085process for the specified ``lfa_component_id``. It returns 0 on success or 4086a standard error code on failure. 4087 4088Function : plat_lfa_load_auth_image() 4089~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4090 4091:: 4092 4093 Argument : uint32_t 4094 Return : int 4095 4096The platform uses this API to load, authenticate and measure the component 4097specified by ``lfa_component_id``. It should return 0 on success or appropriate 4098error codes for load/authentication failures. 4099 4100NOTE: The error code -EAGAIN is not treated as an error, it means the operation 4101is incomplete and the function should be called again by the caller. 4102 4103Function : plat_lfa_notify_activate() 4104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4105 4106:: 4107 4108 Argument : uint32_t 4109 Return : int 4110 4111This API is invoked by the platform to notify its security engine to initiate 4112the required steps for component activation. The function takes the component 4113identifier ``lfa_component_id`` as an argument. It should return 0 on success 4114or appropriate negative error codes on failures. 4115 4116-------------- 4117 4118*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.* 4119 4120.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 4121.. _Arm Generic Interrupt Controller version 2.0 (GICv2): https://developer.arm.com/documentation/ihi0048/b/ 4122.. _3.0 (GICv3): https://developer.arm.com/documentation/ihi0069 4123.. _FreeBSD: https://www.freebsd.org 4124.. _SCC: http://www.simple-cc.org/ 4125.. _DRTM: https://developer.arm.com/documentation/den0113 4126