1Renesas R-Car 2============= 3 4"R-Car" is the nickname for Renesas' system-on-chip (SoC) family for 5car information systems designed for the next-generation of automotive 6computing for the age of autonomous vehicles. 7 8The scalable R-Car hardware platform and flexible software platform 9cover the full product range, from the premium class to the entry 10level. Plug-ins are available for multiple open-source software tools. 11 12 13Renesas R-Car Gen3 evaluation boards: 14------------------------------------- 15 16+------------+-----------------+-----------------------------+ 17| | Standard | Low Cost Boards (LCB) | 18+============+=================+=============================+ 19| R-Car H3 | - Salvator-X | - R-Car Starter Kit Premier | 20| | - Salvator-XS | | 21+------------+-----------------+-----------------------------+ 22| R-Car M3-W | - Salvator-X | | 23| | - Salvator-XS | - R-Car Starter Kit Pro | 24+------------+-----------------+-----------------------------+ 25| R-Car M3-N | - Salvator-X | | 26| | - Salvator-XS | | 27+------------+-----------------+-----------------------------+ 28| R-Car V3M | - Eagle | - Starter Kit | 29+------------+-----------------+-----------------------------+ 30| R-Car V3H | - Condor | - Starter Kit | 31+------------+-----------------+-----------------------------+ 32| R-Car D3 | - Draak | | 33+------------+-----------------+-----------------------------+ 34 35`boards info <https://elinux.org/R-Car>`__ 36 37The current TF-A port has been tested on the R-Car H3 Salvator-X 38Soc_id r8a7795 revision ES1.1 (uses a Secure Payload Dispatcher) 39 40 41:: 42 43 ARM CA57 (ARMv8) 1.5 GHz quad core, with NEON/VFPv4, L1$ I/D 44 48K/32K, L2$ 2MB 45 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, 46 L2$ 512K 47 Memory controller for LPDDR4-3200 4GB in 2 channels, each 64-bit wide 48 Two- and three-dimensional graphics engines, 49 Video processing units, 50 3 channels Display Output, 51 6 channels Video Input, 52 SD card host interface, 53 USB3.0 and USB2.0 interfaces, 54 CAN interfaces 55 Ethernet AVB 56 PCI Express Interfaces 57 Memories 58 INTERNAL 384KB SYSTEM RAM 59 DDR 4 GB LPDDR4 60 HYPERFLASH 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S) 61 QSPI FLASH 16MB QSPI (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI 62 MODULE 63 EMMC 32 GB EMMC (HS400 240 MBYTES/S) 64 MICROSD-CARD SLOT (SDR104 100 MBYTES/S) 65 66 67Overview 68-------- 69On the rcar-gen3 the BOOTROM starts the cpu at EL3; for this port BL2 70will therefore be entered at this exception level (the Renesas' ATF 71reference tree [1] resets into EL1 before entering BL2 - see its 72bl2.ld.S) 73 74BL2 initializes DDR (and on some platforms i2c to interface to the 75PMIC) before determining the boot reason (cold or warm). 76 77During suspend all CPUs are switched off and the DDR is put in backup 78mode (some kind of self-refresh mode). This means that BL2 is always 79entered in a cold boot scenario. 80 81Once BL2 boots, it determines the boot reason, writes it to shared 82memory (BOOT_KIND_BASE) together with the BL31 parameters 83(PARAMS_BASE) and jumps to BL31. 84 85To all effects, BL31 is as if it is being entered in reset mode since 86it still needs to initialize the rest of the cores; this is the reason 87behind using direct shared memory access to BOOT_KIND_BASE _and_ 88PARAMS_BASE instead of using registers to get to those locations (see 89el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use 90case). 91 92Depending on the boot reason BL31 initializes the rest of the cores: 93in case of suspend, it uses a MBOX memory region to recover the 94program counters. 95 96[1] https://github.com/renesas-rcar/arm-trusted-firmware 97 98 99How to build 100------------ 101 102The TF-A build options depend on the target board so you will have to 103refer to those specific instructions. What follows is customized to 104the H3 SiP Salvator-X development system used in this port. 105 106Build Tested: 107~~~~~~~~~~~~~ 108RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" 109 110$ make clean bl2 bl31 rcar_layout_tool PLAT=rcar ${RCAR_OPT} SPD=opteed 111 112System Tested: 113~~~~~~~~~~~~~~ 114* mbed_tls: 115 git@github.com:ARMmbed/mbedtls.git [devel] 116 117 commit 552754a6ee82bab25d1bdf28c8261a4518e65e4d 118 Merge: 68dbc94 f34a4c1 119 Author: Simon Butcher <simon.butcher@arm.com> 120 Date: Thu Aug 30 00:57:28 2018 +0100 121 122* optee_os: 123 https://github.com/BayLibre/optee_os 124 125 Until it gets merged into OP-TEE, the port requires Renesas' 126 Trusted Environment with a modification to support power 127 management. 128 commit 80105192cba9e704ebe8df7ab84095edc2922f84 129 130 Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> 131 Date: Thu Aug 30 16:49:49 2018 +0200 132 plat-rcar: cpu-suspend: handle the power level 133 Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> 134 135* u-boot: 136 The port has beent tested using mainline uboot. 137 138 commit 4cdeda511f8037015b568396e6dcc3d8fb41e8c0 139 Author: Fabio Estevam <festevam@gmail.com> 140 Date: Tue Sep 4 10:23:12 2018 -0300 141 142* linux: 143 The port has beent tested using mainline kernel. 144 145 commit 7876320f88802b22d4e2daf7eb027dd14175a0f8 146 Author: Linus Torvalds <torvalds@linux-foundation.org> 147 Date: Sun Sep 16 11:52:37 2018 -0700 148 Linux 4.19-rc4 149 150TF-A Build Procedure 151~~~~~~~~~~~~~~~~~~~~ 152 153- Fetch all the above 4 repositories. 154 155- Prepare the AARCH64 toolchain. 156 157- Build u-boot using r8a7795_salvator-x_defconfig. 158 Result: u-boot-elf.srec 159 160.. code:: bash 161 162 make CROSS_COMPILE=aarch64-linux-gnu- 163 r8a7795_salvator-x_defconfig 164 165 make CROSS_COMPILE=aarch64-linux-gnu- 166 167- Build atf 168 Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec 169 170.. code:: bash 171 172 RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" 173 174 make clean bl2 bl31 rcar PLAT=rcar ${RCAR_OPT} SPD=opteed 175 176- Build optee-os 177 Result: tee.srec 178 179.. code:: bash 180 181 make -j8 PLATFORM="rcar" CFG_ARM64_core=y 182 183Install Procedure 184~~~~~~~~~~~~~~~~~ 185 186- Boot the board in Mini-monitor mode and enable access to the 187 Hyperflash. 188 189 190- Use the XSL2 Mini-monitor utility to accept all the SREC ascii 191 transfers over serial. 192 193 194Boot trace 195---------- 196 197Notice that BL31 traces are not accessible via the console and that in 198order to verbose the BL2 output you will have to compile TF-A with 199LOG_LEVEL=50 and DEBUG=1 200 201:: 202 203 Initial Program Loader(CA57) Rev.1.0.22 204 NOTICE: BL2: PRR is R-Car H3 Ver.1.1 205 NOTICE: BL2: Board is Salvator-X Rev.1.0 206 NOTICE: BL2: Boot device is HyperFlash(80MHz) 207 NOTICE: BL2: LCM state is CM 208 NOTICE: AVS setting succeeded. DVFS_SetVID=0x53 209 NOTICE: BL2: DDR1600(rev.0.33)NOTICE: [COLD_BOOT]NOTICE: ..0 210 NOTICE: BL2: DRAM Split is 4ch 211 NOTICE: BL2: QoS is default setting(rev.0.37) 212 NOTICE: BL2: Lossy Decomp areas 213 NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570 214 NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0 215 NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0 216 NOTICE: BL2: v2.0(release):v2.0-rc0-32-gbcda69a 217 NOTICE: BL2: Built : 16:41:23, Oct 2 2018 218 NOTICE: BL2: Normal boot 219 INFO: BL2: Doing platform setup 220 INFO: BL2: Loading image id 3 221 NOTICE: BL2: dst=0xe6322000 src=0x8180000 len=512(0x200) 222 NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800) 223 WARNING: r-car ignoring the BL31 size from certificate,using 224 RCAR_TRUSTED_SRAM_SIZE instead 225 INFO: Loading image id=3 at address 0x44000000 226 NOTICE: rcar_file_len: len: 0x0003e000 227 NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000) 228 INFO: Image id=3 loaded: 0x44000000 - 0x4403e000 229 INFO: BL2: Loading image id 4 230 INFO: Loading image id=4 at address 0x44100000 231 NOTICE: rcar_file_len: len: 0x00100000 232 NOTICE: BL2: dst=0x44100000 src=0x8200000 len=1048576(0x100000) 233 INFO: Image id=4 loaded: 0x44100000 - 0x44200000 234 INFO: BL2: Loading image id 5 235 INFO: Loading image id=5 at address 0x50000000 236 NOTICE: rcar_file_len: len: 0x00100000 237 NOTICE: BL2: dst=0x50000000 src=0x8640000 len=1048576(0x100000) 238 INFO: Image id=5 loaded: 0x50000000 - 0x50100000 239 NOTICE: BL2: Booting BL31 240 INFO: Entry point address = 0x44000000 241 INFO: SPSR = 0x3cd 242 VERBOSE: Argument #0 = 0xe6325578 243 VERBOSE: Argument #1 = 0x0 244 VERBOSE: Argument #2 = 0x0 245 VERBOSE: Argument #3 = 0x0 246 VERBOSE: Argument #4 = 0x0 247 VERBOSE: Argument #5 = 0x0 248 VERBOSE: Argument #6 = 0x0 249 VERBOSE: Argument #7 = 0x0 250 251 252 U-Boot 2018.09-rc3-00028-g3711616 (Sep 27 2018 - 18:50:24 +0200) 253 254 CPU: Renesas Electronics R8A7795 rev 1.1 255 Model: Renesas Salvator-X board based on r8a7795 ES2.0+ 256 DRAM: 3.5 GiB 257 Flash: 64 MiB 258 MMC: sd@ee100000: 0, sd@ee140000: 1, sd@ee160000: 2 259 Loading Environment from MMC... OK 260 In: serial@e6e88000 261 Out: serial@e6e88000 262 Err: serial@e6e88000 263 Net: eth0: ethernet@e6800000 264 Hit any key to stop autoboot: 0 265 => 266