1NVIDIA Tegra 2============ 3 4- .. rubric:: T194 5 :name: t194 6 7T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor 8configuration. The Carmel cores support the ARM Architecture version 8.2, 9executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel 10processors are organized as four dual-core clusters, where each cluster has 11a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects 12these processor complexes and allows heterogeneous multi-processing with all 13eight cores if required. 14 15Directory structure 16------------------- 17 18- plat/nvidia/tegra/common - Common code for all Tegra SoCs 19- plat/nvidia/tegra/soc/txxx - Chip specific code 20 21Trusted OS dispatcher 22--------------------- 23 24Tegra supports multiple Trusted OS'. 25 26- Trusted Little Kernel (TLK): In order to include the 'tlkd' dispatcher in 27 the image, pass 'SPD=tlkd' on the command line while preparing a bl31 image. 28- Trusty: In order to include the 'trusty' dispatcher in the image, pass 29 'SPD=trusty' on the command line while preparing a bl31 image. 30 31This allows other Trusted OS vendors to use the upstream code and include 32their dispatchers in the image without changing any makefiles. 33 34These are the supported Trusted OS' by Tegra platforms. 35 36- Tegra194: Trusty 37 38Scatter files 39------------- 40 41Tegra platforms currently support scatter files and ld.S scripts. The scatter 42files help support ARMLINK linker to generate BL31 binaries. For now, there 43exists a common scatter file, plat/nvidia/tegra/scat/bl31.scat, for all Tegra 44SoCs. The `LINKER` build variable needs to point to the ARMLINK binary for 45the scatter file to be used. Tegra platforms have verified BL31 image generation 46with ARMCLANG (compilation) and ARMLINK (linking) for the Tegra186 platforms. 47 48Preparing the BL31 image to run on Tegra SoCs 49--------------------------------------------- 50 51.. code:: shell 52 53 CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ 54 TARGET_SOC=<target-soc e.g. t194> SPD=<dispatcher e.g. trusty|tlkd> 55 bl31 56 57Note that all Tegra platforms only support compiling with GCC or ARMCLANG. Clang 58is not supported. Images will compile with clang, but will not boot. 59 60Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` 61to the build command line. 62 63The Tegra platform code expects a pointer to the following platform specific 64structure via 'x1' register from the BL2 layer which is used by the 65bl31\_early\_platform\_setup() handler to extract the TZDRAM carveout base and 66size for loading the Trusted OS and the UART port ID to be used. The Tegra 67memory controller driver programs this base/size in order to restrict NS 68accesses. 69 70typedef struct plat\_params\_from\_bl2 { 71/\* TZ memory size */ 72uint64\_t tzdram\_size; 73/* TZ memory base */ 74uint64\_t tzdram\_base; 75/* UART port ID \*/ 76int uart\_id; 77/* L2 ECC parity protection disable flag \*/ 78int l2\_ecc\_parity\_prot\_dis; 79/* SHMEM base address for storing the boot logs \*/ 80uint64\_t boot\_profiler\_shmem\_base; 81} plat\_params\_from\_bl2\_t; 82 83Power Management 84---------------- 85 86The PSCI implementation expects each platform to expose the 'power state' 87parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field 88is implementation defined on Tegra SoCs and is preferably defined by 89tegra\_def.h. 90 91Tegra configs 92------------- 93 94- 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity 95 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will 96 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit. 97