1# 2# Copyright (c) 2016-2026, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Warning level to give to the compiler 14W := 0 15 16# Use T32 by default 17AARCH32_INSTRUCTION_SET := T32 18 19# The AArch32 Secure Payload to be built as BL32 image 20AARCH32_SP := none 21 22# The Target build architecture. Supported values are: aarch64, aarch32. 23ARCH := aarch64 24 25# ARM Architecture feature modifiers: none by default 26ARM_ARCH_FEATURE := none 27 28# ARM Architecture major and minor versions: 8.0 by default. 29ARM_ARCH_MAJOR := 8 30ARM_ARCH_MINOR := 0 31 32# Base commit to perform code check on 33BASE_COMMIT := origin/master 34 35# Execute BL2 at EL3 36RESET_TO_BL2 := 0 37 38# Only use SP packages if SP layout JSON is defined 39BL2_ENABLE_SP_LOAD := 0 40 41# BL2 image is stored in XIP memory, for now, this option is only supported 42# when RESET_TO_BL2 is 1. 43BL2_IN_XIP_MEM := 0 44 45# Do dcache invalidate upon BL2 entry at EL3 46BL2_INV_DCACHE := 1 47 48# Select the branch protection features to use. 49BRANCH_PROTECTION := 0 50 51# By default, consider that the platform may release several CPUs out of reset. 52# The platform Makefile is free to override this value. 53COLD_BOOT_SINGLE_CPU := 0 54 55# Flag to compile in coreboot support code. Exclude by default. The coreboot 56# Makefile system will set this when compiling TF as part of a coreboot image. 57COREBOOT := 0 58 59# For Chain of Trust 60CREATE_KEYS := 1 61 62# Build flag to include AArch32 registers in cpu context save and restore during 63# world switch. This flag must be set to 0 for AArch64-only platforms. 64CTX_INCLUDE_AARCH32_REGS := 1 65 66# Include FP registers in cpu context 67CTX_INCLUDE_FPREGS := 0 68 69# Include SVE registers in cpu context 70CTX_INCLUDE_SVE_REGS := 0 71 72# Debug build 73DEBUG := 0 74 75# By default disable authenticated decryption support. 76DECRYPTION_SUPPORT := none 77 78# Build platform 79DEFAULT_PLAT := fvp 80 81# Disable the generation of the binary image (ELF only). 82DISABLE_BIN_GENERATION := 0 83 84# Enable capability to disable authentication dynamically. Only meant for 85# development platforms. 86DYN_DISABLE_AUTH := 0 87 88# Enable the SIMD crypto extension feature. The flags suppose to be in 89# arch_features.mk but since mbedtls_common.mk is included before arch_features.mk, 90# so this flag has to be defined here. 91ENABLE_FEAT_CRYPTO := 0 92 93# Enable the SIMD SHA3 crypto extension feature. 94ENABLE_FEAT_CRYPTO_SHA3 := 0 95 96# Enable the Maximum Power Mitigation Mechanism on supporting cores. 97ENABLE_MPMM := 0 98 99# Flag to Enable Position Independant support (PIE) 100ENABLE_PIE := 0 101 102# Flag to enable Performance Measurement Framework 103ENABLE_PMF := 0 104 105# Flag to enable PSCI STATs functionality 106ENABLE_PSCI_STAT := 0 107 108# Flag to enable runtime instrumentation using PMF 109ENABLE_RUNTIME_INSTRUMENTATION := 0 110 111# Flag to enable stack corruption protection 112ENABLE_STACK_PROTECTOR := 0 113 114# Flag to enable exception handling in EL3 115EL3_EXCEPTION_HANDLING := 0 116 117# Flag to include all errata for all CPUs TF-A implements workarounds for 118# Its supposed to be used only for testing. 119ENABLE_ERRATA_ALL := 0 120 121# By default BL31 encryption disabled 122ENCRYPT_BL31 := 0 123 124# By default BL32 encryption disabled 125ENCRYPT_BL32 := 0 126 127# Default dummy firmware encryption key 128ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 129 130# Default dummy nonce for firmware encryption 131ENC_NONCE := 1234567890abcdef12345678 132 133# Build flag to treat usage of deprecated platform and framework APIs as error. 134ERROR_DEPRECATED := 0 135 136# Fault injection support 137FAULT_INJECTION_SUPPORT := 0 138 139# Flag to enable architectural features detection mechanism 140FEATURE_DETECTION := 0 141 142# Byte alignment that each component in FIP is aligned to 143FIP_ALIGN := 0 144 145# Default FIP file name 146FIP_NAME := fip.bin 147 148# Default FWU_FIP file name 149FWU_FIP_NAME := fwu_fip.bin 150 151# Default BL2 FIP file name 152BL2_FIP_NAME := bl2_fip.bin 153 154# By default firmware encryption with SSK 155FW_ENC_STATUS := 0 156 157# For Chain of Trust 158GENERATE_COT := 0 159 160# Default number of 512 blocks per bitlock 161RME_GPT_BITLOCK_BLOCK := 1 162 163# Default maximum size of GPT contiguous block 164RME_GPT_MAX_BLOCK := 512 165 166# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 167# default, they are for Secure EL1. 168GICV2_G0_FOR_EL3 := 0 169 170# Generic implementation of a GICvX driver 171USE_GIC_DRIVER := 0 172 173# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 174# by lower ELs. 175HANDLE_EA_EL3_FIRST_NS := 0 176 177# Enable Handoff protocol using transfer lists 178TRANSFER_LIST := 0 179 180# Enable HOB list to generate boot information 181HOB_LIST := 0 182 183# Enables support for the gcc compiler option "-mharden-sls=all". 184# By default, disables all SLS hardening. 185HARDEN_SLS := 0 186 187# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 188# The default value is sha256. 189HASH_ALG := sha256 190 191# Whether system coherency is managed in hardware, without explicit software 192# operations. 193HW_ASSISTED_COHERENCY := 0 194 195# Flag to enable trapping of implementation defined sytem registers 196IMPDEF_SYSREG_TRAP := 0 197 198# Set the default algorithm for the generation of Trusted Board Boot keys 199KEY_ALG := rsa 200 201# Set the default key size in case KEY_ALG is rsa 202ifeq ($(KEY_ALG),rsa) 203KEY_SIZE := 2048 204endif 205 206# Option to build TF with Measured Boot support 207MEASURED_BOOT := 0 208 209# Option to build TF with Discrete TPM support 210DISCRETE_TPM := 0 211 212# Option to enable the DICE Protection Environmnet as a Measured Boot backend 213DICE_PROTECTION_ENVIRONMENT :=0 214 215# NS timer register save and restore (deprecated) 216NS_TIMER_SWITCH := 0 217 218# Include lib/libc in the final image 219OVERRIDE_LIBC := 0 220 221# Build PL011 UART driver in minimal generic UART mode 222PL011_GENERIC_UART := 0 223 224# By default, consider that the platform's reset address is not programmable. 225# The platform Makefile is free to override this value. 226PROGRAMMABLE_RESET_ADDRESS := 0 227 228# Flag used to choose the power state format: Extended State-ID or Original 229PSCI_EXTENDED_STATE_ID := 0 230 231# Enable PSCI OS-initiated mode support 232PSCI_OS_INIT_MODE := 0 233 234# SMCCC_ARCH_FEATURE_AVAILABILITY support 235ARCH_FEATURE_AVAILABILITY := 0 236 237# By default, BL1 acts as the reset handler, not BL31 238RESET_TO_BL31 := 0 239 240# For Chain of Trust 241SAVE_KEYS := 0 242 243# Software Delegated Exception support 244SDEI_SUPPORT := 0 245 246# Number of UUIDs allowed for a physical partition 247SPMC_AT_EL3_PARTITION_MAX_UUIDS := 4 248 249# True Random Number firmware Interface support 250TRNG_SUPPORT := 0 251 252# Check to see if Errata ABI is supported 253ERRATA_ABI_SUPPORT := 0 254 255# Check to enable Errata ABI for platforms with non-arm interconnect 256ERRATA_NON_ARM_INTERCONNECT := 0 257 258# SMCCC PCI support 259SMC_PCI_SUPPORT := 0 260 261# Whether code and read-only data should be put on separate memory pages. The 262# platform Makefile is free to override this value. 263SEPARATE_CODE_AND_RODATA := 0 264 265# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 266# separate memory region, which may be discontiguous from the rest of BL31. 267SEPARATE_NOBITS_REGION := 0 268 269# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 270# region, platform Makefile is free to override this value. 271SEPARATE_BL2_NOLOAD_REGION := 0 272 273# Put RW DATA sections (.rwdata) in a separate memory region, which may be 274# discontiguous from the rest of BL31. 275SEPARATE_RWDATA_REGION := 0 276 277# Put SIMD context data structures in a separate memory region. Platforms 278# have the choice to put it outside of default BSS region of EL3 firmware. 279SEPARATE_SIMD_SECTION := 0 280 281# If the BL31 image initialisation code is recalimed after use for the secondary 282# cores stack 283RECLAIM_INIT_CODE := 0 284 285# SPD choice 286SPD := none 287 288# Enable the Management Mode (MM)-based Secure Partition Manager implementation 289SPM_MM := 0 290 291# Use the FF-A SPMC implementation in EL3. 292SPMC_AT_EL3 := 0 293 294# Enable SEL0 SP when SPMC is enabled at EL3 295SPMC_AT_EL3_SEL0_SP :=0 296 297# Use SPM at S-EL2 as a default config for SPMD 298SPMD_SPM_AT_SEL2 := 1 299 300# Flag to introduce an infinite loop in BL1 just before it exits into the next 301# image. This is meant to help debugging the post-BL2 phase. 302SPIN_ON_BL1_EXIT := 0 303 304# Flags to build TF with Trusted Boot support 305TRUSTED_BOARD_BOOT := 0 306 307# Build option to choose whether Trusted Firmware uses Coherent memory or not. 308USE_COHERENT_MEM := 1 309 310# Build option to add debugfs support 311USE_DEBUGFS := 0 312 313# Build option to enable passing the FDT in x0 to BL33, following the kernel 314# convention. 315USE_KERNEL_DT_CONVENTION := 0 316 317# Build option to fconf based io 318ARM_IO_IN_DTB := 0 319 320# Build option to support SDEI through fconf 321SDEI_IN_FCONF := 0 322 323# Build option to support Secure Interrupt descriptors through fconf 324SEC_INT_DESC_IN_FCONF := 0 325 326# Build option to choose whether Trusted Firmware uses library at ROM 327USE_ROMLIB := 0 328 329# Build option to choose whether the xlat tables of BL images can be read-only. 330# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 331# which is the per BL-image option that actually enables the read-only tables 332# API. The reason for having this additional option is to have a common high 333# level makefile where we can check for incompatible features/build options. 334ALLOW_RO_XLAT_TABLES := 0 335 336# Chain of trust. 337COT := tbbr 338 339# Use tbbr_oid.h instead of platform_oid.h 340USE_TBBR_DEFS := 1 341 342# Whether to enable D-Cache early during warm boot. This is usually 343# applicable for platforms wherein interconnect programming is not 344# required to enable cache coherency after warm reset (eg: single cluster 345# platforms). 346WARMBOOT_ENABLE_DCACHE_EARLY := 0 347 348# Default SVE vector length to maximum architected value 349SVE_VECTOR_LEN := 2048 350 351SANITIZE_UB := off 352 353# Enable Link Time Optimization 354ENABLE_LTO := 0 355 356# This option will include EL2 registers in cpu context save and restore during 357# EL2 firmware entry/exit. Internal flag not meant for direct setting. 358# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 359# CTX_INCLUDE_EL2_REGS. 360CTX_INCLUDE_EL2_REGS := 0 361 362# Select workaround for AT speculative behaviour. 363ERRATA_SPECULATIVE_AT := 0 364 365# select workaround for SME aborting powerdown 366ERRATA_SME_POWER_DOWN := 0 367 368# Trap RAS error record access from Non secure 369RAS_TRAP_NS_ERR_REC_ACCESS := 0 370 371# Build option to create cot descriptors using fconf 372COT_DESC_IN_DTB := 0 373 374# Build option to provide OpenSSL directory path 375OPENSSL_DIR := /usr 376 377# Select the openssl binary provided in OPENSSL_DIR variable 378ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 379 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 380else 381 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 382endif 383 384# Build option to use the SP804 timer instead of the generic one 385USE_SP804_TIMER := 0 386 387# Build option to define number of firmware banks, used in firmware update 388# metadata structure. 389NR_OF_FW_BANKS := 2 390 391# Build option to define number of images in firmware bank, used in firmware 392# update metadata structure. 393NR_OF_IMAGES_IN_FW_BANK := 1 394 395# Disable Firmware update support by default 396PSA_FWU_SUPPORT := 0 397 398# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 399# is enabled. 400ifeq ($(PSA_FWU_SUPPORT),1) 401PSA_FWU_METADATA_FW_STORE_DESC := 1 402else 403PSA_FWU_METADATA_FW_STORE_DESC := 0 404endif 405 406# Dynamic Root of Trust for Measurement support 407DRTM_SUPPORT := 0 408 409# Check platform if cache management operations should be performed. 410# Disabled by default. 411CONDITIONAL_CMO := 0 412 413# By default, disable SPMD Logical partitions 414ENABLE_SPMD_LP := 0 415 416# By default, disable PSA crypto (use MbedTLS legacy crypto API). 417PSA_CRYPTO := 0 418 419# getc() support from the console(s). 420# Disabled by default because it constitutes an attack vector into TF-A. It 421# should only be enabled if there is a use case for it. 422ENABLE_CONSOLE_GETC := 0 423 424# Build option to disable EL2 when it is not used. 425# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 426# functions must be enabled by platforms if they require it. 427# Disabled by default. 428INIT_UNUSED_NS_EL2 := 0 429 430# Disable including MPAM EL2 registers in context by default since currently 431# it's only enabled for NS world 432CTX_INCLUDE_MPAM_REGS := 0 433 434# Enable context memory usage reporting during BL31 setup. 435PLATFORM_REPORT_CTX_MEM_USE := 0 436 437# Request a custom addition to the BL31 linker script 438PLAT_EXTRA_LD_SCRIPT := 0 439 440# Enable early console 441EARLY_CONSOLE := 0 442 443# Allow platforms to save/restore DSU PMU registers over a power cycle. 444# Disabled by default and must be enabled by individual platforms. 445PRESERVE_DSU_PMU_REGS := 0 446 447# Enable RMMD to forward attestation requests from RMM to EL3. 448RMMD_ENABLE_EL3_TOKEN_SIGN := 0 449 450# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP). 451# This flag is temporary and it is expected once the interface is 452# finalized, this flag will be removed. 453RMMD_ENABLE_IDE_KEY_PROG := 0 454 455# Live firmware activation support 456LFA_SUPPORT := 0 457 458# Enable support for arm DSU driver. 459USE_DSU_DRIVER := 0 460 461# Define the separation of BL2 flag, by default it is disabled. 462SEPARATE_BL2_FIP := 0 463 464# Disable NUMA awareness for per-CPU framework by default. Platforms should 465# enable this feature by setting PLATFORM_NODE_COUNT > 1 466PLATFORM_NODE_COUNT := 1 467