1 /* Core header for MiraMEMS 3-Axis Accelerometer's driver. 2 * 3 * mir3da_core.h - Linux kernel modules for MiraMEMS 3-Axis Accelerometer 4 * 5 * Copyright (C) 2011-2013 MiraMEMS Sensing Technology Co., Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef __MIR3DA_CORE_H__ 19 #define __MIR3DA_CORE_H__ 20 21 #define CUST_VER "" /* for Custom debug version */ 22 #define CORE_VER "4.2.0_2018-08-10-14:56:30_"CUST_VER 23 24 #define MIR3DA_SUPPORT_CHIP_LIST MIR_NSA_NTO 25 26 #define MIR3DA_BUFSIZE 256 27 28 #define MIR3DA_STK_TEMP_SOLUTION 0 29 #define MIR3DA_OFFSET_TEMP_SOLUTION 0 30 #if MIR3DA_OFFSET_TEMP_SOLUTION 31 #define MIR3DA_AUTO_CALIBRATE 0 32 #else 33 #define MIR3DA_AUTO_CALIBRATE 0 34 #endif /* !MIR3DA_OFFSET_TEMP_SOLUTION */ 35 #if MIR3DA_AUTO_CALIBRATE 36 #define MIR3DA_SUPPORT_FAST_AUTO_CALI 0 37 #else 38 #define MIR3DA_SUPPORT_FAST_AUTO_CALI 0 39 #endif 40 #define MIR3DA_SENS_TEMP_SOLUTION 1 41 #define FILTER_AVERAGE_ENHANCE 0 42 #define FILTER_AVERAGE_EX 0 43 #define MIR3DA_SUPPORT_MULTI_LAYOUT 0 44 #define YZ_CROSS_TALK_ENABLE 1 45 46 #define MIR3DA_OFFSET_LEN 9 47 48 typedef void* MIR_HANDLE; 49 typedef void* PLAT_HANDLE; 50 51 52 struct serial_manage_if_s { 53 54 int (*read)(PLAT_HANDLE handle, unsigned char addr, unsigned char *data); 55 int (*write)(PLAT_HANDLE handle, unsigned char addr, unsigned char data); 56 int (*read_block)(PLAT_HANDLE handle, unsigned char base_addr, unsigned char count, unsigned char *data); 57 }; 58 59 struct general_op_s { 60 61 struct serial_manage_if_s smi; 62 63 int (*data_save)(unsigned char *data); 64 int (*data_get)(unsigned char *data); 65 int (*data_check)(void); 66 int (*get_address)(PLAT_HANDLE handle); 67 int (*support_fast_auto_cali)(void); 68 69 int (*myprintf)(const char *fmt, ...); 70 int (*mysprintf)(char *buf, const char *fmt, ...); 71 void (*msdelay)(int ms); 72 }; 73 74 #define MIR_GENERAL_OPS_DECLARE(OPS_HDL, SMI_RD, SMI_RDBL, SMI_WR, DAT_SAVE, DAT_GET,DAT_CHECK, GET_ADDRESS,SUPPORT_FAST_AUTO_CALI,MDELAY, MYPRINTF, MYSPRINTF) \ 75 \ 76 struct general_op_s OPS_HDL = { { SMI_RD, SMI_WR, SMI_RDBL }, DAT_SAVE, DAT_GET,DAT_CHECK,GET_ADDRESS, SUPPORT_FAST_AUTO_CALI,MYPRINTF, MYSPRINTF, MDELAY } 77 enum interrupt_src { 78 79 INTERRUPT_ACTIVITY = 1, 80 INTERRUPT_CLICK, 81 82 }; 83 84 typedef enum _int_op_type { 85 86 INTERRUPT_OP_INIT, 87 INTERRUPT_OP_ENABLE, 88 INTERRUPT_OP_CONFIG, 89 INTERRUPT_OP_DISABLE, 90 91 } mir_int_op_type; 92 93 enum interrupt_pin { 94 95 INTERRUPT_PIN1, 96 INTERRUPT_PIN2, 97 }; 98 99 enum pin_output_mode { 100 101 OUTPUT_MOD_PULL_PUSH, 102 OUTPUT_MOD_OD, 103 }; 104 105 struct int_act_cfg_s { 106 107 unsigned char threshold; 108 unsigned char duration; 109 }; 110 111 struct int_clk_cfg_s { 112 113 unsigned char threshold; 114 unsigned char click_time; /* click time */ 115 unsigned char quiet_time; /* quiet time after click */ 116 unsigned char window; /* for second click time window */ 117 }; 118 119 typedef union _int_src_configuration { 120 121 struct int_act_cfg_s act; 122 struct int_clk_cfg_s clk; 123 124 } mir_int_src_cfg_t; 125 126 typedef struct _int_configuration { 127 128 enum interrupt_pin pin; 129 enum interrupt_src int_src; 130 131 mir_int_src_cfg_t int_cfg; 132 133 } mir_int_cfg_t; 134 135 typedef struct _int_init_data { 136 137 enum pin_output_mode pin_mod; 138 139 unsigned char level; /* 1: high active, 0: low active */ 140 unsigned char latch; /* >0: latch time, 0: no latch */ 141 142 } mir_int_init_t ; 143 144 typedef union _int_op_data { 145 146 enum interrupt_src int_src; 147 mir_int_init_t init; 148 mir_int_cfg_t cfg; 149 150 } mir_int_op_data; 151 152 typedef struct _int_operations { 153 154 mir_int_op_type type; 155 mir_int_op_data data; 156 157 } mir_int_ops_t; 158 159 /* Register define for NSA asic */ 160 #define NSA_REG_SPI_I2C 0x00 161 #define NSA_REG_WHO_AM_I 0x01 162 #define NSA_REG_ACC_X_LSB 0x02 163 #define NSA_REG_ACC_X_MSB 0x03 164 #define NSA_REG_ACC_Y_LSB 0x04 165 #define NSA_REG_ACC_Y_MSB 0x05 166 #define NSA_REG_ACC_Z_LSB 0x06 167 #define NSA_REG_ACC_Z_MSB 0x07 168 #define NSA_REG_MOTION_FLAG 0x09 169 #define NSA_REG_STEPS_MSB 0x0D 170 #define NSA_REG_STEPS_LSB 0x0E 171 #define NSA_REG_G_RANGE 0x0F 172 #define NSA_REG_ODR_AXIS_DISABLE 0x10 173 #define NSA_REG_POWERMODE_BW 0x11 174 #define NSA_REG_SWAP_POLARITY 0x12 175 #define NSA_REG_FIFO_CTRL 0x14 176 #define NAS_REG_INT_SET0 0x15 177 #define NSA_REG_INTERRUPT_SETTINGS1 0x16 178 #define NSA_REG_INTERRUPT_SETTINGS2 0x17 179 #define NSA_REG_INTERRUPT_MAPPING1 0x19 180 #define NSA_REG_INTERRUPT_MAPPING2 0x1a 181 #define NSA_REG_INTERRUPT_MAPPING3 0x1b 182 #define NSA_REG_INT_PIN_CONFIG 0x20 183 #define NSA_REG_INT_LATCH 0x21 184 #define NSA_REG_ACTIVE_DURATION 0x27 185 #define NSA_REG_ACTIVE_THRESHOLD 0x28 186 #define NSA_REG_TAP_DURATION 0x2A 187 #define NSA_REG_TAP_THRESHOLD 0x2B 188 #define NSA_REG_STEP_CONFIG1 0x2F 189 #define NSA_REG_STEP_CONFIG2 0x30 190 #define NSA_REG_STEP_CONFIG3 0x31 191 #define NSA_REG_STEP_CONFIG4 0x32 192 #define NSA_REG_STEP_FILTER 0x33 193 #define NSA_REG_SM_THRESHOLD 0x34 194 #define NSA_REG_CUSTOM_OFFSET_X 0x38 195 #define NSA_REG_CUSTOM_OFFSET_Y 0x39 196 #define NSA_REG_CUSTOM_OFFSET_Z 0x3a 197 #define NSA_REG_ENGINEERING_MODE 0x7f 198 #define NSA_REG_SENSITIVITY_TRIM_X 0x80 199 #define NSA_REG_SENSITIVITY_TRIM_Y 0x81 200 #define NSA_REG_SENSITIVITY_TRIM_Z 0x82 201 #define NSA_REG_COARSE_OFFSET_TRIM_X 0x83 202 #define NSA_REG_COARSE_OFFSET_TRIM_Y 0x84 203 #define NSA_REG_COARSE_OFFSET_TRIM_Z 0x85 204 #define NSA_REG_FINE_OFFSET_TRIM_X 0x86 205 #define NSA_REG_FINE_OFFSET_TRIM_Y 0x87 206 #define NSA_REG_FINE_OFFSET_TRIM_Z 0x88 207 #define NSA_REG_SENS_COMP 0x8c 208 #define NSA_REG_MEMS_OPTION 0x8f 209 #define NSA_REG_CHIP_INFO 0xc0 210 #define NSA_REG_CHIP_INFO_SECOND 0xc1 211 #define NSA_REG_MEMS_OPTION_SECOND 0xc7 212 #define NSA_REG_SENS_COARSE_TRIM 0xd1 213 #define NAS_REG_OSC_TRIM 0x8e 214 215 #define MIR3DA_ODR_50HZ 0 216 #define MIR3DA_ODR_100HZ 1 217 #define MIR3DA_ODR_200HZ 2 218 219 #define MI_TAG "[MIR3DA] " 220 enum{ 221 DEBUG_ERR=1, 222 DEBUG_ASSERT=1<<1, 223 DEBUG_MSG=1<<2, 224 DEBUG_FUNC=1<<3, 225 DEBUG_DATA=1<<4, 226 }; 227 228 extern int mir3da_Log_level; 229 230 /* register operation */ 231 int mir3da_register_read(MIR_HANDLE handle, short reg, unsigned char *data); 232 int mir3da_register_write(MIR_HANDLE handle, short reg, unsigned char data); 233 int mir3da_register_read_continuously(MIR_HANDLE handle, short base_reg, unsigned char count, unsigned char *data); 234 int mir3da_register_mask_write(MIR_HANDLE handle, short addr, unsigned char mask, unsigned char data); 235 236 int mir3da_install_general_ops(struct general_op_s *ops); 237 /* chip init */ 238 MIR_HANDLE mir3da_core_init(PLAT_HANDLE handle); 239 240 /* data polling */ 241 int mir3da_read_data(MIR_HANDLE handle, short *x, short *y, short *z); 242 243 /* filter configure */ 244 #if FILTER_AVERAGE_ENHANCE 245 struct mir3da_filter_param_s{ 246 int filter_param_l; 247 int filter_param_h; 248 int filter_threhold; 249 }; 250 251 int mir3da_get_filter_param(struct mir3da_filter_param_s* param); 252 int mir3da_set_filter_param(struct mir3da_filter_param_s* param); 253 #endif 254 255 #if MIR3DA_STK_TEMP_SOLUTION 256 #endif 257 258 enum { 259 GSENSOR_MOD_NSA_NTO=0, 260 }; 261 262 /* CALI */ 263 int mir3da_calibrate(MIR_HANDLE handle, int z_dir); 264 265 /* calibration */ 266 #if MIR3DA_OFFSET_TEMP_SOLUTION 267 enum file_check_statu { 268 FILE_NO_EXIST , 269 FILE_CHECKING , 270 FILE_EXIST, 271 }; 272 #endif 273 274 /* Interrupt operations */ 275 int mir3da_interrupt_ops(MIR_HANDLE handle, mir_int_ops_t *ops); 276 277 int mir3da_read_offset(MIR_HANDLE handle, unsigned char* offst); 278 int mir3da_write_offset(MIR_HANDLE handle, unsigned char* offset); 279 280 int mir3da_set_enable(MIR_HANDLE handle, char bEnable); 281 int mir3da_get_enable(MIR_HANDLE handle, char *bEnable); 282 int mir3da_get_reg_data(MIR_HANDLE handle, char *buf); 283 int mir3da_set_odr(MIR_HANDLE handle, int delay); 284 int mir3da_direction_remap(short *x,short *y, short *z, int direction); 285 286 int mir3da_chip_resume(MIR_HANDLE handle); 287 int mir3da_get_primary_offset(MIR_HANDLE handle,int *x,int *y,int *z); 288 289 int mir3da_read_step(MIR_HANDLE handle, unsigned short *count); 290 int mir3da_step_count_init(MIR_HANDLE handle); 291 int mir3da_irq_init(MIR_HANDLE handle); 292 int mir3da_step_count_init(MIR_HANDLE handle); 293 int mir3da_get_step_enable(MIR_HANDLE handle, char *enable); 294 int mir3da_set_step_enable(MIR_HANDLE handle, char enable); 295 int mir3da_get_sm_enable(MIR_HANDLE handle, char *enable); 296 int mir3da_set_sm_enable(MIR_HANDLE handle, char enable); 297 int mir3da_get_tilt_enable(MIR_HANDLE handle, char *enable); 298 int mir3da_set_tilt_enable(MIR_HANDLE handle, char enable); 299 300 301 #endif /* __MIR3DA_CORE_H__ */ 302 303 304