1 /* 2 * Chip-specific hardware definitions for 3 * Broadcom 802.11abg Networking Device Driver 4 * 5 * Broadcom Proprietary and Confidential. Copyright (C) 2020, 6 * All Rights Reserved. 7 * 8 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom; 9 * the contents of this file may not be disclosed to third parties, 10 * copied or duplicated in any form, in whole or in part, without 11 * the prior written permission of Broadcom. 12 * 13 * 14 * <<Broadcom-WL-IPTag/Proprietary:>> 15 */ 16 17 #ifndef _D11REGS_H 18 #define _D11REGS_H 19 20 #include <typedefs.h> 21 #include <sbhndpio.h> 22 #include <sbhnddma.h> 23 #include <sbconfig.h> 24 25 #if !defined(BCMDONGLEHOST) 26 #include <dot11mac_all_regs.h> 27 #include <d11regs_comp.h> 28 #endif 29 30 #if defined(BCMDONGLEHOST) || defined(WL_UNITTEST) 31 typedef struct { 32 uint32 pad; 33 } d11regdefs_t; 34 35 typedef volatile uint8 d11regs_t; 36 typedef struct _d11regs_info { 37 uint32 pad; 38 } d11regs_info_t; 39 40 #else /* defined(BCMDONGLEHOST) || defined(WL_UNITTEST) */ 41 42 typedef volatile struct d11regs d11regs_t; 43 44 typedef struct _d11regs_info { 45 d11regs_t *regs; 46 } d11regs_info_t; 47 48 #endif /* !defined(BCMDONGLEHOST) || !defined(WL_UNITTEST) */ 49 50 typedef volatile struct { 51 uint32 intstatus; 52 uint32 intmask; 53 } intctrlregs_t; 54 55 /** 56 * read: 32-bit register that can be read as 32-bit or as 2 16-bit 57 * write: only low 16b-it half can be written 58 */ 59 typedef volatile union { 60 uint32 pmqhostdata; /**< read only! */ 61 struct { 62 uint16 pmqctrlstatus; /**< read/write */ 63 uint16 PAD; 64 } w; 65 } pmqreg_t; 66 67 /** dma corerev >= 11 */ 68 typedef volatile struct { 69 dma64regs_t dmaxmt; /* dma tx */ 70 pio4regs_t piotx; /* pio tx */ 71 dma64regs_t dmarcv; /* dma rx */ 72 pio4regs_t piorx; /* pio rx */ 73 } fifo64_t; 74 75 /** indirect dma corerev >= 64 */ 76 typedef volatile struct { 77 dma64regs_t dma; /**< dma tx */ 78 uint32 indintstatus; 79 uint32 indintmask; 80 } ind_dma_t; 81 82 /** indirect dma corerev 80, 81, 82 */ 83 typedef volatile struct { 84 uint32 indintstatus; 85 uint32 indintmask; 86 dma64regs_t dma; /**< dma tx, */ 87 } ind_dma_axc_t; 88 89 /* access to register offsets and fields defined in dot11mac_all_regs.h */ 90 91 #define D11_REG_OFF(regname) \ 92 dot11mac_##regname##_ADDR 93 #define D11_REG_FIELD_MASK(regname, regfield) \ 94 dot11mac_##regname##__##regfield##_MASK 95 #define D11_REG_FIELD_SHIFT(regname, regfield) \ 96 dot11mac_##regname##__##regfield##_SHIFT 97 98 /* convert register offset to backplane address */ 99 100 #ifndef D11_REG_ADDR_CHK 101 // #define D11_REG_ADDR_CHK 102 #endif 103 104 #ifdef D11_REG_ADDR_CHK 105 #define D11_REG_ADDR_EXEMPT(regname) \ 106 (D11_REG_OFF(regname) == D11_REG_OFF(PHY_REG_ADDR) || \ 107 D11_REG_OFF(regname) == D11_REG_OFF(radioregaddr) || \ 108 D11_REG_OFF(regname) == D11_REG_OFF(radioregdata) || \ 109 D11_REG_OFF(regname) == D11_REG_OFF(OBJ_DATA) || \ 110 0) 111 #define D11_REG32_ADDR(regbase, regname) \ 112 ({ \ 113 STATIC_ASSERT(D11_REG_ADDR_EXEMPT(regname) || D11_REG_OFF(regname) < 0x3e0); \ 114 (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname)); \ 115 }) 116 #define D11_REG16_ADDR(regbase, regname) \ 117 ({ \ 118 STATIC_ASSERT(D11_REG_ADDR_EXEMPT(regname) || D11_REG_OFF(regname) >= 0x3e0); \ 119 (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname)); \ 120 }) 121 #else /* !D11_REG_ADDR_CHK */ 122 #define D11_REG32_ADDR(regbase, regname) \ 123 (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname)) 124 #define D11_REG16_ADDR(regbase, regname) \ 125 (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname)) 126 #endif /* !D11_REG_ADDR_CHK */ 127 128 /* used in table */ 129 #define D11_REG32_ADDR_ENTRY(regbase, regname) \ 130 (volatile uint32 *)((uintptr)(regbase) + D11_REG_OFF(regname)) 131 #define D11_REG16_ADDR_ENTRY(regbase, regname) \ 132 (volatile uint16 *)((uintptr)(regbase) + D11_REG_OFF(regname)) 133 134 #ifndef D11_NEW_ACCESS_MACROS 135 /* MOVED TO src/wl/sys/wlc_hw_priv.h */ 136 #define GET_MACINTSTATUS(osh, hw) R_REG((osh), D11_MACINTSTATUS(hw)) 137 #define SET_MACINTSTATUS(osh, hw, val) W_REG((osh), D11_MACINTSTATUS(hw), (val)) 138 #define GET_MACINTMASK(osh, hw) R_REG((osh), D11_MACINTMASK(hw)) 139 #define SET_MACINTMASK(osh, hw, val) W_REG((osh), D11_MACINTMASK(hw), (val)) 140 141 #define GET_MACINTSTATUS_X(osh, hw) R_REG((osh), D11_MACINTSTATUS_psmx(hw)) 142 #define SET_MACINTSTATUS_X(osh, hw, val) W_REG((osh), D11_MACINTSTATUS_psmx(hw), (val)) 143 #define GET_MACINTMASK_X(osh, hw) R_REG((osh), D11_MACINTMASK_psmx(hw)) 144 #define SET_MACINTMASK_X(osh, hw, val) W_REG((osh), D11_MACINTMASK_psmx(hw), (val)) 145 146 #define GET_MACINTSTATUS_EXT(osh, hw) R_REG((osh), D11_MACINTSTATUS_EXT(hw)) 147 #define SET_MACINTSTATUS_EXT(osh, hw, val) W_REG((osh), D11_MACINTSTATUS_EXT(hw), (val)) 148 #define GET_MACINTMASK_EXT(osh, hw) R_REG((osh), D11_MACINTMASK_EXT(hw)) 149 #define SET_MACINTMASK_EXT(osh, hw, val) W_REG((osh), D11_MACINTMASK_EXT(hw), (val)) 150 151 #define GET_MACINTSTATUS_EXT_X(osh, hw) R_REG((osh), D11_MACINTSTATUS_EXT_psmx(hw)) 152 #define SET_MACINTSTATUS_EXT_X(osh, hw, val) W_REG((osh), D11_MACINTSTATUS_EXT_psmx(hw), (val)) 153 #define GET_MACINTMASK_EXT_X(osh, hw) R_REG((osh), D11_MACINTMASK_EXT_psmx(hw)) 154 #define SET_MACINTMASK_EXT_X(osh, hw, val) W_REG((osh), D11_MACINTMASK_EXT_psmx(hw), (val)) 155 156 #define D11Reggrp_intctrlregs(hw, ix) ((intctrlregs_t*)(((volatile uint8*)D11_intstat0(hw)) + \ 157 (sizeof(intctrlregs_t)*ix))) 158 #define D11Reggrp_inddma(hw, ix) (D11REV_GE(hw->corerev, 86) ? \ 159 ((ind_dma_t*)(((volatile uint8*)D11_ind_xmt_control(hw)) + (sizeof(ind_dma_t)*ix))) : \ 160 ((ind_dma_t*)(((volatile uint8*)D11_inddma(hw)) + (sizeof(ind_dma_t)*ix)))) 161 #define D11Reggrp_inddma_axc(hw, ix) ((ind_dma_axc_t*)(((volatile uint8*)D11_inddma(hw)) + \ 162 (sizeof(ind_dma_axc_t)*ix))) 163 #define D11Reggrp_indaqm(hw, ix) (D11REV_GE(hw->corerev, 86) ? \ 164 ((ind_dma_t*)(((volatile uint8*)D11_IndAQMctl(hw)) + (sizeof(ind_dma_t)*ix))) : \ 165 ((ind_dma_t*)(((volatile uint8*)D11_indaqm(hw)) + (sizeof(ind_dma_t)*ix)))) 166 #define D11Reggrp_pmqreg(hw, ix) ((pmqreg_t*)(((volatile uint8*)D11_PMQHOSTDATA(hw)) + \ 167 (sizeof(pmqreg_t)*ix))) 168 #define D11Reggrp_f64regs(hw, ix) ((fifo64_t*)(((volatile uint8*)D11_xmt0ctl(hw)) + \ 169 (sizeof(fifo64_t)*ix))) 170 #define D11Reggrp_dmafifo(hw, ix) ((dma32diag_t*)(((volatile uint8*)D11_fifobase(hw)) + \ 171 (sizeof(dma32diag_t)*ix))) 172 #define D11Reggrp_intrcvlazy(hw, ix) ((volatile uint32*)(((volatile uint8*)D11_intrcvlzy0(hw)) + \ 173 (sizeof(uint32)*ix))) 174 #define D11Reggrp_altintmask(hw, ix) ((volatile uint32*)(((volatile uint8*)D11_alt_intmask0(hw)) + \ 175 (sizeof(uint32)*ix))) 176 #define D11REG_ISVALID(ptr, addr) ((volatile uint16 *)(addr) != \ 177 ((volatile uint16 *) &((ptr)->regs->INVALID_ID))) 178 #endif /* D11_NEW_ACCESS_MACROS */ 179 180 #endif /* _D11REGS_H */ 181