1 /* 2 * Driver for CX2081X voice capture IC. 3 * 4 * Copyright: Conexant Systems. 5 * 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 */ 12 13 #ifndef CX20810_CONFIG_H_ 14 #define CX20810_CONFIG_H_ 15 16 enum { 17 CX20810_NORMAL_MODE = 0, 18 CX20810_NORMAL_MODE2, 19 CX20810_NORMAL_MODE_SIMPLE, 20 CX20810_NIRMAL_MODE_CODEC3, 21 CX20810_NIRMAL_MODE_CODEC3_SIMPLE, 22 CX20810_96K_16BIT_MODE, 23 CX20810_48K_16BIT_MODE, 24 }; 25 26 static char codec_config_param_normal_mode[] = { 27 /* 28 * I2S Master mode, LeftJustified 1bit delay 29 * 48k_24bit MSB first, Frame Length 64bit 30 * 12.288Mhz MClk, bclk,48K* 64 , 3.072Mhz 31 * set up PLL, 12.288 Mhz mclk feed to PLL 32 */ 33 #if 1 34 0x80, 0x03, /* MCLK is an input */ 35 0x08, 0x20, /* MCLK !gated */ 36 0x60, 0x04, /* Bypass PLL */ 37 0x09, 0x03, /* Use MLCK directly */ 38 /* end pll setting */ 39 0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */ 40 0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */ 41 0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */ 42 0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */ 43 0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */ 44 0x78, 0x2D, /* Enable VREF @ 2.8V (5V) or 2.6V (3.3V) */ 45 0x78, 0x6D, /* Enable Analog LDO */ 46 0x78, 0x6D, /* Enable Analog LDO */ 47 0x78, 0x6D, /* Enable Analog LDO */ 48 0x78, 0x6D, /* Enable Analog LDO */ 49 0x78, 0x6D, /* Enable Analog LDO */ 50 0x78, 0x6D, /* Enable Analog LDO */ 51 0x7A, 0x01, /* Enable VREFP */ 52 53 /* Setup I2S */ 54 0x16, 0x00, /* Use DC Filters for ADCs */ 55 0x0c, 0x3B, /* Enable I2S-TX and set Master Mode, enable ADC3/4 FIFO */ 56 0x83, 0x00, /* Configure LRCK and BCLK as outputs */ 57 58 0x30, 0x14, /* 7 wire mode,24-bit sample size,// Normal mode */ 59 0x31, 0x07, /* Set 64 cycle per frame TX */ 60 0x33, 0x1F, /* TX WS ,32 cycle */ 61 0x35, 0xA8, /* Lj 1bit delay, enable TX1,2 */ 62 63 0x0A, 0x03, /* Set TX divisor is Source Clock / 4 (Bclk,3.072Mhz) */ 64 0x0A, 0x83, /* Enable divisor */ 65 66 /* Setup ADCs and clocks */ 67 68 /* 69 * if using 20/16/12/8/4 dB gain, set register 70 * 0x28/0x20/0x18/0x10/0x08 71 */ 72 0xBC, 0x28, /* ADC1 8dB Gain */ 73 0xBD, 0x28, /* ADC2 8dB Gain */ 74 0xBE, 0x28, /* ADC3 8dB Gain */ 75 0xBF, 0x28, /* ADC4 8dB Gain */ 76 77 0x10, 0x00, /* Disable all ADC clocks */ 78 0x11, 0x00, /* Disable all ADC clocks and Mixer */ 79 0x10, 0x1F, /* Enable all ADC clocks and ADC digital */ 80 0x11, 0x4F, /* Enable all ADCs and set 48kHz sample rate */ 81 0x10, 0x5F, /* Enable all ADC clocks, ADC digital and ADC Mic Clock Gate */ 82 83 /* 84 *0xA0 , 0x0F ,// ADC1, Mute PGA, enable AAF/ADC/PGA 85 *0xA7 , 0x0F ,// ADC2, Mute PGA, enable AAF/ADC/PGA 86 *0xAE , 0x0F ,// ADC3, Mute PGA, enable AAF/ADC/PGA 87 *0xB5 , 0x0F ,// ADC4, Mute PGA, enable AAF/ADC/PGA 88 */ 89 90 0xA0, 0x07, /* ADC1 !Mute */ 91 0xA7, 0x07, /* ADC2 !Mute */ 92 0xAE, 0x07, /* ADC3 !Mute */ 93 0xB5, 0x07, /* ADC4 !Mute */ 94 #else 95 /* I2S slave mode */ 96 0x0F, 0x03, /* RST */ 97 0x0F, 0x03, /* repeat write is let chip has more time to RST */ 98 0x0F, 0x03, 99 0x0F, 0x03, 100 101 0x0F, 0x00, /* release reset */ 102 103 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 104 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 105 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 106 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 107 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 108 109 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 110 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 111 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 112 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 113 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 114 115 0x7A, 0x01, 116 0x01, 0x01, 117 118 0xA0, 0x07, /* ADC bias EN */ 119 0xA7, 0x07, 120 0xAE, 0x07, 121 0xB5, 0x07, 122 123 0xBC, 0x3C, /* 0x28 20dB 0x34 26dB */ 124 0xBD, 0x3C, 125 0xBE, 0x3C, 126 0xBF, 0x3C, 127 128 0x30, 0x14, /* 14 24bit 0a 16bit */ 129 0x31, 0x07, /* frame (n+1)*8 bit 32+32=64 */ 130 0x32, 0x07, /* */ 131 0x33, 0x1F, /* sys width 32 clk */ 132 0x34, 0x1F, 133 0x35, 0xAC, /* TX right justified and revert i2s1+i2s2 */ 134 0x36, 0x00, /* config for right justified ignored. */ 135 0x37, 0x00, /* RX left justified. */ 136 0x38, 0x00, /* config for right justified ignored. */ 137 0x39, 0x08, /* ADC12 0n DATA1.ADC34 On DATA2 */ 138 0x3A, 0x00, /* Slot1 */ 139 0x3B, 0x00, /* slot2 */ 140 0x3C, 0x00, /* slot3 */ 141 0x3D, 0x00, /* slot4 */ 142 0x3E, 0x1F, /* slot4 */ 143 144 0x16, 0x00, /* Use DC Filter for ADCs */ 145 146 0x80, 0x03, /* MCLK */ 147 0x81, 0x01, /* LRCLK BCLK RX Pull down */ 148 0x82, 0x3F, /* LRCLK BCLK RX */ 149 0x83, 0x0F, /* LRCLK BCLK */ 150 151 0x0F, 0x01, /* RST,clears DSP,audio data interface values */ 152 0x0F, 0x01, /* repeat write is let chip has more time to RST */ 153 0x0F, 0x01, 154 0x0F, 0x01, 155 156 0x08, 0x00, /* disable MCLK to chip */ 157 0x0C, 0x0A, /* Clocks gated */ 158 0x09, 0x02, 159 160 0x0F, 0x00, /* clear RST */ 161 /* enable MCLK to chip */ 162 /* 0x08, 0x30, */ 163 /* 0x08, 0x38, */ 164 0x08, 0x20, 165 0x09, 0x03, 166 167 0x10, 0x00, /* Disable all ADC clocks */ 168 0x11, 0x10, /* Disable all ADC and Mixer */ 169 0x10, 0x1F, /* Enable all ADC clocks and ADC digital */ 170 0x11, 0x4F, /* Enable all ADC and set 48k sample rate */ 171 0x10, 0x5F, /* Enable all ADC clocks, 172 ADC digital and ADC Mic Clock Gate */ 173 #endif 174 }; 175 176 static char codec_config_param_normal_mode2[] = { 177 0x0F, 0x03, /* RST */ 178 0x0F, 0x03, /* repeat write is let chip has more time to RST */ 179 0x0F, 0x03, 180 0x0F, 0x03, 181 182 0x0F, 0x00, /* release reset */ 183 184 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 185 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 186 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 187 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 188 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 189 190 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 191 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 192 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 193 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 194 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 195 196 0x7A, 0x01, 197 0x01, 0x01, 198 199 0xA0, 0x07, /* ADC bias EN */ 200 0xA7, 0x07, 201 0xAE, 0x07, 202 0xB5, 0x07, 203 204 0xBC, 0x24, /* 0x28 20dB 0x34 26dB */ 205 0xBD, 0x24, 206 0xBE, 0x24, 207 0xBF, 0x24, 208 209 0x30, 0x14, /* 14 24bit 0a 16bit */ 210 0x31, 0x07, /* frame (n+1)*8 bit 32+32=64 */ 211 0x32, 0x07, /* */ 212 0x33, 0x1F, /* sys width 32 clk */ 213 0x34, 0x1F, 214 0x35, 0xAC, /* TX right justified and revert i2s1+i2s2 */ 215 0x36, 0x00, /* config for right justified ignored. */ 216 0x37, 0x00, /* RX left justified. */ 217 0x38, 0x00, /* config for right justified ignored. */ 218 0x39, 0x08, /* ADC12 0n DATA1.ADC34 On DATA2 */ 219 0x3A, 0x00, /* Slot1 */ 220 0x3B, 0x00, /* slot2 */ 221 0x3C, 0x00, /* slot3 */ 222 0x3D, 0x00, /* slot4 */ 223 0x3E, 0x1F, /* slot4 */ 224 225 0x16, 0x00, /* Use DC Filter for ADCs */ 226 227 0x80, 0x03, /* MCLK */ 228 0x81, 0x01, /* LRCLK BCLK RX Pull down */ 229 0x82, 0x3F, /* LRCLK BCLK RX */ 230 0x83, 0x0F, /* LRCLK BCLK */ 231 232 #if 0 233 /* PLL config */ 234 235 0x08, 0x00, /* disable MCLK */ 236 237 0x09, 0x40, /* I2S TX Bit Clock */ 238 239 0x60, 0xF8, /* reset and Disable PLL1 */ 240 241 0x61, 0xDF, /* */ 242 0x62, 0x01, 243 0x63, 0x01, 244 /* {0x64, 0x90}, */ 245 /* {0x65, 0x24}, */ 246 0x66, 0x80, 247 0x67, 0x02, 248 /* {0x68, 0x0}, */ 249 /* {0x69, 0x0}, */ 250 251 /* enable PLL1 */ 252 0x60, 0xFB, /* delay for PLL locked */ 253 0x60, 0xFB, 254 0x60, 0xFB, 255 0x60, 0xFB, 256 0x60, 0xFB, 257 0x60, 0xFB, 258 259 /* end PLL config */ 260 #endif 261 262 0x0F, 0x01, /* RST,clears DSP,audio data interface values */ 263 0x0F, 0x01, /* repeat write is let chip has more time to RST */ 264 0x0F, 0x01, 265 0x0F, 0x01, 266 267 0x08, 0x00, /* disable MCLK to chip */ 268 0x0C, 0x0A, /* Clocks gated */ 269 0x09, 0x02, 270 271 0x0F, 0x00, /* clear RST */ 272 /* 0x08, 0x30, */ 273 /* enable MCLK to chip */ 274 /* 0x08, 0x38, */ 275 0x08, 0x20, 276 0x09, 0x03, 277 278 0x10, 0x00, /* Disable all ADC clocks */ 279 0x11, 0x10, /* Disable all ADC and Mixer */ 280 0x10, 0x1F, /* Enable all ADC clocks and ADC digital */ 281 0x11, 0x4F, /* Enable all ADC and set 48k sample rate */ 282 0x10, 0x5F, /* Enable all ADC clocks, 283 ADC digital and ADC Mic Clock Gate */ 284 285 }; 286 287 static char codec_config_param_normal_mode_simple[] = { 288 /* mic pga 增益 */ 289 /* 4通道录音工具 */ 290 0xBC, 0x28, /* 0x28 20dB 0x34 26dB */ 291 0xBD, 0x28, 292 0xBE, 0x28, 293 0xBF, 0x28, 294 295 0x60, 0x04, 296 0x66, 0x00, 297 0x67, 0x02, 298 299 /* PAD配置 */ 300 0x80, 0x03, /* MCLK 为输入 */ 301 0x83, 0x0F, /* LRCLK BCLK 为输入脚，TX1 TX2为输出脚 */ 302 303 /* MCLK 作为输入 */ 304 /* 0x08, 0x30, */ 305 /* MCLK divisor 生效 */ 306 /* 0x08, 0x38, */ 307 0x08, 0x20, /* MCLK 作为输入 12.288MHz */ 308 0x09, 0x03, /* 选MCLK作为PLL输入源 */ 309 0x0a, 0x0b, 310 0x0a, 0x8b, 311 0x0C, 0x0A, /* RT clock disable, TX clock enable, 312 enable clock to ADC3/4 */ 313 314 /* I2S */ 315 /* Tx sample size:16bit, Normal mode */ 316 /* 0x30, 0x0A, */ 317 0x30, 0x14, /* Tx sample size:24bit, Normal mode */ 318 0x35, 0xA2, /* left justified, enable I2S-1 and I2S-2 */ 319 320 0x10, 0x00, 321 0x11, 0x00, 322 0x10, 0x1F, 323 0x11, 0x1F, /* ADC 96k, enables all ADCs */ 324 0x16, 0x00, 325 0x10, 0x5F, 326 327 }; 328 329 static char codec3_config_param_normal_mode[] = { 330 /* POWER */ 331 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 332 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 333 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 334 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 335 0x78, 0x39, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 336 337 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 338 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 339 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 340 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 341 0x78, 0x79, /* PLLEN = 1 ABIASEN IOBUFEN REFIMP = 11 3KR */ 342 343 0x7A, 0x01, 344 0x01, 0x01, 345 346 /* Analog ADC Control */ 347 /* MIcIn PGA A0,A7,AE,B5 [5:4] ctrl_rcm, 348 * [1] enable [3] mute [7] bypass */ 349 /* 模拟部分电源 */ 350 0xA0, 0x07, /* ADC bias EN */ 351 0xA7, 0x07, 352 0xAE, 0x07, 353 0xB5, 0x07, 354 355 /* mic pga 增益 */ 356 /* 4通道录音工具 */ 357 0xBC, 0x06, /* 0x28 20dB 0x34 26dB */ 358 0xBD, 0x06, 359 0xBE, 0x0C, 360 0xBF, 0x14, 361 362 0x60, 0x04, 363 0x66, 0x00, 364 0x67, 0x02, 365 366 /* PAD配置 */ 367 0x80, 0x03, /* MCLK 为输入 */ 368 0x83, 0x0F, /* LRCLK BCLK 为输入脚，TX1 TX2为输出脚 */ 369 370 /* MCLK 作为输入 */ 371 /* 0x08, 0x30, */ 372 /* MCLK divisor 生效 */ 373 /* 0x08, 0x38, */ 374 0x08, 0x20, /* MCLK 作为输入 12.288MHz */ 375 0x09, 0x03, /* 选MCLK作为PLL输入源 */ 376 0x0a, 0x0b, 377 0x0a, 0x8b, 378 0x0C, 0x0A, /* RT clock disable, TX clock enable, 379 enable clock to ADC3/4 */ 380 381 /* I2S */ 382 /* Tx sample size:16bit, Normal mode */ 383 /* 0x30, 0x0A, */ 384 0x30, 0x14, /* Tx sample size:24bit, Normal mode */ 385 0x35, 0xA2, /* left justified, enable I2S-1 and I2S-2 */ 386 387 0x10, 0x00, 388 0x11, 0x00, 389 0x10, 0x1F, 390 0x11, 0x1F, /* ADC 96k, enables all ADCs */ 391 0x16, 0x00, 392 0x10, 0x5F, 393 394 }; 395 396 static char codec3_config_param_normal_mode_simple[] = { 397 /* mic pga 增益 */ 398 /* 4通道录音工具 */ 399 0xBC, 0x28,/* 0x28 20dB 0x34 26dB */ 400 0xBD, 0x28, 401 0xBE, 0x28, 402 0xBF, 0x28, 403 404 0x60, 0x04, 405 0x66, 0x00, 406 0x67, 0x02, 407 408 /* PAD配置 */ 409 0x80, 0x03,/* MCLK 为输入 */ 410 0x83, 0x0F,/* LRCLK BCLK 为输入脚，TX1 TX2为输出脚 */ 411 412 /* MCLK 作为输入 */ 413 /* 0x08, 0x30, */ 414 /* MCLK divisor 生效 */ 415 /* 0x08, 0x38, */ 416 0x08, 0x20,/* MCLK 作为输入 12.288MHz */ 417 0x09, 0x03,/* 选MCLK作为PLL输入源 */ 418 0x0a, 0x0b, 419 0x0a, 0x8b, 420 0x0C, 0x0A,/* RT clock disable, TX clock enable, 421 enable clock to ADC3/4 */ 422 423 /* I2S */ 424 /* Tx sample size:16bit, Normal mode */ 425 /* 0x30, 0x0A, */ 426 0x30, 0x14,/* Tx sample size:24bit, Normal mode */ 427 0x35, 0xA2,/* left justified, enable I2S-1 and I2S-2 */ 428 429 0x10, 0x00, 430 0x11, 0x00, 431 0x10, 0x1F, 432 0x11, 0x1F,/* ADC 96k, enables all ADCs */ 433 0x16, 0x00, 434 0x10, 0x5F, 435 }; 436 437 static char codec_config_param_48k_16bit_mode[] = { 438 /* mic pga 增益 */ 439 /* 4通道录音工具 */ 440 0xBC, 29 << 1,/* 0x28 20dB 0x34 26dB */ 441 0xBD, 29 << 1, 442 0xBE, 29 << 1, 443 0xBF, 29 << 1, 444 445 0x60, 0x04, 446 0x66, 0x00, 447 0x67, 0x02, 448 449 /* PAD配置 */ 450 0x80, 0x03,/* MCLK 为输入 */ 451 0x83, 0x0F,/* LRCLK BCLK 为输入脚，TX1 TX2为输出脚 */ 452 453 /* MCLK 作为输入 */ 454 /* 0x08, 0x30, */ 455 /* MCLK divisor 生效 */ 456 /* 0x08, 0x38, */ 457 0x08, 0x20,/* MCLK 作为输入 12.288MHz */ 458 0x09, 0x03,/* 选MCLK作为PLL输入源 */ 459 0x0a, 0x03, 460 0x0a, 0x83, 461 0x0C, 0x0A,/* RT clock disable, TX clock enable, 462 enable clock to ADC3/4 */ 463 464 /* I2S */ 465 0x30, 0x0A,/* Tx sample size:16bit, Normal mode */ 466 /* Tx sample size:24bit, Normal mode */ 467 /* 0x30, 0x14, */ 468 0x35, 0xA2,/* left justified, enable I2S-1 and I2S-2 */ 469 470 0x10, 0x00, 471 0x11, 0x00, 472 0x10, 0x1F, 473 0x11, 0x4F,/* ADC 96k, enables all ADCs */ 474 0x16, 0x00, 475 0x10, 0x5F, 476 }; 477 478 static char codec_config_param_96k_16bit_mode[] = { 479 /* mic pga 增益 */ 480 /* 4通道录音工具 */ 481 0xBC, 29 << 1,/* 0x28 20dB 0x34 26dB */ 482 0xBD, 29 << 1, 483 0xBE, 29 << 1, 484 0xBF, 29 << 1, 485 486 0x60, 0x04, 487 0x66, 0x00, 488 0x67, 0x02, 489 490 /* PAD配置 */ 491 0x80, 0x03,/* MCLK 为输入 */ 492 0x83, 0x0F,/* LRCLK BCLK 为输入脚，TX1 TX2为输出脚 */ 493 494 /* MCLK 作为输入 */ 495 /* 0x08, 0x30, */ 496 /* MCLK divisor 生效 */ 497 /* 0x08, 0x38, */ 498 0x08, 0x20,/* MCLK 作为输入 12.288MHz */ 499 0x09, 0x03,/* 选MCLK作为PLL输入源 */ 500 0x0a, 0x01, 501 0x0a, 0x81, 502 0x0C, 0x0A,/* RT clock disable, TX clock enable, 503 enable clock to ADC3/4 */ 504 505 /* I2S */ 506 0x30, 0x0A,/* Tx sample size:16bit, Normal mode */ 507 /* Tx sample size:24bit, Normal mode */ 508 /* 0x30, 0x14, */ 509 0x35, 0xA2,/* left justified, enable I2S-1 and I2S-2 */ 510 511 0x10, 0x00, 512 0x11, 0x00, 513 0x10, 0x1F, 514 0x11, 0x5F,/* ADC 96k, enables all ADCs */ 515 0x16, 0x00, 516 0x10, 0x5F, 517 }; 518 #endif /* CX20810_CONFIG_H_ */ 519