1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2026 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef CPS_DRV_LPDDR4_H 10 #define CPS_DRV_LPDDR4_H 11 12 /* 13 * FIELD_GET / FIELD_PREP: identical definitions exist in 14 * include/drivers/cadence/cdns_nand.h (marked "TBD: Move to common place"). 15 * They are inlined here rather than included from that header because 16 * cdns_nand.h transitively pulls in cdns_combo_phy.h, which requires 17 * <stdint.h> types not available at this point in the DDR driver include 18 * chain. Once a suitable common TF-A header is agreed on, both copies 19 * should be consolidated there. 20 */ 21 #ifndef bf_shf 22 #define bf_shf(x) (__builtin_ffsll(x) - 1U) 23 #endif 24 25 #ifndef FIELD_GET 26 #define FIELD_GET(_mask, _reg) \ 27 ({ \ 28 (typeof(_mask))(((_reg) & (_mask)) >> bf_shf(_mask)); \ 29 }) 30 #endif 31 32 #ifndef FIELD_PREP 33 #define FIELD_PREP(_mask, _val) \ 34 ({ \ 35 ((typeof(_mask))(_val) << bf_shf(_mask)) & (_mask); \ 36 }) 37 #endif 38 39 #define CPS_FLD_MASK(fld) (fld ## _MASK) 40 41 #define CPS_FLD_READ(fld, reg_value) (FIELD_GET((CPS_FLD_MASK(fld)), (uint32_t)(reg_value))) 42 43 #define CPS_FLD_WRITE(fld, reg_value, value) \ 44 ({ \ 45 (reg_value & ~(CPS_FLD_MASK(fld))) | FIELD_PREP(CPS_FLD_MASK(fld), value); \ 46 }) 47 48 #define CPS_FLD_SET(fld, reg_value) \ 49 ({ \ 50 (reg_value | CPS_FLD_MASK(fld)); \ 51 }) 52 53 #endif /* CPS_DRV_LPDDR4_H */ 54