1 /* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A720_H 8 #define CORTEX_A720_H 9 10 #define CORTEX_A720_MIDR U(0x410FD810) 11 12 /******************************************************************************* 13 * CPU Auxiliary Control register 1 specific definitions. 14 ******************************************************************************/ 15 #define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0 16 17 /******************************************************************************* 18 * CPU Auxiliary Control register 2 specific definitions. 19 ******************************************************************************/ 20 #define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1 21 22 /******************************************************************************* 23 * CPU Auxiliary Control register 4 specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_A720_CPUACTLR4_EL1 S3_0_C15_C1_3 26 27 /******************************************************************************* 28 * CPU Extended Control register specific definitions 29 ******************************************************************************/ 30 #define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 31 32 /******************************************************************************* 33 * CPU Power Control register specific definitions 34 ******************************************************************************/ 35 #define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 36 #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 37 38 /******************************************************************************* 39 * CPU Instruction Patching Register Definitions 40 ******************************************************************************/ 41 #define CORTEX_A720_CPUPSELR_EL3 S3_6_C15_C8_0 42 #define CORTEX_A720_CPUPCR_EL3 S3_6_C15_C8_1 43 #define CORTEX_A720_CPUPOR_EL3 S3_6_C15_C8_2 44 #define CORTEX_A720_CPUPMR_EL3 S3_6_C15_C8_3 45 46 #ifndef __ASSEMBLER__ 47 long check_erratum_cortex_a720_3699561(long cpu_rev); 48 #endif /* __ASSEMBLER__ */ 49 50 #endif /* CORTEX_A720_H */ 51