1 /* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A510_H 8 #define CORTEX_A510_H 9 10 #define CORTEX_A510_MIDR U(0x410FD460) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) 17 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) 18 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) 19 #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) 20 #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) 21 #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) 22 #define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) 23 #define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) 24 25 /******************************************************************************* 26 * CPU Power Control register specific definitions 27 ******************************************************************************/ 28 #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30 #define CORTEX_A510_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS 0x70 31 #define CORTEX_A510_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS 0x380 32 33 /******************************************************************************* 34 * Complex auxiliary control register specific definitions 35 ******************************************************************************/ 36 #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 37 #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 38 #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) 39 #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 40 #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) 41 #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) 42 #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) 43 44 /******************************************************************************* 45 * Auxiliary control register specific definitions 46 ******************************************************************************/ 47 #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 48 #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) 49 #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) 50 #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 51 #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) 52 #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 53 #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) 54 #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) 55 #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) 56 57 /******************************************************************************* 58 * Auxiliary control register 2 specific definitions 59 ******************************************************************************/ 60 #define CORTEX_A510_CPUACTLR2_EL1 S3_0_C15_C1_1 61 62 /******************************************************************************* 63 * Auxiliary control register 3 specific definitions 64 ******************************************************************************/ 65 #define CORTEX_A510_CPUACTLR3_EL1 S3_0_C15_C1_2 66 67 #ifndef __ASSEMBLER__ 68 69 #if ERRATA_A510_2971420 70 long check_erratum_cortex_a510_2971420(long cpu_rev); 71 #endif 72 73 #endif /* __ASSEMBLER__ */ 74 75 #endif /* CORTEX_A510_H */ 76