1 /* 2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A35_H 8 #define CORTEX_A35_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A35 Main ID register for revision 0 */ 13 #define CORTEX_A35_MIDR U(0x410FD040) 14 15 /* L2 Extended Control Register */ 16 #define CORTEX_A35_L2ECTLR_EL1 S3_1_C11_C0_3 17 18 /******************************************************************************* 19 * CPU Extended Control register specific definitions. 20 * CPUECTLR_EL1 is an implementation-specific register. 21 ******************************************************************************/ 22 #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 23 #define CORTEX_A35_CPUECTLR_SMPEN_BIT (ULL(1) << 6) 24 25 /******************************************************************************* 26 * CPU Auxiliary Control register specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A35_CPUACTLR_EL1 S3_1_C15_C2_0 29 30 #define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI (ULL(1) << 44) 31 32 #endif /* CORTEX_A35_H */ 33