1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef RAMBLUR_PIMEM_HWIO_H 7 #define RAMBLUR_PIMEM_HWIO_H 8 9 /* 10 * Minimal HWIO definitions required by ramblur_pimem_v3.c. 11 * 12 * NOTE: The autogenerated-style *_INI() macros rely on helper functions 13 * (e.g. in_dword_masked()) provided by the including C file. 14 */ 15 16 #define RAMBLUR_PIMEM_REG_SIZE 0x4000 17 18 /* 19 * RAMBLUR_VERSION: PIMEM Version Details 20 * 21 * [bits] [value] 22 * 31:24 MAJOR_VERSION 23 * 23:16 MINOR_VERSION 24 * 15:0 STEP_VERSION 25 */ 26 #define RAMBLUR_VERSION_MAJOR_BMSK 0xff000000 27 #define RAMBLUR_VERSION_MINOR_BMSK 0x00ff0000 28 #define RAMBLUR_VERSION_STEP_BMSK 0x0000ffff 29 #define RAMBLUR_VERSION_MAJOR_SHFT 0x18 30 #define RAMBLUR_VERSION_MINOR_SHFT 0x10 31 #define RAMBLUR_VERSION_STEP_SHFT 0x0 32 #define RAMBLUR_VERSION_ADDR_OFFSET 0x00000000 33 #define RAMBLUR_VERSION_ADDR (RAMBLUR_VERSION_ADDR_OFFSET) 34 35 /* RAMBLUR_WINn_ALGORITHM_CONFIG (n=[0..3]) */ 36 #define RAMBLUR_WINn_ALGORITHM_CONFIG_ADDR_OFFSET(n) (0x68 + (0x4 * (n))) 37 #define RAMBLUR_WINn_ALGORITHM_CONFIG_ADDR(n) \ 38 (RAMBLUR_WINn_ALGORITHM_CONFIG_ADDR_OFFSET(n)) 39 40 /* Security attributes position in ALGORITHM_CONFIG register */ 41 #define RAMBLUR_WIN0_ALGORITHM_CONFIDENTIALITY_ENABLE_SHFT 0x2 42 #define RAMBLUR_WIN0_ALGORITHM_INTEGRITY_ENABLE_SHFT 0x1 43 #define RAMBLUR_WIN0_ALGORITHM_ANTIROLLBACK_ENABLE_SHFT 0x0 44 45 /* RAMBLUR_WINn_SIZE (n=[0..3]) */ 46 #define RAMBLUR_WINn_SIZE_RMSK 0x07f00000 47 #define RAMBLUR_WINn_SIZE_ADDR_OFFSET(n) (0x58 + (0x4 * (n))) 48 #define RAMBLUR_WINn_SIZE_ADDR(n) (RAMBLUR_WINn_SIZE_ADDR_OFFSET(n)) 49 50 /* RAMBLUR_WINn_CTL, n=[0..3] */ 51 #define RAMBLUR_WINn_CTL_OFFSET(n) (0x78 + (0x4 * (n))) 52 #define RAMBLUR_WINn_CTL_ADDR(n) (RAMBLUR_WINn_CTL_OFFSET(n)) 53 #define RAMBLUR_WINn_CTL_RMSK 0xf 54 #define RAMBLUR_WINn_CTL_START_HW_INIT_BMSK 0x8 55 #define RAMBLUR_WINn_CTL_START_HW_INIT_SHFT 0x3 56 #define RAMBLUR_WINn_CTL_SW_INIT_MODE_BMSK 0x4 57 #define RAMBLUR_WINn_CTL_SW_INIT_MODE_SHFT 0x2 58 #define RAMBLUR_WINn_CTL_WIN_ENABLE_BMSK 0x2 59 #define RAMBLUR_WINn_CTL_WIN_ENABLE_SHFT 0x1 60 #define RAMBLUR_WINn_CTL_WIN_DISABLE_BMSK 0x1 61 #define RAMBLUR_WINn_CTL_WIN_DISABLE_SHFT 0x0 62 #define RAMBLUR_WINn_CTL_INI(n) \ 63 in_dword_masked(RAMBLUR_WINn_CTL_ADDR(n), RAMBLUR_WINn_CTL_RMSK) 64 65 /* RAMBLUR_WINn_STATUS, n=[0..3] */ 66 #define RAMBLUR_WINn_STATUS_OFFSET(n) (0x98 + (0x4 * (n))) 67 #define RAMBLUR_WINn_STATUS_ADDR(n) (RAMBLUR_WINn_STATUS_OFFSET(n)) 68 #define RAMBLUR_WINn_STATUS_HW_INIT_DONE_BMSK 0x4 69 #define RAMBLUR_WINn_STATUS_HW_INIT_DONE_SHFT 0x2 70 #define RAMBLUR_WINn_STATUS_HW_INIT_IN_PROGRESS_BMSK 0x2 71 #define RAMBLUR_WINn_STATUS_HW_INIT_IN_PROGRESS_SHFT 0x1 72 #define RAMBLUR_WINn_STATUS_WIN_ENABLE_STATUS_BMSK 0x1 73 #define RAMBLUR_WINn_STATUS_WIN_ENABLE_STATUS_SHFT 0x0 74 75 /* RAMBLUR_WINn_HW_INIT_START, n=[0..3] */ 76 #define RAMBLUR_WINn_HW_INIT_START_OFFSET(n) (0x88 + (0x4 * (n))) 77 #define RAMBLUR_WINn_HW_INIT_START_ADDR(n) \ 78 (RAMBLUR_WINn_HW_INIT_START_OFFSET(n)) 79 #define RAMBLUR_WINn_HW_INIT_START_RMSK 0x3ff8000U 80 #define RAMBLUR_WINn_HW_INIT_START_BMSK 0x3ff8000U 81 #define RAMBLUR_WINn_HW_INIT_START_INI(n) \ 82 in_dword_masked(RAMBLUR_WINn_HW_INIT_START_ADDR(n), \ 83 RAMBLUR_WINn_HW_INIT_START_RMSK) 84 85 /* RAMBLUR_WINn_DATA_VAULT_ADDR_{HI,LOW}, n=[0..3] */ 86 #define RAMBLUR_WINn_DATA_VAULT_ADDR_HI_RMSK 0xf 87 #define RAMBLUR_WINn_DATA_VAULT_ADDR_HI_OFFSET(n) (0x38 + (0x4 * (n))) 88 #define RAMBLUR_WINn_DATA_VAULT_ADDR_HI_ADDR(n) \ 89 (RAMBLUR_WINn_DATA_VAULT_ADDR_HI_OFFSET(n)) 90 #define RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_RMSK 0xfff00000 91 #define RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_OFFSET(n) (0x48 + (0x4 * (n))) 92 #define RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_ADDR(n) \ 93 (RAMBLUR_WINn_DATA_VAULT_ADDR_LOW_OFFSET(n)) 94 95 /* RAMBLUR_WINn_DATA_TXN_QSB_CTL, n=[0..3] */ 96 #define RAMBLUR_WINn_DATA_TXN_QSB_CTL_OFFSET(n) (0xa8 + (0x4 * (n))) 97 #define RAMBLUR_WINn_DATA_TXN_QSB_CTL_ADDR(n) \ 98 (RAMBLUR_WINn_DATA_TXN_QSB_CTL_OFFSET(n)) 99 #define RAMBLUR_WINn_DATA_TXN_QSB_CTL_RMSK 0x0fffffff 100 #define RAMBLUR_WINn_DATA_TXN_QSB_CTL_AINNERCACHEABLE_BMSK 0x4000 101 #define RAMBLUR_WINn_DATA_TXN_QSB_CTL_AINNERCACHEABLE_SHFT 0xe 102 #define RAMBLUR_WINn_DATA_TXN_QSB_CTL_INI(n) \ 103 in_dword_masked(RAMBLUR_WINn_DATA_TXN_QSB_CTL_ADDR(n), \ 104 RAMBLUR_WINn_DATA_TXN_QSB_CTL_RMSK) 105 106 /* RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL, n=[0..3] */ 107 #define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_OFFSET(n) (0xb8 + (0x4 * (n))) 108 #define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_ADDR(n) \ 109 (RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_OFFSET(n)) 110 #define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_RMSK 0x0fffffff 111 #define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_AINNERCACHEABLE_BMSK 0x4000 112 #define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_AINNERCACHEABLE_SHFT 0xe 113 #define RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_INI(n) \ 114 in_dword_masked(RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_ADDR(n), \ 115 RAMBLUR_WINn_OVERHEAD_TXN_QSB_CTL_RMSK) 116 117 #endif /* RAMBLUR_PIMEM_HWIO_H */ 118