1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright 2021 NXP
4 *
5 * Driver for DSPI Controller
6 *
7 */
8
9 #include <assert.h>
10 #include <drivers/ls_dspi.h>
11 #include <io.h>
12 #include <kernel/boot.h>
13 #include <kernel/delay.h>
14 #include <kernel/dt.h>
15 #include <libfdt.h>
16 #include <mm/core_memprot.h>
17 #include <platform_config.h>
18 #include <util.h>
19
20 /* SPI register offset */
21 #define DSPI_MCR 0x0 /* Module Configuration Register */
22 #define DSPI_TCR 0x8 /* Transfer Count Register */
23 #define DSPI_CTAR0 \
24 0xC /* Clock and Transfer Attributes Register (in Master mode) */
25 #define DSPI_CTAR1 \
26 0x10 /* Clock and Transfer Attributes Register (in Master mode) */
27 #define DSPI_SR 0x2C /* Status Register */
28 #define DSPI_RSER 0x30 /* DMA/Interrupt Request Select and Enable Register */
29 #define DSPI_PUSHR 0x34 /* PUSH TX FIFO Register In Master Mode */
30 #define DSPI_POPR 0x38 /* POP RX FIFO Register */
31 #define DSPI_TXFR0 0x3C /* Transmit FIFO Registers */
32 #define DSPI_TXFR1 0x40 /* Transmit FIFO Registers */
33 #define DSPI_TXFR2 0x44 /* Transmit FIFO Registers */
34 #define DSPI_TXFR3 0x48 /* Transmit FIFO Registers */
35 #define DSPI_RXFR0 0x7C /* Receive FIFO Registers */
36 #define DSPI_RXFR1 0x80 /* Receive FIFO Registers */
37 #define DSPI_RXFR2 0x84 /* Receive FIFO Registers */
38 #define DSPI_RXFR3 0x88 /* Receive FIFO Registers */
39 #define DSPI_CTARE0 0x11C /* Clock and Transfer Attributes Register Extended */
40 #define DSPI_CTARE1 0x120 /* Clock and Transfer Attributes Register Extended */
41 #define DSPI_SREX 0x13C /* Status Register Extended */
42
43 /* Module configuration */
44 #define DSPI_MCR_MSTR 0x80000000 /* Master/Slave Mode Select [0] */
45 #define DSPI_MCR_CSCK 0x40000000 /* Continuous SCK Enable [1] */
46 #define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) /* SPI Configuration [2-3] */
47 #define DSPI_MCR_ROOE \
48 0x01000000 /* Receive FIFO Overflow Overwrite Enable[7] */
49 #define DSPI_MCR_PCSIS(x) \
50 (1 << (16 + (x))) /* Peripheral Chip Select x Inactive State [12-15] */
51 #define DSPI_MCR_PCSIS_MASK (0xff << 16)
52 #define DSPI_MCR_MDIS 0x00004000 /* Module Disable [17] */
53 #define DSPI_MCR_DTXF 0x00002000 /* Disable Transmit FIFO [18] */
54 #define DSPI_MCR_DRXF 0x00001000 /* Disable Receive FIFO [19] */
55 #define DSPI_MCR_CTXF 0x00000800 /* Clear TX FIFO [20] */
56 #define DSPI_MCR_CRXF 0x00000400 /* Clear RX FIFO [21] */
57 #define DPSI_XSPI 0x00000008 /* Extended SPI Mode [28] */
58 #define DSPI_MCR_PES 0x00000002 /* Parity Error Stop [30] */
59 #define DSPI_MCR_HALT 0x00000001 /* Halt [31] */
60 #define DPSI_ENABLE 0x0
61 #define DSPI_DISABLE 0x1
62
63 /* Transfer count */
64 #define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16)
65
66 /* Status */
67 #define DSPI_SR_TXRXS 0x40000000 /* TX and RX Status [1] */
68 #define DSPI_SR_TXCTR(x) \
69 (((x) & 0x0000F000) >> 12) /* TX FIFO Counter [16-19] */
70 #define DSPI_SR_RXCTR(x) \
71 (((x) & 0x000000F0) >> 4) /* RX FIFO Counter [24-27] */
72
73 #define DSPI_DATA_8BIT SHIFT_U32(8, 0)
74 #define DSPI_DATA_16BIT SHIFT_U32(0xF, 0)
75
76 #define DSPI_TFR_CONT (0x80000000)
77 #define DSPI_TFR_CTAS(x) (((x) & 0x07) << 12)
78 #define DSPI_TFR_PCS(x) (((1 << (x)) & 0x0000003f) << 16)
79 #define DSPI_IDLE_DATA 0x0
80
81 /* tx/rx data wait timeout value, unit: us */
82 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
83
84 /* Transfer Fifo */
85 #define DSPI_TFR_TXDATA(x) (((x) & 0x0000FFFF))
86
87 /* Bit definitions and macros for DRFR */
88 #define DSPI_RFR_RXDATA(x) (((x) & 0x0000FFFF))
89
90 /* CTAR register pre-configure mask */
91 #define DSPI_CTAR_SET_MODE_MASK \
92 (DSPI_CTAR_FMSZ(15) | DSPI_CTAR_PCS_SCK(3) | DSPI_CTAR_PA_SCK(3) | \
93 DSPI_CTAR_P_DT(3) | DSPI_CTAR_CS_SCK(15) | DSPI_CTAR_A_SCK(15) | \
94 DSPI_CTAR_A_DT(15))
95
96 /* default SCK frequency, unit: HZ */
97 #define PLATFORM_CLK 650000000
98 #define DSPI_DEFAULT_SCK_FREQ 10000000
99 #define DSPI_CLK_DIV 4 /* prescaler divisor */
100 #define DSPI_CLK (PLATFORM_CLK / DSPI_CLK_DIV) /* DSPI clock */
101 #define CS_SPEED_MAX_HZ 1000000 /* Slave max speed */
102
103 /*
104 * Calculate the divide scaler value between expected SCK frequency
105 * and input clk frequency
106 * req_pbr: pre-scaler value of baud rate for slave
107 * req_br: scaler value of baud rate for slave
108 * speed_hz: speed value of slave
109 * clkrate: clock value of slave
110 */
dspi_convert_hz_to_baud(unsigned int * req_pbr,unsigned int * req_br,unsigned int speed_hz,unsigned int clkrate)111 static TEE_Result dspi_convert_hz_to_baud(unsigned int *req_pbr,
112 unsigned int *req_br,
113 unsigned int speed_hz,
114 unsigned int clkrate)
115 {
116 /* Valid pre-scaler values for baud rate*/
117 static const unsigned int pbr_val[4] = { 2, 3, 5, 7 };
118 /* Valid baud rate scaler values*/
119 static const unsigned int brs_val[16] = { 2, 4, 6, 8,
120 16, 32, 64, 128,
121 256, 512, 1024, 2048,
122 4096, 8192, 16384, 32768 };
123 unsigned int tmp_val = 0;
124 unsigned int curr_val = 0;
125 unsigned int i = 0;
126 unsigned int j = 0;
127
128 tmp_val = clkrate / speed_hz;
129
130 for (i = 0; i < ARRAY_SIZE(pbr_val); i++) {
131 for (j = 0; j < ARRAY_SIZE(brs_val); j++) {
132 curr_val = pbr_val[i] * brs_val[j];
133 if (curr_val >= tmp_val) {
134 *req_pbr = i;
135 *req_br = j;
136 return TEE_SUCCESS;
137 }
138 }
139 }
140
141 EMSG("Can not find valid baud rate, speed_hz is %d, ", speed_hz);
142 EMSG("clkrate is %d, using max prescaler value", clkrate);
143
144 return TEE_ERROR_ITEM_NOT_FOUND;
145 }
146
147 /*
148 * Configure speed of slave
149 * dspi_data: DSPI controller chip instance
150 * speed: speed of slave
151 */
dspi_setup_speed(struct ls_dspi_data * dspi_data,unsigned int speed)152 static void dspi_setup_speed(struct ls_dspi_data *dspi_data,
153 unsigned int speed)
154 {
155 TEE_Result status = TEE_ERROR_GENERIC;
156 unsigned int bus_setup = 0;
157 unsigned int bus_clock = 0;
158 unsigned int req_i = 0;
159 unsigned int req_j = 0;
160
161 bus_clock = dspi_data->bus_clk_hz;
162
163 DMSG("DSPI set_speed: expected SCK speed %u, bus_clk %u", speed,
164 bus_clock);
165
166 bus_setup = io_read32(dspi_data->base + DSPI_CTAR0);
167 bus_setup &= ~(DSPI_CTAR_BRD | DSPI_CTAR_BRP(0x3) | DSPI_CTAR_BR(0xf));
168
169 status = dspi_convert_hz_to_baud(&req_i, &req_j, speed, bus_clock);
170
171 /* In case of failure scenario with max speed, setting default speed */
172 if (status == TEE_ERROR_ITEM_NOT_FOUND) {
173 speed = dspi_data->speed_hz;
174 status = dspi_convert_hz_to_baud(&req_i, &req_j,
175 speed, bus_clock);
176 }
177
178 if (status == TEE_SUCCESS) {
179 bus_setup |= (DSPI_CTAR_BRP(req_i) | DSPI_CTAR_BR(req_j));
180 io_write32(dspi_data->base + DSPI_CTAR0, bus_setup);
181 dspi_data->speed_hz = speed;
182 } else {
183 EMSG("Unable to set speed");
184 }
185 }
186
187 /*
188 * Transferred data to TX FIFO
189 * dspi_data: DSPI controller chip instance
190 */
dspi_tx(struct ls_dspi_data * dspi_data,uint32_t ctrl,uint16_t data)191 static void dspi_tx(struct ls_dspi_data *dspi_data, uint32_t ctrl,
192 uint16_t data)
193 {
194 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
195 uint32_t dspi_val_addr = dspi_data->base + DSPI_PUSHR;
196 uint32_t dspi_val = ctrl | data;
197
198 /* wait for empty entries in TXFIFO or timeout */
199 while (DSPI_SR_TXCTR(io_read32(dspi_data->base + DSPI_SR)) >= 4 &&
200 timeout--)
201 udelay(1);
202
203 if (timeout >= 0)
204 io_write32(dspi_val_addr, dspi_val);
205 else
206 EMSG("waiting timeout!");
207 }
208
209 /*
210 * Read data from RX FIFO
211 * dspi_data: DSPI controller chip instance
212 */
dspi_rx(struct ls_dspi_data * dspi_data)213 static uint16_t dspi_rx(struct ls_dspi_data *dspi_data)
214 {
215 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
216 uint32_t dspi_val_addr = dspi_data->base + DSPI_POPR;
217
218 /* wait for valid entries in RXFIFO or timeout */
219 while (DSPI_SR_RXCTR(io_read32(dspi_data->base + DSPI_SR)) == 0 &&
220 timeout--)
221 udelay(1);
222
223 if (timeout >= 0)
224 return (uint16_t)DSPI_RFR_RXDATA(io_read32(dspi_val_addr));
225
226 EMSG("waiting timeout!");
227
228 return 0xFFFF;
229 }
230
231 /*
232 * Transfer and Receive 8-bit data
233 * chip: spi_chip instance
234 * wdata: TX data queue
235 * rdata: RX data queue
236 * num_pkts: number of data packets
237 */
ls_dspi_txrx8(struct spi_chip * chip,uint8_t * wdata,uint8_t * rdata,size_t num_pkts)238 static enum spi_result ls_dspi_txrx8(struct spi_chip *chip, uint8_t *wdata,
239 uint8_t *rdata, size_t num_pkts)
240 {
241 uint8_t *spi_rd = NULL;
242 uint8_t *spi_wr = NULL;
243 uint32_t ctrl = 0;
244 struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
245 chip);
246 unsigned int cs = data->slave_cs;
247
248 spi_wr = wdata;
249 spi_rd = rdata;
250
251 /*
252 * Assert PCSn signals between transfers
253 * select which CTAR register and slave to be used for TX
254 * CTAS selects which CTAR to be used, here we are using CTAR0
255 * PCS (peripheral chip select) is selecting the slave.
256 */
257 ctrl = DSPI_TFR_CTAS(data->ctar_sel) | DSPI_TFR_PCS(cs);
258 if (data->slave_mode & SPI_CONT)
259 ctrl |= DSPI_TFR_CONT;
260
261 if (data->slave_data_size_bits != 8) {
262 EMSG("data_size_bits should be 8, not %u",
263 data->slave_data_size_bits);
264 return SPI_ERR_CFG;
265 }
266
267 while (num_pkts) {
268 if (wdata && rdata) {
269 dspi_tx(data, ctrl, *spi_wr++);
270 *spi_rd++ = dspi_rx(data);
271 } else if (wdata) {
272 dspi_tx(data, ctrl, *spi_wr++);
273 dspi_rx(data);
274 } else if (rdata) {
275 dspi_tx(data, ctrl, DSPI_IDLE_DATA);
276 *spi_rd++ = dspi_rx(data);
277 }
278 num_pkts = num_pkts - 1;
279 }
280
281 return SPI_OK;
282 }
283
284 /*
285 * Transfer and Receive 16-bit data
286 * chip: spi_chip instance
287 * wdata: TX data queue
288 * rdata: RX data queue
289 * num_pkts: number of data packets
290 */
ls_dspi_txrx16(struct spi_chip * chip,uint16_t * wdata,uint16_t * rdata,size_t num_pkts)291 static enum spi_result ls_dspi_txrx16(struct spi_chip *chip, uint16_t *wdata,
292 uint16_t *rdata, size_t num_pkts)
293 {
294 uint32_t ctrl = 0;
295 uint16_t *spi_rd = NULL;
296 uint16_t *spi_wr = NULL;
297 struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
298 chip);
299 unsigned int cs = data->slave_cs;
300
301 spi_wr = wdata;
302 spi_rd = rdata;
303
304 /*
305 * Assert PCSn signals between transfers
306 * select which CTAR register and slave to be used for TX
307 * CTAS selects which CTAR to be used, here we are using CTAR0
308 * PCS (peripheral chip select) is selecting the slave.
309 */
310 ctrl = DSPI_TFR_CTAS(data->ctar_sel) | DSPI_TFR_PCS(cs);
311 if (data->slave_mode & SPI_CONT)
312 ctrl |= DSPI_TFR_CONT;
313
314 if (data->slave_data_size_bits != 16) {
315 EMSG("data_size_bits should be 16, not %u",
316 data->slave_data_size_bits);
317 return SPI_ERR_CFG;
318 }
319
320 while (num_pkts) {
321 if (wdata && rdata) {
322 dspi_tx(data, ctrl, *spi_wr++);
323 *spi_rd++ = dspi_rx(data);
324 } else if (wdata) {
325 dspi_tx(data, ctrl, *spi_wr++);
326 dspi_rx(data);
327 } else if (rdata) {
328 dspi_tx(data, ctrl, DSPI_IDLE_DATA);
329 *spi_rd++ = dspi_rx(data);
330 }
331 num_pkts = num_pkts - 1;
332 }
333
334 return SPI_OK;
335 }
336
337 /*
338 * Statrt DSPI module
339 * chip: spi_chip instance
340 */
ls_dspi_start(struct spi_chip * chip)341 static void ls_dspi_start(struct spi_chip *chip)
342 {
343 struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
344 chip);
345
346 DMSG("Start DSPI Module");
347 io_clrbits32(data->base + DSPI_MCR, DSPI_MCR_HALT);
348 }
349
350 /*
351 * Stop DSPI module
352 * chip: spi_chip instance
353 */
ls_dspi_end(struct spi_chip * chip)354 static void ls_dspi_end(struct spi_chip *chip)
355 {
356 struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
357 chip);
358
359 /* De-assert PCSn if in CONT mode */
360 if (data->slave_mode & SPI_CONT) {
361 unsigned int cs = data->slave_cs;
362 unsigned int ctrl = DSPI_TFR_CTAS(data->ctar_sel) |
363 DSPI_TFR_PCS(cs);
364
365 /* Dummy read to deassert */
366 dspi_tx(data, ctrl, DSPI_IDLE_DATA);
367 dspi_rx(data);
368 }
369
370 DMSG("Stop DSPI Module");
371 io_setbits32(data->base + DSPI_MCR, DSPI_MCR_HALT);
372 }
373
374 /*
375 * Clear RX and TX FIFO
376 * dspi_data: DSPI controller chip instance
377 */
dspi_flush_fifo(struct ls_dspi_data * dspi_data)378 static void dspi_flush_fifo(struct ls_dspi_data *dspi_data)
379 {
380 unsigned int mcr_val = 0;
381
382 mcr_val = io_read32(dspi_data->base + DSPI_MCR);
383 /* flush RX and TX FIFO */
384 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
385
386 io_write32(dspi_data->base + DSPI_MCR, mcr_val);
387 }
388
389 /*
390 * Flush DSPI module
391 * chip: spi_chip instance
392 */
ls_dspi_flush(struct spi_chip * chip)393 static void ls_dspi_flush(struct spi_chip *chip)
394 {
395 struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
396 chip);
397
398 dspi_flush_fifo(data);
399 }
400
401 /*
402 * Configure active state of slave
403 * dspi_data: DSPI controller chip instance
404 * cs: chip select value of slave
405 * state: slave mode
406 */
dspi_set_cs_active_state(struct ls_dspi_data * dspi_data,unsigned int cs,unsigned int state)407 static void dspi_set_cs_active_state(struct ls_dspi_data *dspi_data,
408 unsigned int cs, unsigned int state)
409 {
410 DMSG("Set CS active state cs=%d state=%d", cs, state);
411
412 if (state & SPI_CS_HIGH)
413 /* CSx inactive state is low */
414 io_clrbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs));
415 else
416 /* CSx inactive state is high */
417 io_setbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs));
418 }
419
420 /*
421 * Configure transfer state of slave
422 * dspi_data: DSPI controller chip instance
423 * state: slave mode
424 */
dspi_set_transfer_state(struct ls_dspi_data * dspi_data,unsigned int state)425 static void dspi_set_transfer_state(struct ls_dspi_data *dspi_data,
426 unsigned int state)
427 {
428 unsigned int bus_setup = 0;
429
430 DMSG("Set transfer state=%d bits=%d", state,
431 dspi_data->slave_data_size_bits);
432
433 bus_setup = io_read32(dspi_data->base + DSPI_CTAR0);
434 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
435 bus_setup |= dspi_data->ctar_val;
436 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
437
438 if (state & SPI_CPOL)
439 bus_setup |= DSPI_CTAR_CPOL;
440 if (state & SPI_CPHA)
441 bus_setup |= DSPI_CTAR_CPHA;
442 if (state & SPI_LSB_FIRST)
443 bus_setup |= DSPI_CTAR_LSBFE;
444
445 if (dspi_data->slave_data_size_bits == 8)
446 bus_setup |= DSPI_CTAR_FMSZ(7);
447 else if (dspi_data->slave_data_size_bits == 16)
448 bus_setup |= DSPI_CTAR_FMSZ(15);
449
450 if (dspi_data->ctar_sel == 0)
451 io_write32(dspi_data->base + DSPI_CTAR0, bus_setup);
452 else
453 io_write32(dspi_data->base + DSPI_CTAR1, bus_setup);
454 }
455
456 /*
457 * Configure speed of slave
458 * dspi_data: DSPI controller chip instance
459 * speed_max_hz: maximum speed for slave
460 */
dspi_set_speed(struct ls_dspi_data * dspi_data,unsigned int speed_max_hz)461 static void dspi_set_speed(struct ls_dspi_data *dspi_data,
462 unsigned int speed_max_hz)
463 {
464 dspi_setup_speed(dspi_data, speed_max_hz);
465 }
466
467 /*
468 * Configure slave for DSPI controller
469 * dspi_data: DSPI controller chip instance
470 * cs: chip select value of slave
471 * speed_max_hz: maximum speed of slave
472 * state: slave mode
473 */
dspi_config_slave_state(struct ls_dspi_data * dspi_data,unsigned int cs,unsigned int speed_max_hz,unsigned int state)474 static void dspi_config_slave_state(struct ls_dspi_data *dspi_data,
475 unsigned int cs, unsigned int speed_max_hz,
476 unsigned int state)
477 {
478 unsigned int sr_val = 0;
479
480 /* configure speed */
481 dspi_set_speed(dspi_data, speed_max_hz);
482
483 /* configure transfer state */
484 dspi_set_transfer_state(dspi_data, state);
485
486 /* configure active state of CSX */
487 dspi_set_cs_active_state(dspi_data, cs, state);
488
489 /* clear FIFO */
490 dspi_flush_fifo(dspi_data);
491
492 /* check module TX and RX status */
493 sr_val = io_read32(dspi_data->base + DSPI_SR);
494 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
495 EMSG("DSPI RX/TX not ready");
496 }
497
498 /*
499 * Configure master for DSPI controller
500 * dspi_data: DSPI controller chip instance
501 * mcr_val: value of master configuration register
502 */
dspi_set_master_state(struct ls_dspi_data * dspi_data,unsigned int mcr_val)503 static void dspi_set_master_state(struct ls_dspi_data *dspi_data,
504 unsigned int mcr_val)
505 {
506 DMSG("Set master state val=0x%x", mcr_val);
507 io_write32(dspi_data->base + DSPI_MCR, mcr_val);
508 }
509
510 /*
511 * Configure DSPI controller
512 * chip: spi_chip instance
513 */
ls_dspi_configure(struct spi_chip * chip)514 static void ls_dspi_configure(struct spi_chip *chip)
515 {
516 struct ls_dspi_data *data = container_of(chip, struct ls_dspi_data,
517 chip);
518 unsigned int mcr_cfg_val = 0;
519
520 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | DSPI_MCR_CRXF |
521 DSPI_MCR_CTXF;
522
523 /* Configure Master */
524 dspi_set_master_state(data, mcr_cfg_val);
525
526 /* Configure DSPI slave */
527 dspi_config_slave_state(data, data->slave_cs, data->slave_speed_max_hz,
528 data->slave_mode);
529 }
530
531 /*
532 * Extract information for DSPI Controller from the DTB
533 * dspi_data: DSPI controller chip instance
534 */
get_info_from_device_tree(struct ls_dspi_data * dspi_data)535 static TEE_Result get_info_from_device_tree(struct ls_dspi_data *dspi_data)
536 {
537 const fdt32_t *bus_num = NULL;
538 const fdt32_t *chip_select_num = NULL;
539 size_t size = 0;
540 int node = 0;
541 vaddr_t ctrl_base = 0;
542 void *fdt = NULL;
543
544 /*
545 * First get the DSPI Controller base address from the DTB
546 * if DTB present and if the DSPI Controller defined in it.
547 */
548 fdt = get_dt();
549 if (!fdt) {
550 EMSG("Unable to get DTB, DSPI init failed");
551 return TEE_ERROR_ITEM_NOT_FOUND;
552 }
553
554 node = 0;
555 while (node != -FDT_ERR_NOTFOUND) {
556 node = fdt_node_offset_by_compatible(fdt, node,
557 "fsl,lx2160a-dspi");
558 if (!(fdt_get_status(fdt, node) & DT_STATUS_OK_SEC))
559 continue;
560
561 bus_num = fdt_getprop(fdt, node, "bus-num", NULL);
562 if (bus_num && dspi_data->slave_bus ==
563 (unsigned int)fdt32_to_cpu(*bus_num)) {
564 if (dt_map_dev(fdt, node, &ctrl_base, &size,
565 DT_MAP_AUTO) < 0) {
566 EMSG("Unable to get virtual address");
567 return TEE_ERROR_GENERIC;
568 }
569 break;
570 }
571 }
572
573 dspi_data->base = ctrl_base;
574 dspi_data->bus_clk_hz = DSPI_CLK;
575
576 chip_select_num = fdt_getprop(fdt, node, "spi-num-chipselects", NULL);
577 if (chip_select_num)
578 dspi_data->num_chipselect = (int)fdt32_to_cpu(*chip_select_num);
579 else
580 return TEE_ERROR_ITEM_NOT_FOUND;
581
582 dspi_data->speed_hz = DSPI_DEFAULT_SCK_FREQ;
583
584 return TEE_SUCCESS;
585 }
586
587 static const struct spi_ops ls_dspi_ops = {
588 .configure = ls_dspi_configure,
589 .start = ls_dspi_start,
590 .txrx8 = ls_dspi_txrx8,
591 .txrx16 = ls_dspi_txrx16,
592 .end = ls_dspi_end,
593 .flushfifo = ls_dspi_flush,
594 };
595 DECLARE_KEEP_PAGER(ls_dspi_ops);
596
ls_dspi_init(struct ls_dspi_data * dspi_data)597 TEE_Result ls_dspi_init(struct ls_dspi_data *dspi_data)
598 {
599 TEE_Result status = TEE_ERROR_GENERIC;
600
601 /*
602 * First get the DSPI Controller base address from the DTB,
603 * if DTB present and if the DSPI Controller defined in it.
604 */
605 if (dspi_data)
606 status = get_info_from_device_tree(dspi_data);
607 if (status == TEE_SUCCESS)
608 /* generic DSPI chip handle */
609 dspi_data->chip.ops = &ls_dspi_ops;
610 else
611 EMSG("Unable to get info from device tree");
612
613 return status;
614 }
615