1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2025, Linaro Ltd
4 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <drivers/clk.h>
8 #include <drivers/clk_qcom.h>
9 #include <io.h>
10 #include <mm/core_mmu.h>
11
12 register_phys_mem(MEM_AREA_IO_NSEC, GCC_BASE, GCC_SIZE);
13
14 #define CBCR_BRANCH_ENABLE_BIT BIT(0)
15 #define CBCR_HW_CTL_ENABLE_BIT BIT(1)
16 #define CBCR_BRANCH_OFF_BIT BIT(31)
17
cbcr_branch_on(uint32_t val)18 static inline bool cbcr_branch_on(uint32_t val)
19 {
20 return !(val & CBCR_BRANCH_OFF_BIT);
21 }
22
qcom_clock_enable_cbc(vaddr_t cbcr)23 TEE_Result qcom_clock_enable_cbc(vaddr_t cbcr)
24 {
25 int ret = 0;
26
27 io_setbits32(cbcr, CBCR_BRANCH_ENABLE_BIT);
28
29 REG_POLL_TIMEOUT(cbcr, 10 * 1000, 10, &ret, cbcr_branch_on);
30
31 if (ret < 0)
32 return TEE_ERROR_TIMEOUT;
33
34 return TEE_SUCCESS;
35 }
36
qcom_clock_enable(enum qcom_clk_group group)37 TEE_Result qcom_clock_enable(enum qcom_clk_group group)
38 {
39 switch (group) {
40 case QCOM_CLKS_TURING:
41 case QCOM_CLKS_LPASS:
42 case QCOM_CLKS_WPSS:
43 return qcom_clock_enable_pas(group);
44 default:
45 EMSG("Unsupported clock group %d\n", group);
46 return TEE_ERROR_BAD_PARAMETERS;
47 }
48
49 return TEE_SUCCESS;
50 }
51