1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+)
2 /*
3 * Copyright (C) 2018-2022, STMicroelectronics
4 */
5
6 #include <assert.h>
7 #include <config.h>
8 #include <drivers/stm32mp1_rcc.h>
9 #include <drivers/clk.h>
10 #include <drivers/clk_dt.h>
11 #include <drivers/stm32_shared_io.h>
12 #include <drivers/stm32mp_dt_bindings.h>
13 #include <initcall.h>
14 #include <io.h>
15 #include <keep.h>
16 #include <kernel/dt.h>
17 #include <kernel/dt_driver.h>
18 #include <kernel/boot.h>
19 #include <kernel/panic.h>
20 #include <kernel/spinlock.h>
21 #include <libfdt.h>
22 #include <platform_config.h>
23 #include <stdio.h>
24 #include <stm32_util.h>
25 #include <trace.h>
26 #include <util.h>
27
28 /* Identifiers for root oscillators */
29 enum stm32mp_osc_id {
30 OSC_HSI,
31 OSC_HSE,
32 OSC_CSI,
33 OSC_LSI,
34 OSC_LSE,
35 OSC_I2S_CKIN,
36 OSC_USB_PHY_48,
37 NB_OSC,
38 _UNKNOWN_OSC_ID = 0xffU
39 };
40
41 /* Identifiers for parent clocks */
42 enum stm32mp1_parent_id {
43 _HSI,
44 _HSE,
45 _CSI,
46 _LSI,
47 _LSE,
48 _I2S_CKIN,
49 _USB_PHY_48,
50 _HSI_KER,
51 _HSE_KER,
52 _HSE_KER_DIV2,
53 _HSE_RTC,
54 _CSI_KER,
55 _PLL1_P,
56 _PLL1_Q,
57 _PLL1_R,
58 _PLL2_P,
59 _PLL2_Q,
60 _PLL2_R,
61 _PLL3_P,
62 _PLL3_Q,
63 _PLL3_R,
64 _PLL4_P,
65 _PLL4_Q,
66 _PLL4_R,
67 _ACLK,
68 _PCLK1,
69 _PCLK2,
70 _PCLK3,
71 _PCLK4,
72 _PCLK5,
73 _HCLK5,
74 _HCLK6,
75 _HCLK2,
76 _CK_PER,
77 _CK_MPU,
78 _CK_MCU,
79 _PARENT_NB,
80 _UNKNOWN_ID = 0xff,
81 };
82
83 /*
84 * Identifiers for parent clock selectors.
85 * This enum lists only the parent clocks we are interested in.
86 */
87 enum stm32mp1_parent_sel {
88 _STGEN_SEL,
89 _I2C35_SEL,
90 _I2C46_SEL,
91 _SPI6_SEL,
92 _USART1_SEL,
93 _RNG1_SEL,
94 _UART6_SEL,
95 _UART24_SEL,
96 _UART35_SEL,
97 _UART78_SEL,
98 _AXISS_SEL,
99 _MCUSS_SEL,
100 _USBPHY_SEL,
101 _USBO_SEL,
102 _RTC_SEL,
103 _MPU_SEL,
104 _PARENT_SEL_NB,
105 _UNKNOWN_SEL = 0xff,
106 };
107
108 static const uint8_t parent_id_clock_id[_PARENT_NB] = {
109 [_HSE] = CK_HSE,
110 [_HSI] = CK_HSI,
111 [_CSI] = CK_CSI,
112 [_LSE] = CK_LSE,
113 [_LSI] = CK_LSI,
114 [_I2S_CKIN] = _UNKNOWN_ID,
115 [_USB_PHY_48] = _UNKNOWN_ID,
116 [_HSI_KER] = CK_HSI,
117 [_HSE_KER] = CK_HSE,
118 [_HSE_KER_DIV2] = CK_HSE_DIV2,
119 [_HSE_RTC] = _UNKNOWN_ID,
120 [_CSI_KER] = CK_CSI,
121 [_PLL1_P] = PLL1_P,
122 [_PLL1_Q] = PLL1_Q,
123 [_PLL1_R] = PLL1_R,
124 [_PLL2_P] = PLL2_P,
125 [_PLL2_Q] = PLL2_Q,
126 [_PLL2_R] = PLL2_R,
127 [_PLL3_P] = PLL3_P,
128 [_PLL3_Q] = PLL3_Q,
129 [_PLL3_R] = PLL3_R,
130 [_PLL4_P] = PLL4_P,
131 [_PLL4_Q] = PLL4_Q,
132 [_PLL4_R] = PLL4_R,
133 [_ACLK] = CK_AXI,
134 [_PCLK1] = CK_AXI,
135 [_PCLK2] = CK_AXI,
136 [_PCLK3] = CK_AXI,
137 [_PCLK4] = CK_AXI,
138 [_PCLK5] = CK_AXI,
139 [_HCLK5] = CK_AXI,
140 [_HCLK6] = CK_AXI,
141 [_HCLK2] = CK_AXI,
142 [_CK_PER] = CK_PER,
143 [_CK_MPU] = CK_MPU,
144 [_CK_MCU] = CK_MCU,
145 };
146
clock_id2parent_id(unsigned long id)147 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id)
148 {
149 size_t n = 0;
150
151 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID);
152
153 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++)
154 if (parent_id_clock_id[n] == id)
155 return (enum stm32mp1_parent_id)n;
156
157 return _UNKNOWN_ID;
158 }
159
160 /* Identifiers for PLLs and their configuration resources */
161 enum stm32mp1_pll_id {
162 _PLL1,
163 _PLL2,
164 _PLL3,
165 _PLL4,
166 _PLL_NB
167 };
168
169 enum stm32mp1_div_id {
170 _DIV_P,
171 _DIV_Q,
172 _DIV_R,
173 _DIV_NB,
174 };
175
176 enum stm32mp1_plltype {
177 PLL_800,
178 PLL_1600,
179 PLL_TYPE_NB
180 };
181
182 /*
183 * Clock generic gates clocks which state is controlled by a single RCC bit
184 *
185 * @offset: RCC register byte offset from RCC base where clock is controlled
186 * @bit: Bit position in the RCC 32bit register
187 * @clock_id: Identifier used for the clock in the clock driver API
188 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register
189 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register)
190 * @secure: One of N_S or SEC, defined below
191 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector
192 * (8bit storage of ID from enum stm32mp1_parent_sel)
193 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock
194 * (8bit storage of ID from enum stm32mp1_parent_id)
195 */
196 struct stm32mp1_clk_gate {
197 uint16_t offset;
198 uint8_t bit;
199 uint8_t clock_id;
200 uint8_t set_clr;
201 uint8_t secure;
202 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
203 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
204 };
205
206 /* Parent clock selection: select register info, parent clocks references */
207 struct stm32mp1_clk_sel {
208 uint16_t offset;
209 uint8_t src;
210 uint8_t msk;
211 uint8_t nb_parent;
212 const uint8_t *parent;
213 };
214
215 #define REFCLK_SIZE 4
216 /* PLL control: type, control register offsets, up-to-4 selectable parent */
217 struct stm32mp1_clk_pll {
218 enum stm32mp1_plltype plltype;
219 uint16_t rckxselr;
220 uint16_t pllxcfgr1;
221 uint16_t pllxcfgr2;
222 uint16_t pllxfracr;
223 uint16_t pllxcr;
224 uint16_t pllxcsgr;
225 enum stm32mp_osc_id refclk[REFCLK_SIZE];
226 };
227
228 #define N_S 0 /* Non-secure can access RCC interface */
229 #define SEC 1 /* RCC[TZEN] protects RCC interface */
230
231 /* Clocks with selectable source and not set/clr register access */
232 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \
233 { \
234 .offset = (_offset), \
235 .bit = (_bit), \
236 .clock_id = (_clock_id), \
237 .set_clr = 0, \
238 .secure = (_sec), \
239 .sel = (_parent_sel), \
240 .fixed = _UNKNOWN_ID, \
241 }
242
243 /* Clocks with fixed source and not set/clr register access */
244 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \
245 { \
246 .offset = (_offset), \
247 .bit = (_bit), \
248 .clock_id = (_clock_id), \
249 .set_clr = 0, \
250 .secure = (_sec), \
251 .sel = _UNKNOWN_SEL, \
252 .fixed = (_parent), \
253 }
254
255 /* Clocks with selectable source and set/clr register access */
256 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \
257 { \
258 .offset = (_offset), \
259 .bit = (_bit), \
260 .clock_id = (_clock_id), \
261 .set_clr = 1, \
262 .secure = (_sec), \
263 .sel = (_parent_sel), \
264 .fixed = _UNKNOWN_ID, \
265 }
266
267 /* Clocks with fixed source and set/clr register access */
268 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \
269 { \
270 .offset = (_offset), \
271 .bit = (_bit), \
272 .clock_id = (_clock_id), \
273 .set_clr = 1, \
274 .secure = (_sec), \
275 .sel = _UNKNOWN_SEL, \
276 .fixed = (_parent), \
277 }
278
279 /*
280 * Clocks with selectable source and set/clr register access
281 * and enable bit position defined by a label (argument _bit)
282 */
283 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \
284 { \
285 .offset = (_offset), \
286 .clock_id = (_clock_id), \
287 .bit = _offset ## _ ## _bit ## _POS, \
288 .set_clr = 1, \
289 .secure = (_sec), \
290 .sel = (_parent_sel), \
291 .fixed = _UNKNOWN_ID, \
292 }
293 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \
294 { \
295 .offset = (_offset), \
296 .clock_id = (_clock_id), \
297 .bit = _offset ## _ ## _bit ## _POS, \
298 .set_clr = 1, \
299 .secure = (_sec), \
300 .sel = _UNKNOWN_SEL, \
301 .fixed = (_parent), \
302 }
303
304 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \
305 [(idx)] = { \
306 .offset = (_offset), \
307 .src = (_src), \
308 .msk = (_mask), \
309 .parent = (_parent), \
310 .nb_parent = ARRAY_SIZE(_parent) \
311 }
312
313 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \
314 _off5, _off6, _p1, _p2, _p3, _p4) \
315 [(_idx)] = { \
316 .plltype = (_type), \
317 .rckxselr = (_off1), \
318 .pllxcfgr1 = (_off2), \
319 .pllxcfgr2 = (_off3), \
320 .pllxfracr = (_off4), \
321 .pllxcr = (_off5), \
322 .pllxcsgr = (_off6), \
323 .refclk[0] = (_p1), \
324 .refclk[1] = (_p2), \
325 .refclk[2] = (_p3), \
326 .refclk[3] = (_p4), \
327 }
328
329 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
330
331 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
332 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK),
333 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
334 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK),
335 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
336 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
337 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
338 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
339 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
340 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK),
341 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
342 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
343
344 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL),
345 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL),
346 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL),
347 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL),
348 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5),
349 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5),
350 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5),
351 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5),
352 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5),
353 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5),
354 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL),
355
356 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5),
357 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5),
358 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5),
359 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL),
360 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _HCLK5),
361
362 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6),
363
364 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL),
365
366 /* Non-secure clocks */
367 #ifdef CFG_WITH_NSEC_I2CS
368 _CLK_SC2_SELEC(N_S, RCC_MP_APB1ENSETR, I2C5EN, I2C5_K, _I2C35_SEL),
369 #endif
370
371 #ifdef CFG_WITH_NSEC_GPIOS
372 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID),
373 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID),
374 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID),
375 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID),
376 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID),
377 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID),
378 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID),
379 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID),
380 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID),
381 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID),
382 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID),
383 #endif
384 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
385 #ifdef CFG_WITH_NSEC_UARTS
386 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
387 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
388 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
389 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
390 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
391 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
392 #endif
393 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
394 #ifdef CFG_WITH_NSEC_UARTS
395 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
396 #endif
397 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
398 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
399 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
400
401 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
402 };
403 DECLARE_KEEP_PAGER(stm32mp1_clk_gate);
404
405 const uint8_t stm32mp1_clk_on[] = {
406 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2,
407 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R,
408 CK_AXI, CK_MPU, CK_MCU,
409 };
410
411 /* Parents for secure aware clocks in the xxxSELR value ordering */
412 static const uint8_t stgen_parents[] = {
413 _HSI_KER, _HSE_KER
414 };
415
416 #ifdef CFG_WITH_NSEC_I2CS
417 static const uint8_t i2c35_parents[] = {
418 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
419 };
420 #endif
421
422 static const uint8_t i2c46_parents[] = {
423 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
424 };
425
426 static const uint8_t spi6_parents[] = {
427 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
428 };
429
430 static const uint8_t usart1_parents[] = {
431 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
432 };
433
434 static const uint8_t rng1_parents[] = {
435 _CSI, _PLL4_R, _LSE, _LSI
436 };
437
438 static const uint8_t mpu_parents[] = {
439 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
440 };
441
442 /* Parents for (some) non-secure clocks */
443 #ifdef CFG_WITH_NSEC_UARTS
444 static const uint8_t uart6_parents[] = {
445 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
446 };
447
448 static const uint8_t uart234578_parents[] = {
449 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
450 };
451 #endif
452
453 static const uint8_t axiss_parents[] = {
454 _HSI, _HSE, _PLL2_P
455 };
456
457 static const uint8_t mcuss_parents[] = {
458 _HSI, _HSE, _CSI, _PLL3_P
459 };
460
461 static const uint8_t rtc_parents[] = {
462 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC
463 };
464
465 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
466 /* Secure aware clocks */
467 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
468 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
469 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
470 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents),
471 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents),
472 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 16, 0x3, rtc_parents),
473 _CLK_PARENT(_MPU_SEL, RCC_MPCKSELR, 0, 0x3, mpu_parents),
474 /* Always non-secure clocks (maybe used in some way in secure world) */
475 #ifdef CFG_WITH_NSEC_I2CS
476 _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
477 #endif
478 #ifdef CFG_WITH_NSEC_UARTS
479 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
480 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents),
481 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents),
482 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents),
483 #endif
484 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents),
485 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents),
486 };
487
488 /* PLLNCFGR2 register divider by output */
489 static const uint8_t pllncfgr2[_DIV_NB] = {
490 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
491 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
492 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
493 };
494
495 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
496 _CLK_PLL(_PLL1, PLL_1600,
497 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
498 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
499 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
500 _CLK_PLL(_PLL2, PLL_1600,
501 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
502 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
503 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
504 _CLK_PLL(_PLL3, PLL_800,
505 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
506 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
507 OSC_HSI, OSC_HSE, OSC_CSI, _UNKNOWN_OSC_ID),
508 _CLK_PLL(_PLL4, PLL_800,
509 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
510 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
511 OSC_HSI, OSC_HSE, OSC_CSI, OSC_I2S_CKIN),
512 };
513
514 /* Prescaler table lookups for clock computation */
515 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
516 static const uint8_t stm32mp1_mcu_div[16] = {
517 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
518 };
519
520 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
521 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
522 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
523 static const uint8_t stm32mp1_mpu_apbx_div[8] = {
524 0, 1, 2, 3, 4, 4, 4, 4
525 };
526
527 /* div = /1 /2 /3 /4 */
528 static const uint8_t stm32mp1_axi_div[8] = {
529 1, 2, 3, 4, 4, 4, 4, 4
530 };
531
532 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = {
533 [_HSI] = "HSI",
534 [_HSE] = "HSE",
535 [_CSI] = "CSI",
536 [_LSI] = "LSI",
537 [_LSE] = "LSE",
538 [_I2S_CKIN] = "I2S_CKIN",
539 [_HSI_KER] = "HSI_KER",
540 [_HSE_KER] = "HSE_KER",
541 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
542 [_HSE_RTC] = "HSE_RTC",
543 [_CSI_KER] = "CSI_KER",
544 [_PLL1_P] = "PLL1_P",
545 [_PLL1_Q] = "PLL1_Q",
546 [_PLL1_R] = "PLL1_R",
547 [_PLL2_P] = "PLL2_P",
548 [_PLL2_Q] = "PLL2_Q",
549 [_PLL2_R] = "PLL2_R",
550 [_PLL3_P] = "PLL3_P",
551 [_PLL3_Q] = "PLL3_Q",
552 [_PLL3_R] = "PLL3_R",
553 [_PLL4_P] = "PLL4_P",
554 [_PLL4_Q] = "PLL4_Q",
555 [_PLL4_R] = "PLL4_R",
556 [_ACLK] = "ACLK",
557 [_PCLK1] = "PCLK1",
558 [_PCLK2] = "PCLK2",
559 [_PCLK3] = "PCLK3",
560 [_PCLK4] = "PCLK4",
561 [_PCLK5] = "PCLK5",
562 [_HCLK2] = "HCLK2",
563 [_HCLK5] = "HCLK5",
564 [_HCLK6] = "HCLK6",
565 [_CK_PER] = "CK_PER",
566 [_CK_MPU] = "CK_MPU",
567 [_CK_MCU] = "CK_MCU",
568 [_USB_PHY_48] = "USB_PHY_48",
569 };
570
571 /*
572 * Oscillator frequency in Hz. This array shall be initialized
573 * according to platform.
574 */
575 static unsigned long stm32mp1_osc[NB_OSC];
576
osc_frequency(enum stm32mp_osc_id idx)577 static unsigned long osc_frequency(enum stm32mp_osc_id idx)
578 {
579 if (idx >= ARRAY_SIZE(stm32mp1_osc)) {
580 DMSG("clk id %d not found", idx);
581 return 0;
582 }
583
584 return stm32mp1_osc[idx];
585 }
586
gate_ref(unsigned int idx)587 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
588 {
589 return &stm32mp1_clk_gate[idx];
590 }
591
clk_sel_ref(unsigned int idx)592 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
593 {
594 return &stm32mp1_clk_sel[idx];
595 }
596
pll_ref(unsigned int idx)597 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
598 {
599 return &stm32mp1_clk_pll[idx];
600 }
601
stm32mp1_clk_get_gated_id(unsigned long id)602 static int stm32mp1_clk_get_gated_id(unsigned long id)
603 {
604 unsigned int i = 0;
605
606 for (i = 0; i < NB_GATES; i++)
607 if (gate_ref(i)->clock_id == id)
608 return i;
609
610 DMSG("clk id %lu not found", id);
611 return -1;
612 }
613
stm32mp1_clk_get_sel(int i)614 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
615 {
616 return (enum stm32mp1_parent_sel)gate_ref(i)->sel;
617 }
618
stm32mp1_clk_get_fixed_parent(int i)619 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
620 {
621 return (enum stm32mp1_parent_id)gate_ref(i)->fixed;
622 }
623
stm32mp1_clk_get_parent(unsigned long id)624 static int stm32mp1_clk_get_parent(unsigned long id)
625 {
626 const struct stm32mp1_clk_sel *sel = NULL;
627 enum stm32mp1_parent_id parent_id = 0;
628 uint32_t p_sel = 0;
629 int i = 0;
630 enum stm32mp1_parent_id p = _UNKNOWN_ID;
631 enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
632 vaddr_t rcc_base = stm32_rcc_base();
633
634 parent_id = clock_id2parent_id(id);
635 if (parent_id != _UNKNOWN_ID)
636 return (int)parent_id;
637
638 i = stm32mp1_clk_get_gated_id(id);
639 if (i < 0)
640 panic();
641
642 p = stm32mp1_clk_get_fixed_parent(i);
643 if (p < _PARENT_NB)
644 return (int)p;
645
646 s = stm32mp1_clk_get_sel(i);
647 if (s == _UNKNOWN_SEL)
648 return -1;
649 if (s >= _PARENT_SEL_NB)
650 panic();
651
652 sel = clk_sel_ref(s);
653 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk;
654 if (p_sel < sel->nb_parent)
655 return (int)sel->parent[p_sel];
656
657 DMSG("No parent selected for clk %lu", id);
658 return -1;
659 }
660
stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll * pll)661 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
662 {
663 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr);
664 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
665
666 return osc_frequency(pll->refclk[src]);
667 }
668
669 /*
670 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
671 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
672 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
673 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
674 */
stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll * pll)675 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
676 {
677 unsigned long refclk = 0;
678 unsigned long fvco = 0;
679 uint32_t cfgr1 = 0;
680 uint32_t fracr = 0;
681 uint32_t divm = 0;
682 uint32_t divn = 0;
683
684 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1);
685 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr);
686
687 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT;
688 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
689
690 refclk = stm32mp1_pll_get_fref(pll);
691
692 /*
693 * With FRACV :
694 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
695 * Without FRACV
696 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
697 */
698 if (fracr & RCC_PLLNFRACR_FRACLE) {
699 unsigned long long numerator = 0;
700 unsigned long long denominator = 0;
701 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
702 RCC_PLLNFRACR_FRACV_SHIFT;
703
704 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
705 numerator = refclk * numerator;
706 denominator = ((unsigned long long)divm + 1U) << 13;
707 fvco = (unsigned long)(numerator / denominator);
708 } else {
709 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
710 }
711
712 return fvco;
713 }
714
stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,enum stm32mp1_div_id div_id)715 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
716 enum stm32mp1_div_id div_id)
717 {
718 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
719 unsigned long dfout = 0;
720 uint32_t cfgr2 = 0;
721 uint32_t divy = 0;
722
723 if (div_id >= _DIV_NB)
724 return 0;
725
726 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2);
727 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
728
729 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
730
731 return dfout;
732 }
733
get_clock_rate(enum stm32mp1_parent_id p)734 static unsigned long get_clock_rate(enum stm32mp1_parent_id p)
735 {
736 uint32_t reg = 0;
737 unsigned long clock = 0;
738 vaddr_t rcc_base = stm32_rcc_base();
739
740 switch (p) {
741 case _CK_MPU:
742 /* MPU sub system */
743 reg = io_read32(rcc_base + RCC_MPCKSELR);
744 switch (reg & RCC_SELR_SRC_MASK) {
745 case RCC_MPCKSELR_HSI:
746 clock = osc_frequency(OSC_HSI);
747 break;
748 case RCC_MPCKSELR_HSE:
749 clock = osc_frequency(OSC_HSE);
750 break;
751 case RCC_MPCKSELR_PLL:
752 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
753 break;
754 case RCC_MPCKSELR_PLL_MPUDIV:
755 reg = io_read32(rcc_base + RCC_MPCKDIVR);
756 if (reg & RCC_MPUDIV_MASK)
757 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >>
758 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK];
759 else
760 clock = 0;
761 break;
762 default:
763 break;
764 }
765 break;
766 /* AXI sub system */
767 case _ACLK:
768 case _HCLK2:
769 case _HCLK5:
770 case _HCLK6:
771 case _PCLK4:
772 case _PCLK5:
773 reg = io_read32(rcc_base + RCC_ASSCKSELR);
774 switch (reg & RCC_SELR_SRC_MASK) {
775 case RCC_ASSCKSELR_HSI:
776 clock = osc_frequency(OSC_HSI);
777 break;
778 case RCC_ASSCKSELR_HSE:
779 clock = osc_frequency(OSC_HSE);
780 break;
781 case RCC_ASSCKSELR_PLL:
782 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
783 break;
784 default:
785 break;
786 }
787
788 /* System clock divider */
789 reg = io_read32(rcc_base + RCC_AXIDIVR);
790 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
791
792 switch (p) {
793 case _PCLK4:
794 reg = io_read32(rcc_base + RCC_APB4DIVR);
795 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
796 break;
797 case _PCLK5:
798 reg = io_read32(rcc_base + RCC_APB5DIVR);
799 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
800 break;
801 default:
802 break;
803 }
804 break;
805 /* MCU sub system */
806 case _CK_MCU:
807 case _PCLK1:
808 case _PCLK2:
809 case _PCLK3:
810 reg = io_read32(rcc_base + RCC_MSSCKSELR);
811 switch (reg & RCC_SELR_SRC_MASK) {
812 case RCC_MSSCKSELR_HSI:
813 clock = osc_frequency(OSC_HSI);
814 break;
815 case RCC_MSSCKSELR_HSE:
816 clock = osc_frequency(OSC_HSE);
817 break;
818 case RCC_MSSCKSELR_CSI:
819 clock = osc_frequency(OSC_CSI);
820 break;
821 case RCC_MSSCKSELR_PLL:
822 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
823 break;
824 default:
825 break;
826 }
827
828 /* MCU clock divider */
829 reg = io_read32(rcc_base + RCC_MCUDIVR);
830 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
831
832 switch (p) {
833 case _PCLK1:
834 reg = io_read32(rcc_base + RCC_APB1DIVR);
835 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
836 break;
837 case _PCLK2:
838 reg = io_read32(rcc_base + RCC_APB2DIVR);
839 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
840 break;
841 case _PCLK3:
842 reg = io_read32(rcc_base + RCC_APB3DIVR);
843 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
844 break;
845 case _CK_MCU:
846 default:
847 break;
848 }
849 break;
850 case _CK_PER:
851 reg = io_read32(rcc_base + RCC_CPERCKSELR);
852 switch (reg & RCC_SELR_SRC_MASK) {
853 case RCC_CPERCKSELR_HSI:
854 clock = osc_frequency(OSC_HSI);
855 break;
856 case RCC_CPERCKSELR_HSE:
857 clock = osc_frequency(OSC_HSE);
858 break;
859 case RCC_CPERCKSELR_CSI:
860 clock = osc_frequency(OSC_CSI);
861 break;
862 default:
863 break;
864 }
865 break;
866 case _HSI:
867 case _HSI_KER:
868 clock = osc_frequency(OSC_HSI);
869 break;
870 case _CSI:
871 case _CSI_KER:
872 clock = osc_frequency(OSC_CSI);
873 break;
874 case _HSE:
875 case _HSE_KER:
876 clock = osc_frequency(OSC_HSE);
877 break;
878 case _HSE_KER_DIV2:
879 clock = osc_frequency(OSC_HSE) >> 1;
880 break;
881 case _HSE_RTC:
882 clock = osc_frequency(OSC_HSE);
883 clock /= (io_read32(rcc_base + RCC_RTCDIVR) &
884 RCC_DIVR_DIV_MASK) + 1;
885 break;
886 case _LSI:
887 clock = osc_frequency(OSC_LSI);
888 break;
889 case _LSE:
890 clock = osc_frequency(OSC_LSE);
891 break;
892 /* PLL */
893 case _PLL1_P:
894 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
895 break;
896 case _PLL1_Q:
897 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
898 break;
899 case _PLL1_R:
900 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
901 break;
902 case _PLL2_P:
903 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
904 break;
905 case _PLL2_Q:
906 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
907 break;
908 case _PLL2_R:
909 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
910 break;
911 case _PLL3_P:
912 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
913 break;
914 case _PLL3_Q:
915 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
916 break;
917 case _PLL3_R:
918 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
919 break;
920 case _PLL4_P:
921 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
922 break;
923 case _PLL4_Q:
924 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
925 break;
926 case _PLL4_R:
927 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
928 break;
929 /* Other */
930 case _USB_PHY_48:
931 clock = osc_frequency(OSC_USB_PHY_48);
932 break;
933 default:
934 break;
935 }
936
937 return clock;
938 }
939
__clk_enable(const struct stm32mp1_clk_gate * gate)940 static void __clk_enable(const struct stm32mp1_clk_gate *gate)
941 {
942 vaddr_t base = stm32_rcc_base();
943 uint32_t bit = BIT(gate->bit);
944
945 if (gate->set_clr)
946 io_write32(base + gate->offset, bit);
947 else
948 io_setbits32_stm32shregs(base + gate->offset, bit);
949
950 FMSG("Clock %u has been enabled", gate->clock_id);
951 }
952
__clk_disable(const struct stm32mp1_clk_gate * gate)953 static void __clk_disable(const struct stm32mp1_clk_gate *gate)
954 {
955 vaddr_t base = stm32_rcc_base();
956 uint32_t bit = BIT(gate->bit);
957
958 if (gate->set_clr)
959 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit);
960 else
961 io_clrbits32_stm32shregs(base + gate->offset, bit);
962
963 FMSG("Clock %u has been disabled", gate->clock_id);
964 }
965
get_timer_rate(long parent_rate,unsigned int apb_bus)966 static long get_timer_rate(long parent_rate, unsigned int apb_bus)
967 {
968 uint32_t timgxpre = 0;
969 uint32_t apbxdiv = 0;
970 vaddr_t rcc_base = stm32_rcc_base();
971
972 switch (apb_bus) {
973 case 1:
974 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) &
975 RCC_APBXDIV_MASK;
976 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) &
977 RCC_TIMGXPRER_TIMGXPRE;
978 break;
979 case 2:
980 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) &
981 RCC_APBXDIV_MASK;
982 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) &
983 RCC_TIMGXPRER_TIMGXPRE;
984 break;
985 default:
986 panic();
987 break;
988 }
989
990 if (apbxdiv == 0)
991 return parent_rate;
992
993 return parent_rate * (timgxpre + 1) * 2;
994 }
995
_stm32_clock_get_rate(unsigned long id)996 static unsigned long _stm32_clock_get_rate(unsigned long id)
997 {
998 enum stm32mp1_parent_id p = _UNKNOWN_ID;
999 unsigned long rate = 0;
1000
1001 p = stm32mp1_clk_get_parent(id);
1002 if (p < 0)
1003 return 0;
1004
1005 rate = get_clock_rate(p);
1006
1007 if ((id >= TIM2_K) && (id <= TIM14_K))
1008 rate = get_timer_rate(rate, 1);
1009
1010 if ((id >= TIM1_K) && (id <= TIM17_K))
1011 rate = get_timer_rate(rate, 2);
1012
1013 return rate;
1014 }
1015
1016 static const char *stm32mp_osc_node_label[NB_OSC] = {
1017 [OSC_LSI] = "clk-lsi",
1018 [OSC_LSE] = "clk-lse",
1019 [OSC_HSI] = "clk-hsi",
1020 [OSC_HSE] = "clk-hse",
1021 [OSC_CSI] = "clk-csi",
1022 [OSC_I2S_CKIN] = "i2s_ckin",
1023 [OSC_USB_PHY_48] = "ck_usbo_48m"
1024 };
1025
clk_freq_prop(const void * fdt,int node)1026 static unsigned int clk_freq_prop(const void *fdt, int node)
1027 {
1028 const fdt32_t *cuint = NULL;
1029 int ret = 0;
1030
1031 /* Disabled clocks report null rate */
1032 if (fdt_get_status(fdt, node) == DT_STATUS_DISABLED)
1033 return 0;
1034
1035 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret);
1036 if (!cuint)
1037 panic();
1038
1039 return fdt32_to_cpu(*cuint);
1040 }
1041
get_osc_freq_from_dt(const void * fdt)1042 static void get_osc_freq_from_dt(const void *fdt)
1043 {
1044 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID;
1045 int clk_node = fdt_path_offset(fdt, "/clocks");
1046
1047 if (clk_node < 0)
1048 panic();
1049
1050 COMPILE_TIME_ASSERT((int)OSC_HSI == 0);
1051 for (idx = OSC_HSI; idx < NB_OSC; idx++) {
1052 const char *name = stm32mp_osc_node_label[idx];
1053 int subnode = 0;
1054
1055 fdt_for_each_subnode(subnode, fdt, clk_node) {
1056 const char *cchar = NULL;
1057 int ret = 0;
1058
1059 cchar = fdt_get_name(fdt, subnode, &ret);
1060 if (!cchar)
1061 panic();
1062
1063 if (strncmp(cchar, name, (size_t)ret) == 0) {
1064 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode);
1065
1066 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]);
1067 break;
1068 }
1069 }
1070
1071 if (!stm32mp1_osc[idx])
1072 DMSG("Osc %s: no frequency info", name);
1073 }
1074 }
1075
enable_static_secure_clocks(void)1076 static void enable_static_secure_clocks(void)
1077 {
1078 unsigned int idx = 0;
1079 const unsigned long secure_enable[] = {
1080 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB,
1081 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K,
1082 BSEC,
1083 };
1084
1085 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++)
1086 clk_enable(stm32mp_rcc_clock_id_to_clk(secure_enable[idx]));
1087
1088 if (CFG_TEE_CORE_NB_CORE > 1)
1089 clk_enable(stm32mp_rcc_clock_id_to_clk(RTCAPB));
1090 }
1091
enable_rcc_tzen(void)1092 static void __maybe_unused enable_rcc_tzen(void)
1093 {
1094 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN);
1095 }
1096
disable_rcc_tzen(void)1097 static void __maybe_unused disable_rcc_tzen(void)
1098 {
1099 IMSG("RCC is non-secure");
1100 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN);
1101 }
1102
stm32mp1_clk_fdt_init(const void * fdt,int node)1103 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node)
1104 {
1105 unsigned int i = 0;
1106 int len = 0;
1107 int ignored = 0;
1108
1109 get_osc_freq_from_dt(fdt);
1110
1111 /*
1112 * OP-TEE core is not in charge of configuring clock parenthood.
1113 * This is expected from an earlier boot stage. Modifying the clock
1114 * tree parenthood here may jeopardize already configured clocks.
1115 * The sequence below ignores such DT directives with a friendly
1116 * debug trace.
1117 */
1118 if (fdt_getprop(fdt, node, "st,clksrc", &len)) {
1119 DMSG("Ignore source clocks configuration from DT");
1120 ignored++;
1121 }
1122 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) {
1123 DMSG("Ignore clock divisors configuration from DT");
1124 ignored++;
1125 }
1126 if (fdt_getprop(fdt, node, "st,pkcs", &len)) {
1127 DMSG("Ignore peripheral clocks tree configuration from DT");
1128 ignored++;
1129 }
1130 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1131 char name[] = "st,pll@X";
1132
1133 snprintf(name, sizeof(name), "st,pll@%d", i);
1134 node = fdt_subnode_offset(fdt, node, name);
1135 if (node < 0)
1136 continue;
1137
1138 if (fdt_getprop(fdt, node, "cfg", &len) ||
1139 fdt_getprop(fdt, node, "frac", &len)) {
1140 DMSG("Ignore PLL%u configurations from DT", i);
1141 ignored++;
1142 }
1143 }
1144
1145 if (ignored != 0)
1146 IMSG("DT clock tree configurations were ignored");
1147
1148 return TEE_SUCCESS;
1149 }
1150
1151 /*
1152 * Conversion between clk references and clock gates and clock on internals
1153 *
1154 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering.
1155 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering.
1156 */
1157 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) +
1158 ARRAY_SIZE(stm32mp1_clk_on)];
1159
1160 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate))
1161
clk_is_gate(struct clk * clk)1162 static bool clk_is_gate(struct clk *clk)
1163 {
1164 int clk_index = clk - stm32mp1_clk;
1165
1166 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk));
1167 return clk_index < CLK_ON_INDEX_OFFSET;
1168 }
1169
clk_to_clock_id(struct clk * clk)1170 static unsigned long clk_to_clock_id(struct clk *clk)
1171 {
1172 int gate_index = clk - stm32mp1_clk;
1173 int on_index = gate_index - CLK_ON_INDEX_OFFSET;
1174
1175 if (clk_is_gate(clk))
1176 return stm32mp1_clk_gate[gate_index].clock_id;
1177
1178 return stm32mp1_clk_on[on_index];
1179 }
1180
clk_to_gate_ref(struct clk * clk)1181 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk)
1182 {
1183 int gate_index = clk - stm32mp1_clk;
1184
1185 assert(clk_is_gate(clk));
1186
1187 return stm32mp1_clk_gate + gate_index;
1188 }
1189
clock_id_to_gate_index(unsigned long clock_id)1190 static int clock_id_to_gate_index(unsigned long clock_id)
1191 {
1192 size_t n = 0;
1193
1194 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++)
1195 if (stm32mp1_clk_gate[n].clock_id == clock_id)
1196 return n;
1197
1198 return -1;
1199 }
1200
clock_id_to_always_on_index(unsigned long clock_id)1201 static int clock_id_to_always_on_index(unsigned long clock_id)
1202 {
1203 size_t n = 0;
1204
1205 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++)
1206 if (stm32mp1_clk_on[n] == clock_id)
1207 return n;
1208
1209 return -1;
1210 }
1211
clock_id_to_clk(unsigned long clock_id)1212 static struct clk *clock_id_to_clk(unsigned long clock_id)
1213 {
1214 int gate_index = clock_id_to_gate_index(clock_id);
1215 int on_index = clock_id_to_always_on_index(clock_id);
1216
1217 if (gate_index >= 0)
1218 return stm32mp1_clk + gate_index;
1219
1220 if (on_index >= 0)
1221 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index;
1222
1223 return NULL;
1224 }
1225
stm32mp_rcc_clock_id_to_clk(unsigned long clock_id)1226 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id)
1227 {
1228 return clock_id_to_clk(clock_id);
1229 }
1230
1231 #if (CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG) && defined(CFG_TEE_CORE_DEBUG)
1232 struct clk_name {
1233 unsigned int clock_id;
1234 const char *name;
1235 };
1236
1237 #define CLOCK_NAME(_binding, _name) \
1238 { .clock_id = (_binding), .name = (_name) }
1239
1240 /* Store names only for some clocks */
1241 const struct clk_name exposed_clk_name[] = {
1242 /* Clocks used by platform drivers not yet probed from DT */
1243 CLOCK_NAME(CK_DBG, "dbg"),
1244 CLOCK_NAME(CK_MCU, "mcu"),
1245 CLOCK_NAME(RTCAPB, "rtcapb"),
1246 CLOCK_NAME(BKPSRAM, "bkpsram"),
1247 CLOCK_NAME(RTC, "rtc"),
1248 CLOCK_NAME(CRYP1, "crpy1"),
1249 CLOCK_NAME(SYSCFG, "syscfg"),
1250 CLOCK_NAME(GPIOA, "gpioa"),
1251 CLOCK_NAME(GPIOB, "gpiob"),
1252 CLOCK_NAME(GPIOC, "gpioc"),
1253 CLOCK_NAME(GPIOD, "gpiod"),
1254 CLOCK_NAME(GPIOE, "gpioe"),
1255 CLOCK_NAME(GPIOF, "gpiof"),
1256 CLOCK_NAME(GPIOG, "gpiog"),
1257 CLOCK_NAME(GPIOH, "gpioh"),
1258 CLOCK_NAME(GPIOI, "gpioi"),
1259 CLOCK_NAME(GPIOJ, "gpioj"),
1260 CLOCK_NAME(GPIOK, "gpiok"),
1261 CLOCK_NAME(GPIOZ, "gpioz"),
1262 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */
1263 CLOCK_NAME(CK_HSE, "hse"),
1264 CLOCK_NAME(CK_HSI, "hsi"),
1265 CLOCK_NAME(CK_CSI, "csi"),
1266 CLOCK_NAME(CK_LSE, "lse"),
1267 CLOCK_NAME(CK_LSI, "lsi"),
1268 CLOCK_NAME(PLL2_Q, "pll2q"),
1269 CLOCK_NAME(PLL2_R, "pll2r"),
1270 CLOCK_NAME(PLL3_Q, "pll3q"),
1271 CLOCK_NAME(PLL3_R, "pll3r"),
1272 CLOCK_NAME(CRYP1, "cryp1"),
1273 CLOCK_NAME(HASH1, "hash1"),
1274 CLOCK_NAME(I2C4_K, "i2c4"),
1275 CLOCK_NAME(I2C6_K, "i2c6"),
1276 CLOCK_NAME(IWDG1, "iwdg"),
1277 CLOCK_NAME(RNG1_K, "rng1"),
1278 CLOCK_NAME(SPI6_K, "spi6"),
1279 CLOCK_NAME(USART1_K, "usart1"),
1280 CLOCK_NAME(CK_MCU, "mcu"),
1281 };
1282 DECLARE_KEEP_PAGER(exposed_clk_name);
1283
clk_op_get_name(struct clk * clk)1284 static const char *clk_op_get_name(struct clk *clk)
1285 {
1286 unsigned long clock_id = clk_to_clock_id(clk);
1287 size_t n = 0;
1288
1289 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++)
1290 if (exposed_clk_name[n].clock_id == clock_id)
1291 return exposed_clk_name[n].name;
1292
1293 return NULL;
1294 }
1295 #else
clk_op_get_name(struct clk * clk __unused)1296 static const char *clk_op_get_name(struct clk *clk __unused)
1297 {
1298 return NULL;
1299 }
1300 #endif /*CFG_TEE_CORE_LOG_LEVEL*/
1301
clk_op_compute_rate(struct clk * clk,unsigned long parent_rate __unused)1302 static unsigned long clk_op_compute_rate(struct clk *clk,
1303 unsigned long parent_rate __unused)
1304 {
1305 return _stm32_clock_get_rate(clk_to_clock_id(clk));
1306 }
1307
clk_op_enable(struct clk * clk)1308 static TEE_Result clk_op_enable(struct clk *clk)
1309 {
1310 if (clk_is_gate(clk)) {
1311 __clk_enable(clk_to_gate_ref(clk));
1312
1313 /* Make sure the clock is enabled before returning to caller */
1314 dsb();
1315 }
1316
1317 return TEE_SUCCESS;
1318 }
1319 DECLARE_KEEP_PAGER(clk_op_enable);
1320
clk_op_disable(struct clk * clk)1321 static void clk_op_disable(struct clk *clk)
1322 {
1323 if (clk_is_gate(clk)) {
1324 /* Make sure the previous operations are visible */
1325 dsb();
1326
1327 __clk_disable(clk_to_gate_ref(clk));
1328 }
1329 }
1330 DECLARE_KEEP_PAGER(clk_op_disable);
1331
1332 /* This variable is weak to break its dependency chain when linked as unpaged */
1333 const struct clk_ops stm32mp1_clk_ops
1334 __weak __relrodata_unpaged("stm32mp1_clk_ops") = {
1335 .enable = clk_op_enable,
1336 .disable = clk_op_disable,
1337 .get_rate = clk_op_compute_rate,
1338 };
1339
register_stm32mp1_clocks(void)1340 static TEE_Result register_stm32mp1_clocks(void)
1341 {
1342 TEE_Result res = TEE_ERROR_GENERIC;
1343 size_t n = 0;
1344
1345 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) {
1346 stm32mp1_clk[n].ops = &stm32mp1_clk_ops;
1347 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n);
1348 refcount_set(&stm32mp1_clk[n].enabled_count, 0);
1349
1350 res = clk_register(stm32mp1_clk + n);
1351 if (res)
1352 return res;
1353 }
1354
1355 return TEE_SUCCESS;
1356 }
1357
stm32mp1_clk_dt_get_clk(struct dt_pargs * pargs,void * data __unused,struct clk ** out_clk)1358 static TEE_Result stm32mp1_clk_dt_get_clk(struct dt_pargs *pargs,
1359 void *data __unused,
1360 struct clk **out_clk)
1361 {
1362 unsigned long clock_id = pargs->args[0];
1363 struct clk *clk = NULL;
1364
1365 if (pargs->args_count != 1)
1366 return TEE_ERROR_BAD_PARAMETERS;
1367
1368 clk = clock_id_to_clk(clock_id);
1369 if (!clk)
1370 return TEE_ERROR_BAD_PARAMETERS;
1371
1372 *out_clk = clk;
1373
1374 return TEE_SUCCESS;
1375 }
1376
1377 /* Non-null reference for compat data */
1378 static const uint8_t non_secure_rcc;
1379
stm32mp1_clock_provider_probe(const void * fdt,int offs,const void * compat_data)1380 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs,
1381 const void *compat_data)
1382 {
1383 TEE_Result res = TEE_ERROR_GENERIC;
1384
1385 if (compat_data == &non_secure_rcc)
1386 disable_rcc_tzen();
1387 else
1388 enable_rcc_tzen();
1389
1390 /*
1391 * Default disable MCKPROT, it may be enabled later from
1392 * STM32 remoteproc driver.
1393 */
1394 stm32_rcc_set_mckprot(false);
1395
1396 res = stm32mp1_clk_fdt_init(fdt, offs);
1397 if (res) {
1398 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res);
1399 panic();
1400 }
1401
1402 res = register_stm32mp1_clocks();
1403 if (res) {
1404 EMSG("Failed to register clocks: %#"PRIx32, res);
1405 panic();
1406 }
1407
1408 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk,
1409 NULL);
1410 if (res) {
1411 EMSG("Failed to register clock provider: %#"PRIx32, res);
1412 panic();
1413 }
1414
1415 enable_static_secure_clocks();
1416
1417 return TEE_SUCCESS;
1418 }
1419
1420 static const struct dt_device_match stm32mp1_clock_match_table[] = {
1421 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, },
1422 { .compatible = "st,stm32mp1-rcc-secure", },
1423 { }
1424 };
1425
1426 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = {
1427 .name = "stm32mp1_clock",
1428 .type = DT_DRIVER_CLK,
1429 .match_table = stm32mp1_clock_match_table,
1430 .probe = stm32mp1_clock_provider_probe,
1431 };
1432