1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35 #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
36
37 struct clk;
38 struct clk_hw;
39 struct clk_core;
40 struct dentry;
41
42 /**
43 * struct clk_rate_request - Structure encoding the clk constraints that
44 * a clock user might require.
45 *
46 * @rate: Requested clock rate. This field will be adjusted by
47 * clock drivers according to hardware capabilities.
48 * @min_rate: Minimum rate imposed by clk users.
49 * @max_rate: Maximum rate imposed by clk users.
50 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
51 * requested constraints.
52 * @best_parent_hw: The most appropriate parent clock that fulfills the
53 * requested constraints.
54 *
55 */
56 struct clk_rate_request {
57 unsigned long rate;
58 unsigned long min_rate;
59 unsigned long max_rate;
60 unsigned long best_parent_rate;
61 struct clk_hw *best_parent_hw;
62 };
63
64 /**
65 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
66 *
67 * @num: Numerator of the duty cycle ratio
68 * @den: Denominator of the duty cycle ratio
69 */
70 struct clk_duty {
71 unsigned int num;
72 unsigned int den;
73 };
74
75 /**
76 * struct clk_ops - Callback operations for hardware clocks; these are to
77 * be provided by the clock implementation, and will be called by drivers
78 * through the clk_* api.
79 *
80 * @prepare: Prepare the clock for enabling. This must not return until
81 * the clock is fully prepared, and it's safe to call clk_enable.
82 * This callback is intended to allow clock implementations to
83 * do any initialisation that may sleep. Called with
84 * prepare_lock held.
85 *
86 * @unprepare: Release the clock from its prepared state. This will typically
87 * undo any work done in the @prepare callback. Called with
88 * prepare_lock held.
89 *
90 * @is_prepared: Queries the hardware to determine if the clock is prepared.
91 * This function is allowed to sleep. Optional, if this op is not
92 * set then the prepare count will be used.
93 *
94 * @unprepare_unused: Unprepare the clock atomically. Only called from
95 * clk_disable_unused for prepare clocks with special needs.
96 * Called with prepare mutex held. This function may sleep.
97 *
98 * @enable: Enable the clock atomically. This must not return until the
99 * clock is generating a valid clock signal, usable by consumer
100 * devices. Called with enable_lock held. This function must not
101 * sleep.
102 *
103 * @disable: Disable the clock atomically. Called with enable_lock held.
104 * This function must not sleep.
105 *
106 * @is_enabled: Queries the hardware to determine if the clock is enabled.
107 * This function must not sleep. Optional, if this op is not
108 * set then the enable count will be used.
109 *
110 * @disable_unused: Disable the clock atomically. Only called from
111 * clk_disable_unused for gate clocks with special needs.
112 * Called with enable_lock held. This function must not
113 * sleep.
114 *
115 * @save_context: Save the context of the clock in prepration for poweroff.
116 *
117 * @restore_context: Restore the context of the clock after a restoration
118 * of power.
119 *
120 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
121 * parent rate is an input parameter. It is up to the caller to
122 * ensure that the prepare_mutex is held across this call.
123 * Returns the calculated rate. Optional, but recommended - if
124 * this op is not set then clock rate will be initialized to 0.
125 *
126 * @round_rate: Given a target rate as input, returns the closest rate actually
127 * supported by the clock. The parent rate is an input/output
128 * parameter.
129 *
130 * @determine_rate: Given a target rate as input, returns the closest rate
131 * actually supported by the clock, and optionally the parent clock
132 * that should be used to provide the clock rate.
133 *
134 * @set_parent: Change the input source of this clock; for clocks with multiple
135 * possible parents specify a new parent by passing in the index
136 * as a u8 corresponding to the parent in either the .parent_names
137 * or .parents arrays. This function in affect translates an
138 * array index into the value programmed into the hardware.
139 * Returns 0 on success, -EERROR otherwise.
140 *
141 * @get_parent: Queries the hardware to determine the parent of a clock. The
142 * return value is a u8 which specifies the index corresponding to
143 * the parent clock. This index can be applied to either the
144 * .parent_names or .parents arrays. In short, this function
145 * translates the parent value read from hardware into an array
146 * index. Currently only called when the clock is initialized by
147 * __clk_init. This callback is mandatory for clocks with
148 * multiple parents. It is optional (and unnecessary) for clocks
149 * with 0 or 1 parents.
150 *
151 * @set_rate: Change the rate of this clock. The requested rate is specified
152 * by the second argument, which should typically be the return
153 * of .round_rate call. The third argument gives the parent rate
154 * which is likely helpful for most .set_rate implementation.
155 * Returns 0 on success, -EERROR otherwise.
156 *
157 * @set_rate_and_parent: Change the rate and the parent of this clock. The
158 * requested rate is specified by the second argument, which
159 * should typically be the return of .round_rate call. The
160 * third argument gives the parent rate which is likely helpful
161 * for most .set_rate_and_parent implementation. The fourth
162 * argument gives the parent index. This callback is optional (and
163 * unnecessary) for clocks with 0 or 1 parents as well as
164 * for clocks that can tolerate switching the rate and the parent
165 * separately via calls to .set_parent and .set_rate.
166 * Returns 0 on success, -EERROR otherwise.
167 *
168 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
169 * is expressed in ppb (parts per billion). The parent accuracy is
170 * an input parameter.
171 * Returns the calculated accuracy. Optional - if this op is not
172 * set then clock accuracy will be initialized to parent accuracy
173 * or 0 (perfect clock) if clock has no parent.
174 *
175 * @get_phase: Queries the hardware to get the current phase of a clock.
176 * Returned values are 0-359 degrees on success, negative
177 * error codes on failure.
178 *
179 * @set_phase: Shift the phase this clock signal in degrees specified
180 * by the second argument. Valid values for degrees are
181 * 0-359. Return 0 on success, otherwise -EERROR.
182 *
183 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
184 * of a clock. Returned values denominator cannot be 0 and must be
185 * superior or equal to the numerator.
186 *
187 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
188 * the numerator (2nd argurment) and denominator (3rd argument).
189 * Argument must be a valid ratio (denominator > 0
190 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 *
192 * @init: Perform platform-specific initialization magic.
193 * This is not used by any of the basic clock types.
194 * This callback exist for HW which needs to perform some
195 * initialisation magic for CCF to get an accurate view of the
196 * clock. It may also be used dynamic resource allocation is
197 * required. It shall not used to deal with clock parameters,
198 * such as rate or parents.
199 * Returns 0 on success, -EERROR otherwise.
200 *
201 * @terminate: Free any resource allocated by init.
202 *
203 * @debug_init: Set up type-specific debugfs entries for this clock. This
204 * is called once, after the debugfs directory entry for this
205 * clock has been created. The dentry pointer representing that
206 * directory is provided as an argument. Called with
207 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
208 *
209 * @pre_rate_change: Optional callback for a clock to fulfill its rate
210 * change requirements before any rate change has occurred in
211 * its clock tree. Returns 0 on success, -EERROR otherwise.
212 *
213 * @post_rate_change: Optional callback for a clock to clean up any
214 * requirements that were needed while the clock and its tree
215 * was changing states. Returns 0 on success, -EERROR otherwise.
216 *
217 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
218 * implementations to split any work between atomic (enable) and sleepable
219 * (prepare) contexts. If enabling a clock requires code that might sleep,
220 * this must be done in clk_prepare. Clock enable code that will never be
221 * called in a sleepable context may be implemented in clk_enable.
222 *
223 * Typically, drivers will call clk_prepare when a clock may be needed later
224 * (eg. when a device is opened), and clk_enable when the clock is actually
225 * required (eg. from an interrupt). Note that clk_prepare MUST have been
226 * called before clk_enable.
227 */
228 struct clk_ops {
229 int (*prepare)(struct clk_hw *hw);
230 void (*unprepare)(struct clk_hw *hw);
231 int (*is_prepared)(struct clk_hw *hw);
232 void (*unprepare_unused)(struct clk_hw *hw);
233 int (*enable)(struct clk_hw *hw);
234 void (*disable)(struct clk_hw *hw);
235 int (*is_enabled)(struct clk_hw *hw);
236 void (*disable_unused)(struct clk_hw *hw);
237 int (*save_context)(struct clk_hw *hw);
238 void (*restore_context)(struct clk_hw *hw);
239 unsigned long (*recalc_rate)(struct clk_hw *hw,
240 unsigned long parent_rate);
241 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
242 unsigned long *parent_rate);
243 int (*determine_rate)(struct clk_hw *hw,
244 struct clk_rate_request *req);
245 int (*set_parent)(struct clk_hw *hw, u8 index);
246 u8 (*get_parent)(struct clk_hw *hw);
247 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
248 unsigned long parent_rate);
249 int (*set_rate_and_parent)(struct clk_hw *hw,
250 unsigned long rate,
251 unsigned long parent_rate, u8 index);
252 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
253 unsigned long parent_accuracy);
254 int (*get_phase)(struct clk_hw *hw);
255 int (*set_phase)(struct clk_hw *hw, int degrees);
256 int (*get_duty_cycle)(struct clk_hw *hw,
257 struct clk_duty *duty);
258 int (*set_duty_cycle)(struct clk_hw *hw,
259 struct clk_duty *duty);
260 int (*init)(struct clk_hw *hw);
261 void (*terminate)(struct clk_hw *hw);
262 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
263 int (*pre_rate_change)(struct clk_hw *hw,
264 unsigned long rate,
265 unsigned long new_rate);
266 int (*post_rate_change)(struct clk_hw *hw,
267 unsigned long old_rate,
268 unsigned long rate);
269 };
270
271 /**
272 * struct clk_parent_data - clk parent information
273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274 * @fw_name: parent name local to provider registering clk
275 * @name: globally unique parent name (used as a fallback)
276 * @index: parent index local to provider registering clk (if @fw_name absent)
277 */
278 struct clk_parent_data {
279 const struct clk_hw *hw;
280 const char *fw_name;
281 const char *name;
282 int index;
283 };
284
285 /**
286 * struct clk_init_data - holds init data that's common to all clocks and is
287 * shared between the clock provider and the common clock framework.
288 *
289 * @name: clock name
290 * @ops: operations this clock supports
291 * @parent_names: array of string names for all possible parents
292 * @parent_data: array of parent data for all possible parents (when some
293 * parents are external to the clk controller)
294 * @parent_hws: array of pointers to all possible parents (when all parents
295 * are internal to the clk controller)
296 * @num_parents: number of possible parents
297 * @flags: framework-level hints and quirks
298 */
299 struct clk_init_data {
300 const char *name;
301 const struct clk_ops *ops;
302 /* Only one of the following three should be assigned */
303 const char * const *parent_names;
304 const struct clk_parent_data *parent_data;
305 const struct clk_hw **parent_hws;
306 u8 num_parents;
307 unsigned long flags;
308 };
309
310 /**
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
313 * clk_foo and then referenced by the struct clk instance that uses struct
314 * clk_foo's clk_ops
315 *
316 * @core: pointer to the struct clk_core instance that points back to this
317 * struct clk_hw instance
318 *
319 * @clk: pointer to the per-user struct clk instance that can be used to call
320 * into the clk API
321 *
322 * @init: pointer to struct clk_init_data that contains the init data shared
323 * with the common clock framework. This pointer will be set to NULL once
324 * a clk_register() variant is called on this clk_hw pointer.
325 */
326 struct clk_hw {
327 struct clk_core *core;
328 struct clk *clk;
329 const struct clk_init_data *init;
330 };
331
332 /*
333 * DOC: Basic clock implementations common to many platforms
334 *
335 * Each basic clock hardware type is comprised of a structure describing the
336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
337 * unique flags for that hardware type, a registration function and an
338 * alternative macro for static initialization
339 */
340
341 /**
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
344 * @fixed_rate: constant frequency of clock
345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
346 * @flags: hardware specific flags
347 *
348 * Flags:
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
350 * instead of what's set in @fixed_accuracy.
351 */
352 struct clk_fixed_rate {
353 struct clk_hw hw;
354 unsigned long fixed_rate;
355 unsigned long fixed_accuracy;
356 unsigned long flags;
357 };
358
359 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
360
361 extern const struct clk_ops clk_fixed_rate_ops;
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
363 struct device_node *np, const char *name,
364 const char *parent_name, const struct clk_hw *parent_hw,
365 const struct clk_parent_data *parent_data, unsigned long flags,
366 unsigned long fixed_rate, unsigned long fixed_accuracy,
367 unsigned long clk_fixed_flags);
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
369 const char *parent_name, unsigned long flags,
370 unsigned long fixed_rate);
371 /**
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
373 * framework
374 * @dev: device that is registering this clock
375 * @name: name of this clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
379 */
380 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
382 NULL, (flags), (fixed_rate), 0, 0)
383 /**
384 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
385 * the clock framework
386 * @dev: device that is registering this clock
387 * @name: name of this clock
388 * @parent_hw: pointer to parent clk
389 * @flags: framework-specific flags
390 * @fixed_rate: non-adjustable clock rate
391 */
392 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
393 fixed_rate) \
394 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
395 NULL, (flags), (fixed_rate), 0, 0)
396 /**
397 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_data: parent clk data
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 */
405 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
406 fixed_rate) \
407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
408 (parent_data), (flags), (fixed_rate), 0, \
409 0)
410 /**
411 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
412 * the clock framework
413 * @dev: device that is registering this clock
414 * @name: name of this clock
415 * @parent_name: name of clock's parent
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
418 * @fixed_accuracy: non-adjustable clock accuracy
419 */
420 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
421 flags, fixed_rate, \
422 fixed_accuracy) \
423 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
424 NULL, NULL, (flags), (fixed_rate), \
425 (fixed_accuracy), 0)
426 /**
427 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
428 * clock with the clock framework
429 * @dev: device that is registering this clock
430 * @name: name of this clock
431 * @parent_hw: pointer to parent clk
432 * @flags: framework-specific flags
433 * @fixed_rate: non-adjustable clock rate
434 * @fixed_accuracy: non-adjustable clock accuracy
435 */
436 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
437 parent_hw, flags, fixed_rate, fixed_accuracy) \
438 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
439 NULL, NULL, (flags), (fixed_rate), \
440 (fixed_accuracy), 0)
441 /**
442 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
443 * clock with the clock framework
444 * @dev: device that is registering this clock
445 * @name: name of this clock
446 * @parent_name: name of clock's parent
447 * @flags: framework-specific flags
448 * @fixed_rate: non-adjustable clock rate
449 * @fixed_accuracy: non-adjustable clock accuracy
450 */
451 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
452 parent_data, flags, fixed_rate, fixed_accuracy) \
453 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
454 (parent_data), NULL, (flags), \
455 (fixed_rate), (fixed_accuracy), 0)
456
457 void clk_unregister_fixed_rate(struct clk *clk);
458 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
459
460 void of_fixed_clk_setup(struct device_node *np);
461
462 /**
463 * struct clk_gate - gating clock
464 *
465 * @hw: handle between common and hardware-specific interfaces
466 * @reg: register controlling gate
467 * @bit_idx: single bit controlling gate
468 * @flags: hardware-specific flags
469 * @lock: register lock
470 *
471 * Clock which can gate its output. Implements .enable & .disable
472 *
473 * Flags:
474 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
475 * enable the clock. Setting this flag does the opposite: setting the bit
476 * disable the clock and clearing it enables the clock
477 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
478 * of this register, and mask of gate bits are in higher 16-bit of this
479 * register. While setting the gate bits, higher 16-bit should also be
480 * updated to indicate changing gate bits.
481 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
482 * the gate register. Setting this flag makes the register accesses big
483 * endian.
484 */
485 struct clk_gate {
486 struct clk_hw hw;
487 void __iomem *reg;
488 u8 bit_idx;
489 u8 flags;
490 spinlock_t *lock;
491 };
492
493 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
494
495 #define CLK_GATE_SET_TO_DISABLE BIT(0)
496 #define CLK_GATE_HIWORD_MASK BIT(1)
497 #define CLK_GATE_BIG_ENDIAN BIT(2)
498
499 extern const struct clk_ops clk_gate_ops;
500 struct clk_hw *__clk_hw_register_gate(struct device *dev,
501 struct device_node *np, const char *name,
502 const char *parent_name, const struct clk_hw *parent_hw,
503 const struct clk_parent_data *parent_data,
504 unsigned long flags,
505 void __iomem *reg, u8 bit_idx,
506 u8 clk_gate_flags, spinlock_t *lock);
507 struct clk *clk_register_gate(struct device *dev, const char *name,
508 const char *parent_name, unsigned long flags,
509 void __iomem *reg, u8 bit_idx,
510 u8 clk_gate_flags, spinlock_t *lock);
511 /**
512 * clk_hw_register_gate - register a gate clock with the clock framework
513 * @dev: device that is registering this clock
514 * @name: name of this clock
515 * @parent_name: name of this clock's parent
516 * @flags: framework-specific flags for this clock
517 * @reg: register address to control gating of this clock
518 * @bit_idx: which bit in the register controls gating of this clock
519 * @clk_gate_flags: gate-specific flags for this clock
520 * @lock: shared register lock for this clock
521 */
522 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
523 clk_gate_flags, lock) \
524 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
525 NULL, (flags), (reg), (bit_idx), \
526 (clk_gate_flags), (lock))
527 /**
528 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
529 * framework
530 * @dev: device that is registering this clock
531 * @name: name of this clock
532 * @parent_hw: pointer to parent clk
533 * @flags: framework-specific flags for this clock
534 * @reg: register address to control gating of this clock
535 * @bit_idx: which bit in the register controls gating of this clock
536 * @clk_gate_flags: gate-specific flags for this clock
537 * @lock: shared register lock for this clock
538 */
539 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
540 bit_idx, clk_gate_flags, lock) \
541 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
542 NULL, (flags), (reg), (bit_idx), \
543 (clk_gate_flags), (lock))
544 /**
545 * clk_hw_register_gate_parent_data - register a gate clock with the clock
546 * framework
547 * @dev: device that is registering this clock
548 * @name: name of this clock
549 * @parent_data: parent clk data
550 * @flags: framework-specific flags for this clock
551 * @reg: register address to control gating of this clock
552 * @bit_idx: which bit in the register controls gating of this clock
553 * @clk_gate_flags: gate-specific flags for this clock
554 * @lock: shared register lock for this clock
555 */
556 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
557 bit_idx, clk_gate_flags, lock) \
558 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
559 (flags), (reg), (bit_idx), \
560 (clk_gate_flags), (lock))
561 void clk_unregister_gate(struct clk *clk);
562 void clk_hw_unregister_gate(struct clk_hw *hw);
563 int clk_gate_is_enabled(struct clk_hw *hw);
564
565 struct clk_div_table {
566 unsigned int val;
567 unsigned int div;
568 };
569
570 /**
571 * struct clk_divider - adjustable divider clock
572 *
573 * @hw: handle between common and hardware-specific interfaces
574 * @reg: register containing the divider
575 * @shift: shift to the divider bit field
576 * @width: width of the divider bit field
577 * @table: array of value/divider pairs, last entry should have div = 0
578 * @lock: register lock
579 *
580 * Clock with an adjustable divider affecting its output frequency. Implements
581 * .recalc_rate, .set_rate and .round_rate
582 *
583 * Flags:
584 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
585 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
586 * the raw value read from the register, with the value of zero considered
587 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
588 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
589 * the hardware register
590 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
591 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
592 * Some hardware implementations gracefully handle this case and allow a
593 * zero divisor by not modifying their input clock
594 * (divide by one / bypass).
595 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
596 * of this register, and mask of divider bits are in higher 16-bit of this
597 * register. While setting the divider bits, higher 16-bit should also be
598 * updated to indicate changing divider bits.
599 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
600 * to the closest integer instead of the up one.
601 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
602 * not be changed by the clock framework.
603 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
604 * except when the value read from the register is zero, the divisor is
605 * 2^width of the field.
606 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
607 * for the divider register. Setting this flag makes the register accesses
608 * big endian.
609 */
610 struct clk_divider {
611 struct clk_hw hw;
612 void __iomem *reg;
613 u8 shift;
614 u8 width;
615 u8 flags;
616 const struct clk_div_table *table;
617 spinlock_t *lock;
618 };
619
620 #define clk_div_mask(width) ((1 << (width)) - 1)
621 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
622
623 #define CLK_DIVIDER_ONE_BASED BIT(0)
624 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
625 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
626 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
627 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
628 #define CLK_DIVIDER_READ_ONLY BIT(5)
629 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
630 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
631
632 extern const struct clk_ops clk_divider_ops;
633 extern const struct clk_ops clk_divider_ro_ops;
634
635 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
636 unsigned int val, const struct clk_div_table *table,
637 unsigned long flags, unsigned long width);
638 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
639 unsigned long rate, unsigned long *prate,
640 const struct clk_div_table *table,
641 u8 width, unsigned long flags);
642 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
643 unsigned long rate, unsigned long *prate,
644 const struct clk_div_table *table, u8 width,
645 unsigned long flags, unsigned int val);
646 int divider_get_val(unsigned long rate, unsigned long parent_rate,
647 const struct clk_div_table *table, u8 width,
648 unsigned long flags);
649
650 struct clk_hw *__clk_hw_register_divider(struct device *dev,
651 struct device_node *np, const char *name,
652 const char *parent_name, const struct clk_hw *parent_hw,
653 const struct clk_parent_data *parent_data, unsigned long flags,
654 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
655 const struct clk_div_table *table, spinlock_t *lock);
656 struct clk *clk_register_divider_table(struct device *dev, const char *name,
657 const char *parent_name, unsigned long flags,
658 void __iomem *reg, u8 shift, u8 width,
659 u8 clk_divider_flags, const struct clk_div_table *table,
660 spinlock_t *lock);
661 /**
662 * clk_register_divider - register a divider clock with the clock framework
663 * @dev: device registering this clock
664 * @name: name of this clock
665 * @parent_name: name of clock's parent
666 * @flags: framework-specific flags
667 * @reg: register address to adjust divider
668 * @shift: number of bits to shift the bitfield
669 * @width: width of the bitfield
670 * @clk_divider_flags: divider-specific flags for this clock
671 * @lock: shared register lock for this clock
672 */
673 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
674 clk_divider_flags, lock) \
675 clk_register_divider_table((dev), (name), (parent_name), (flags), \
676 (reg), (shift), (width), \
677 (clk_divider_flags), NULL, (lock))
678 /**
679 * clk_hw_register_divider - register a divider clock with the clock framework
680 * @dev: device registering this clock
681 * @name: name of this clock
682 * @parent_name: name of clock's parent
683 * @flags: framework-specific flags
684 * @reg: register address to adjust divider
685 * @shift: number of bits to shift the bitfield
686 * @width: width of the bitfield
687 * @clk_divider_flags: divider-specific flags for this clock
688 * @lock: shared register lock for this clock
689 */
690 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
691 width, clk_divider_flags, lock) \
692 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
693 NULL, (flags), (reg), (shift), (width), \
694 (clk_divider_flags), NULL, (lock))
695 /**
696 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
697 * framework
698 * @dev: device registering this clock
699 * @name: name of this clock
700 * @parent_hw: pointer to parent clk
701 * @flags: framework-specific flags
702 * @reg: register address to adjust divider
703 * @shift: number of bits to shift the bitfield
704 * @width: width of the bitfield
705 * @clk_divider_flags: divider-specific flags for this clock
706 * @lock: shared register lock for this clock
707 */
708 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
709 shift, width, clk_divider_flags, \
710 lock) \
711 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
712 NULL, (flags), (reg), (shift), (width), \
713 (clk_divider_flags), NULL, (lock))
714 /**
715 * clk_hw_register_divider_parent_data - register a divider clock with the clock
716 * framework
717 * @dev: device registering this clock
718 * @name: name of this clock
719 * @parent_data: parent clk data
720 * @flags: framework-specific flags
721 * @reg: register address to adjust divider
722 * @shift: number of bits to shift the bitfield
723 * @width: width of the bitfield
724 * @clk_divider_flags: divider-specific flags for this clock
725 * @lock: shared register lock for this clock
726 */
727 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
728 reg, shift, width, \
729 clk_divider_flags, lock) \
730 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
731 (parent_data), (flags), (reg), (shift), \
732 (width), (clk_divider_flags), NULL, (lock))
733 /**
734 * clk_hw_register_divider_table - register a table based divider clock with
735 * the clock framework
736 * @dev: device registering this clock
737 * @name: name of this clock
738 * @parent_name: name of clock's parent
739 * @flags: framework-specific flags
740 * @reg: register address to adjust divider
741 * @shift: number of bits to shift the bitfield
742 * @width: width of the bitfield
743 * @clk_divider_flags: divider-specific flags for this clock
744 * @table: array of divider/value pairs ending with a div set to 0
745 * @lock: shared register lock for this clock
746 */
747 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
748 shift, width, clk_divider_flags, table, \
749 lock) \
750 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
751 NULL, (flags), (reg), (shift), (width), \
752 (clk_divider_flags), (table), (lock))
753 /**
754 * clk_hw_register_divider_table_parent_hw - register a table based divider
755 * clock with the clock framework
756 * @dev: device registering this clock
757 * @name: name of this clock
758 * @parent_hw: pointer to parent clk
759 * @flags: framework-specific flags
760 * @reg: register address to adjust divider
761 * @shift: number of bits to shift the bitfield
762 * @width: width of the bitfield
763 * @clk_divider_flags: divider-specific flags for this clock
764 * @table: array of divider/value pairs ending with a div set to 0
765 * @lock: shared register lock for this clock
766 */
767 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
768 reg, shift, width, \
769 clk_divider_flags, table, \
770 lock) \
771 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
772 NULL, (flags), (reg), (shift), (width), \
773 (clk_divider_flags), (table), (lock))
774 /**
775 * clk_hw_register_divider_table_parent_data - register a table based divider
776 * clock with the clock framework
777 * @dev: device registering this clock
778 * @name: name of this clock
779 * @parent_data: parent clk data
780 * @flags: framework-specific flags
781 * @reg: register address to adjust divider
782 * @shift: number of bits to shift the bitfield
783 * @width: width of the bitfield
784 * @clk_divider_flags: divider-specific flags for this clock
785 * @table: array of divider/value pairs ending with a div set to 0
786 * @lock: shared register lock for this clock
787 */
788 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
789 flags, reg, shift, width, \
790 clk_divider_flags, table, \
791 lock) \
792 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
793 (parent_data), (flags), (reg), (shift), \
794 (width), (clk_divider_flags), (table), \
795 (lock))
796
797 void clk_unregister_divider(struct clk *clk);
798 void clk_hw_unregister_divider(struct clk_hw *hw);
799
800 /**
801 * struct clk_mux - multiplexer clock
802 *
803 * @hw: handle between common and hardware-specific interfaces
804 * @reg: register controlling multiplexer
805 * @table: array of register values corresponding to the parent index
806 * @shift: shift to multiplexer bit field
807 * @mask: mask of mutliplexer bit field
808 * @flags: hardware-specific flags
809 * @lock: register lock
810 *
811 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
812 * and .recalc_rate
813 *
814 * Flags:
815 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
816 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
817 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
818 * register, and mask of mux bits are in higher 16-bit of this register.
819 * While setting the mux bits, higher 16-bit should also be updated to
820 * indicate changing mux bits.
821 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
822 * .get_parent clk_op.
823 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
824 * frequency.
825 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
826 * the mux register. Setting this flag makes the register accesses big
827 * endian.
828 */
829 struct clk_mux {
830 struct clk_hw hw;
831 void __iomem *reg;
832 u32 *table;
833 u32 mask;
834 u8 shift;
835 u8 flags;
836 spinlock_t *lock;
837 };
838
839 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
840
841 #define CLK_MUX_INDEX_ONE BIT(0)
842 #define CLK_MUX_INDEX_BIT BIT(1)
843 #define CLK_MUX_HIWORD_MASK BIT(2)
844 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
845 #define CLK_MUX_ROUND_CLOSEST BIT(4)
846 #define CLK_MUX_BIG_ENDIAN BIT(5)
847
848 extern const struct clk_ops clk_mux_ops;
849 extern const struct clk_ops clk_mux_ro_ops;
850
851 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
852 const char *name, u8 num_parents,
853 const char * const *parent_names,
854 const struct clk_hw **parent_hws,
855 const struct clk_parent_data *parent_data,
856 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
857 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
858 struct clk *clk_register_mux_table(struct device *dev, const char *name,
859 const char * const *parent_names, u8 num_parents,
860 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
861 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
862
863 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
864 shift, width, clk_mux_flags, lock) \
865 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
866 (flags), (reg), (shift), BIT((width)) - 1, \
867 (clk_mux_flags), NULL, (lock))
868 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
869 flags, reg, shift, mask, clk_mux_flags, \
870 table, lock) \
871 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
872 (parent_names), NULL, NULL, (flags), (reg), \
873 (shift), (mask), (clk_mux_flags), (table), \
874 (lock))
875 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
876 shift, width, clk_mux_flags, lock) \
877 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
878 (parent_names), NULL, NULL, (flags), (reg), \
879 (shift), BIT((width)) - 1, (clk_mux_flags), \
880 NULL, (lock))
881 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
882 reg, shift, width, clk_mux_flags, lock) \
883 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
884 (parent_hws), NULL, (flags), (reg), (shift), \
885 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
886 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
887 flags, reg, shift, width, \
888 clk_mux_flags, lock) \
889 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
890 (parent_data), (flags), (reg), (shift), \
891 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
892
893 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
894 unsigned int val);
895 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
896
897 void clk_unregister_mux(struct clk *clk);
898 void clk_hw_unregister_mux(struct clk_hw *hw);
899
900 void of_fixed_factor_clk_setup(struct device_node *node);
901
902 /**
903 * struct clk_fixed_factor - fixed multiplier and divider clock
904 *
905 * @hw: handle between common and hardware-specific interfaces
906 * @mult: multiplier
907 * @div: divider
908 *
909 * Clock with a fixed multiplier and divider. The output frequency is the
910 * parent clock rate divided by div and multiplied by mult.
911 * Implements .recalc_rate, .set_rate and .round_rate
912 */
913
914 struct clk_fixed_factor {
915 struct clk_hw hw;
916 unsigned int mult;
917 unsigned int div;
918 };
919
920 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
921
922 extern const struct clk_ops clk_fixed_factor_ops;
923 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
924 const char *parent_name, unsigned long flags,
925 unsigned int mult, unsigned int div);
926 void clk_unregister_fixed_factor(struct clk *clk);
927 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
928 const char *name, const char *parent_name, unsigned long flags,
929 unsigned int mult, unsigned int div);
930 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
931
932 /**
933 * struct clk_fractional_divider - adjustable fractional divider clock
934 *
935 * @hw: handle between common and hardware-specific interfaces
936 * @reg: register containing the divider
937 * @mshift: shift to the numerator bit field
938 * @mwidth: width of the numerator bit field
939 * @nshift: shift to the denominator bit field
940 * @nwidth: width of the denominator bit field
941 * @lock: register lock
942 *
943 * Clock with adjustable fractional divider affecting its output frequency.
944 *
945 * Flags:
946 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
947 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
948 * is set then the numerator and denominator are both the value read
949 * plus one.
950 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
951 * used for the divider register. Setting this flag makes the register
952 * accesses big endian.
953 * CLK_FRAC_DIVIDER_NO_LIMIT - not need to follow the 20 times limit on
954 * fractional divider
955 */
956 struct clk_fractional_divider {
957 struct clk_hw hw;
958 void __iomem *reg;
959 u8 mshift;
960 u8 mwidth;
961 u32 mmask;
962 u8 nshift;
963 u8 nwidth;
964 u32 nmask;
965 u8 flags;
966 void (*approximation)(struct clk_hw *hw,
967 unsigned long rate, unsigned long *parent_rate,
968 unsigned long *m, unsigned long *n);
969 spinlock_t *lock;
970 };
971
972 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
973
974 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
975 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
976 #define CLK_FRAC_DIVIDER_NO_LIMIT BIT(2)
977
978 extern const struct clk_ops clk_fractional_divider_ops;
979 struct clk *clk_register_fractional_divider(struct device *dev,
980 const char *name, const char *parent_name, unsigned long flags,
981 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
982 u8 clk_divider_flags, spinlock_t *lock);
983 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
984 const char *name, const char *parent_name, unsigned long flags,
985 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
986 u8 clk_divider_flags, spinlock_t *lock);
987 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
988
989 /**
990 * struct clk_multiplier - adjustable multiplier clock
991 *
992 * @hw: handle between common and hardware-specific interfaces
993 * @reg: register containing the multiplier
994 * @shift: shift to the multiplier bit field
995 * @width: width of the multiplier bit field
996 * @lock: register lock
997 *
998 * Clock with an adjustable multiplier affecting its output frequency.
999 * Implements .recalc_rate, .set_rate and .round_rate
1000 *
1001 * Flags:
1002 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1003 * from the register, with 0 being a valid value effectively
1004 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1005 * set, then a null multiplier will be considered as a bypass,
1006 * leaving the parent rate unmodified.
1007 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1008 * rounded to the closest integer instead of the down one.
1009 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1010 * used for the multiplier register. Setting this flag makes the register
1011 * accesses big endian.
1012 */
1013 struct clk_multiplier {
1014 struct clk_hw hw;
1015 void __iomem *reg;
1016 u8 shift;
1017 u8 width;
1018 u8 flags;
1019 spinlock_t *lock;
1020 };
1021
1022 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1023
1024 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1025 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1026 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1027
1028 extern const struct clk_ops clk_multiplier_ops;
1029
1030 /***
1031 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1032 *
1033 * @hw: handle between common and hardware-specific interfaces
1034 * @mux_hw: handle between composite and hardware-specific mux clock
1035 * @rate_hw: handle between composite and hardware-specific rate clock
1036 * @gate_hw: handle between composite and hardware-specific gate clock
1037 * @mux_ops: clock ops for mux
1038 * @rate_ops: clock ops for rate
1039 * @gate_ops: clock ops for gate
1040 */
1041 struct clk_composite {
1042 struct clk_hw hw;
1043 struct clk_ops ops;
1044
1045 struct clk_hw *mux_hw;
1046 struct clk_hw *rate_hw;
1047 struct clk_hw *gate_hw;
1048
1049 const struct clk_ops *mux_ops;
1050 const struct clk_ops *rate_ops;
1051 const struct clk_ops *gate_ops;
1052 };
1053
1054 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1055
1056 struct clk *clk_register_composite(struct device *dev, const char *name,
1057 const char * const *parent_names, int num_parents,
1058 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1059 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1060 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1061 unsigned long flags);
1062 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1063 const struct clk_parent_data *parent_data, int num_parents,
1064 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1065 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1066 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1067 unsigned long flags);
1068 void clk_unregister_composite(struct clk *clk);
1069 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1070 const char * const *parent_names, int num_parents,
1071 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1072 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1073 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1074 unsigned long flags);
1075 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1076 const char *name,
1077 const struct clk_parent_data *parent_data, int num_parents,
1078 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1079 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1080 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1081 unsigned long flags);
1082 void clk_hw_unregister_composite(struct clk_hw *hw);
1083
1084 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1085 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1086
1087 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1088 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1089 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1090
1091 void clk_unregister(struct clk *clk);
1092 void devm_clk_unregister(struct device *dev, struct clk *clk);
1093
1094 void clk_hw_unregister(struct clk_hw *hw);
1095 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1096 void clk_sync_state(struct device *dev);
1097
1098 /* helper functions */
1099 const char *__clk_get_name(const struct clk *clk);
1100 const char *clk_hw_get_name(const struct clk_hw *hw);
1101 #ifdef CONFIG_COMMON_CLK
1102 struct clk_hw *__clk_get_hw(struct clk *clk);
1103 #else
__clk_get_hw(struct clk * clk)1104 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1105 {
1106 return (struct clk_hw *)clk;
1107 }
1108 #endif
1109
1110 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1111 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1112 const char *con_id);
1113
1114 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1115 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1116 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1117 unsigned int index);
1118 int clk_hw_get_parent_index(struct clk_hw *hw);
1119 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1120 unsigned int __clk_get_enable_count(struct clk *clk);
1121 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1122 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1123 bool clk_hw_is_prepared(const struct clk_hw *hw);
1124 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1125 bool clk_hw_is_enabled(const struct clk_hw *hw);
1126 bool __clk_is_enabled(struct clk *clk);
1127 struct clk *__clk_lookup(const char *name);
1128 int __clk_mux_determine_rate(struct clk_hw *hw,
1129 struct clk_rate_request *req);
1130 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1131 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1132 struct clk_rate_request *req);
1133 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1134 struct clk_rate_request *req,
1135 unsigned long flags);
1136 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1137 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1138 unsigned long max_rate);
1139
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1140 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1141 {
1142 dst->clk = src->clk;
1143 dst->core = src->core;
1144 }
1145
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1146 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1147 unsigned long *prate,
1148 const struct clk_div_table *table,
1149 u8 width, unsigned long flags)
1150 {
1151 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1152 rate, prate, table, width, flags);
1153 }
1154
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1155 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1156 unsigned long *prate,
1157 const struct clk_div_table *table,
1158 u8 width, unsigned long flags,
1159 unsigned int val)
1160 {
1161 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1162 rate, prate, table, width, flags,
1163 val);
1164 }
1165
1166 /*
1167 * FIXME clock api without lock protection
1168 */
1169 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1170
1171 struct clk_onecell_data {
1172 struct clk **clks;
1173 unsigned int clk_num;
1174 };
1175
1176 struct clk_hw_onecell_data {
1177 unsigned int num;
1178 struct clk_hw *hws[];
1179 };
1180
1181 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1182
1183 /*
1184 * Use this macro when you have a driver that requires two initialization
1185 * routines, one at of_clk_init(), and one at platform device probe
1186 */
1187 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1188 static void __init name##_of_clk_init_driver(struct device_node *np) \
1189 { \
1190 of_node_clear_flag(np, OF_POPULATED); \
1191 fn(np); \
1192 } \
1193 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1194
1195 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1196 (&(struct clk_init_data) { \
1197 .flags = _flags, \
1198 .name = _name, \
1199 .parent_names = (const char *[]) { _parent }, \
1200 .num_parents = 1, \
1201 .ops = _ops, \
1202 })
1203
1204 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1205 (&(struct clk_init_data) { \
1206 .flags = _flags, \
1207 .name = _name, \
1208 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1209 .num_parents = 1, \
1210 .ops = _ops, \
1211 })
1212
1213 /*
1214 * This macro is intended for drivers to be able to share the otherwise
1215 * individual struct clk_hw[] compound literals created by the compiler
1216 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1217 */
1218 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1219 (&(struct clk_init_data) { \
1220 .flags = _flags, \
1221 .name = _name, \
1222 .parent_hws = _parent, \
1223 .num_parents = 1, \
1224 .ops = _ops, \
1225 })
1226
1227 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1228 (&(struct clk_init_data) { \
1229 .flags = _flags, \
1230 .name = _name, \
1231 .parent_data = (const struct clk_parent_data[]) { \
1232 { .fw_name = _parent }, \
1233 }, \
1234 .num_parents = 1, \
1235 .ops = _ops, \
1236 })
1237
1238 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1239 (&(struct clk_init_data) { \
1240 .flags = _flags, \
1241 .name = _name, \
1242 .parent_names = _parents, \
1243 .num_parents = ARRAY_SIZE(_parents), \
1244 .ops = _ops, \
1245 })
1246
1247 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1248 (&(struct clk_init_data) { \
1249 .flags = _flags, \
1250 .name = _name, \
1251 .parent_hws = _parents, \
1252 .num_parents = ARRAY_SIZE(_parents), \
1253 .ops = _ops, \
1254 })
1255
1256 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1257 (&(struct clk_init_data) { \
1258 .flags = _flags, \
1259 .name = _name, \
1260 .parent_data = _parents, \
1261 .num_parents = ARRAY_SIZE(_parents), \
1262 .ops = _ops, \
1263 })
1264
1265 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1266 (&(struct clk_init_data) { \
1267 .flags = _flags, \
1268 .name = _name, \
1269 .parent_names = NULL, \
1270 .num_parents = 0, \
1271 .ops = _ops, \
1272 })
1273
1274 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1275 _div, _mult, _flags) \
1276 struct clk_fixed_factor _struct = { \
1277 .div = _div, \
1278 .mult = _mult, \
1279 .hw.init = CLK_HW_INIT(_name, \
1280 _parent, \
1281 &clk_fixed_factor_ops, \
1282 _flags), \
1283 }
1284
1285 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1286 _div, _mult, _flags) \
1287 struct clk_fixed_factor _struct = { \
1288 .div = _div, \
1289 .mult = _mult, \
1290 .hw.init = CLK_HW_INIT_HW(_name, \
1291 _parent, \
1292 &clk_fixed_factor_ops, \
1293 _flags), \
1294 }
1295
1296 /*
1297 * This macro allows the driver to reuse the _parent array for multiple
1298 * fixed factor clk declarations.
1299 */
1300 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1301 _div, _mult, _flags) \
1302 struct clk_fixed_factor _struct = { \
1303 .div = _div, \
1304 .mult = _mult, \
1305 .hw.init = CLK_HW_INIT_HWS(_name, \
1306 _parent, \
1307 &clk_fixed_factor_ops, \
1308 _flags), \
1309 }
1310
1311 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1312 _div, _mult, _flags) \
1313 struct clk_fixed_factor _struct = { \
1314 .div = _div, \
1315 .mult = _mult, \
1316 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1317 _parent, \
1318 &clk_fixed_factor_ops, \
1319 _flags), \
1320 }
1321
1322 #ifdef CONFIG_OF
1323 int of_clk_add_provider(struct device_node *np,
1324 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1325 void *data),
1326 void *data);
1327 int of_clk_add_hw_provider(struct device_node *np,
1328 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1329 void *data),
1330 void *data);
1331 int devm_of_clk_add_hw_provider(struct device *dev,
1332 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1333 void *data),
1334 void *data);
1335 void of_clk_del_provider(struct device_node *np);
1336 void devm_of_clk_del_provider(struct device *dev);
1337 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1338 void *data);
1339 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1340 void *data);
1341 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1342 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1343 void *data);
1344 int of_clk_parent_fill(struct device_node *np, const char **parents,
1345 unsigned int size);
1346 int of_clk_detect_critical(struct device_node *np, int index,
1347 unsigned long *flags);
1348
1349 #else /* !CONFIG_OF */
1350
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1351 static inline int of_clk_add_provider(struct device_node *np,
1352 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1353 void *data),
1354 void *data)
1355 {
1356 return 0;
1357 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1358 static inline int of_clk_add_hw_provider(struct device_node *np,
1359 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1360 void *data),
1361 void *data)
1362 {
1363 return 0;
1364 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1365 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1366 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1367 void *data),
1368 void *data)
1369 {
1370 return 0;
1371 }
of_clk_del_provider(struct device_node * np)1372 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1373 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1374 static inline struct clk *of_clk_src_simple_get(
1375 struct of_phandle_args *clkspec, void *data)
1376 {
1377 return ERR_PTR(-ENOENT);
1378 }
1379 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1380 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1381 {
1382 return ERR_PTR(-ENOENT);
1383 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1384 static inline struct clk *of_clk_src_onecell_get(
1385 struct of_phandle_args *clkspec, void *data)
1386 {
1387 return ERR_PTR(-ENOENT);
1388 }
1389 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1390 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1391 {
1392 return ERR_PTR(-ENOENT);
1393 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1394 static inline int of_clk_parent_fill(struct device_node *np,
1395 const char **parents, unsigned int size)
1396 {
1397 return 0;
1398 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1399 static inline int of_clk_detect_critical(struct device_node *np, int index,
1400 unsigned long *flags)
1401 {
1402 return 0;
1403 }
1404 #endif /* CONFIG_OF */
1405
1406 void clk_gate_restore_context(struct clk_hw *hw);
1407
1408 #endif /* CLK_PROVIDER_H */
1409