1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright 2022-2023 NXP 4 */ 5 6#include <asm.S> 7#include <riscv.h> 8 9/* 10 * On the below data cache management, we rely on FENCE instruction. 11 * The FENCE instruction is used to order device I/O and memory accesses 12 * as viewed by other RISC-V harts and external devices or coprocessors. 13 * "fence" below is a pseudo-instruction of "fence iorw, iorw" which 14 * performs Fence on all memory and I/O. 15 */ 16 17/* void dcache_cleaninv_range(void *addr, size_t size); */ 18FUNC dcache_cleaninv_range , : 19 fence 20 ret 21END_FUNC dcache_cleaninv_range 22 23/* void dcache_clean_range(void *addr, size_t size); */ 24FUNC dcache_clean_range , : 25 fence 26 ret 27END_FUNC dcache_clean_range 28 29/* void dcache_inv_range(void *addr, size_t size); */ 30FUNC dcache_inv_range , : 31 fence 32 ret 33END_FUNC dcache_inv_range 34 35/* void dcache_op_all(unsigned long op_type); */ 36FUNC dcache_op_all , : 37 fence 38 ret 39END_FUNC dcache_op_all 40 41/* void icache_inv_all(void); */ 42FUNC icache_inv_all , : 43 /* 44 * FENCE.I instruction provides explicit synchronization 45 * between writes to instruction memory and instruction 46 * fetches on the same hart. This implies instruction cache 47 * management operations as result of executing this instruction. 48 */ 49 fence.i 50 ret 51END_FUNC icache_inv_all 52 53/* void icache_inv_range(void *addr, size_t size); */ 54FUNC icache_inv_range , : 55 /* 56 * RISC-V does not have an instruction to flush a range 57 * of the I$, therefore, flush it entirely as invoking 58 * icache_inv_all(). 59 */ 60 fence.i 61 ret 62END_FUNC icache_inv_range 63