1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2018-2020 NXP 4 * 5 * Brief CAAM Controller Hardware Abstration Layer header. 6 */ 7 #ifndef __CAAM_HAL_CTRL_H__ 8 #define __CAAM_HAL_CTRL_H__ 9 10 #include <caam_common.h> 11 #include <types_ext.h> 12 13 /* 14 * Initializes the CAAM HW Controller 15 * 16 * @baseaddr Controller base address 17 */ 18 void caam_hal_ctrl_init(vaddr_t baseaddr); 19 20 /* 21 * Returns the number of Job Ring supported 22 * 23 * @baseaddr Controller base address 24 */ 25 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr); 26 27 /* 28 * If Hash operation is supported, returns the Maximum Hash Algorithm 29 * supported by the HW else UINT8_MAX 30 * 31 * @baseaddr Controller base address 32 */ 33 uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr); 34 35 /* 36 * Returns the number of Public Key module supported 37 * 38 * @baseaddr Controller base address 39 */ 40 uint8_t caam_hal_ctrl_pknum(vaddr_t baseaddr); 41 42 /* 43 * Returns if the HW support the split key operation. 44 * 45 * @baseaddr Controller base address 46 */ 47 bool caam_hal_ctrl_splitkey_support(vaddr_t baseaddr); 48 49 /* 50 * Returns the CAAM Era 51 * 52 * @baseaddr Controller base address 53 */ 54 uint8_t caam_hal_ctrl_era(vaddr_t baseaddr); 55 56 /* 57 * Increment the CAAM PRIBLOB field 58 * 59 * @baseaddr Controller base address 60 */ 61 void caam_hal_ctrl_inc_priblob(vaddr_t baseaddr); 62 63 #ifdef CFG_NXP_CAAM_MP_DRV 64 /* 65 * Get the SCFGR content and check the MPCURVE fields. 66 * The function returns either: 67 * - UINT8_MAX if the Manafacturing Protection is not supported 68 * - The MP Curve Value if programmed (4 bits value) 69 * - 0 if the MP Curve is not programmed 70 * 71 * @ctrl_addr Controller base address 72 */ 73 uint8_t caam_hal_ctrl_get_mpcurve(vaddr_t ctrl_addr); 74 75 /* 76 * Read the MPMR content 77 * 78 * @ctrl_addr Controller base address 79 * @mpmr [out] MPMR buffer read 80 */ 81 TEE_Result caam_hal_ctrl_read_mpmr(vaddr_t ctrl_addr, struct caambuf *mpmr); 82 83 /* 84 * Fill the MPMR content then lock the register 85 * 86 * @ctrl_addr Controller base address 87 * @msg_mpmr Buffer with the message and length to fill the MPMR content 88 */ 89 void caam_hal_ctrl_fill_mpmr(vaddr_t ctrl_addr, struct caambuf *msg_mpmr); 90 91 /* 92 * Indicate if the MP is set 93 * 94 * @ctrl_addr Controller base address 95 */ 96 bool caam_hal_ctrl_is_mp_set(vaddr_t ctrl_addr); 97 #endif /* CFG_NXP_CAAM_MP_DRV */ 98 99 #ifdef CFG_NXP_CAAM_SM_DRV 100 /* 101 * Get the Secure Memory Virtual base address setup in the given job ring 102 * 103 * @ctrl_addr Controller base address 104 * @jr_offset Job ring offset 105 */ 106 vaddr_t caam_hal_ctrl_get_smvaddr(vaddr_t ctrl_addr, paddr_t jr_offset); 107 #endif /* CFG_NXP_CAAM_SM_DRV */ 108 #endif /* __CAAM_HAL_CTRL_H__ */ 109