1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2002-2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 #include <common.h>
14 #include <console.h>
15 #include <environment.h>
16 #include <dm.h>
17 #include <fdtdec.h>
18 #include <fs.h>
19 #include <i2c.h>
20 #include <initcall.h>
21 #include <init_helpers.h>
22 #include <malloc.h>
23 #include <mapmem.h>
24 #include <mp_boot.h>
25 #include <os.h>
26 #include <post.h>
27 #include <relocate.h>
28 #include <spi.h>
29 #include <status_led.h>
30 #include <timer.h>
31 #include <trace.h>
32 #include <video.h>
33 #include <watchdog.h>
34 #ifdef CONFIG_MACH_TYPE
35 #include <asm/mach-types.h>
36 #endif
37 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
38 #include <asm/mp.h>
39 #endif
40 #include <asm/io.h>
41 #include <asm/sections.h>
42 #include <dm/root.h>
43 #include <linux/errno.h>
44 #include <bidram.h>
45 #include <sysmem.h>
46
47 /*
48 * Pointer to initial global data area
49 *
50 * Here we initialize it if needed.
51 */
52 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
53 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
54 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
55 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
56 #else
57 DECLARE_GLOBAL_DATA_PTR;
58 #endif
59
60 /*
61 * TODO(sjg@chromium.org): IMO this code should be
62 * refactored to a single function, something like:
63 *
64 * void led_set_state(enum led_colour_t colour, int on);
65 */
66 /************************************************************************
67 * Coloured LED functionality
68 ************************************************************************
69 * May be supplied by boards if desired
70 */
coloured_LED_init(void)71 __weak void coloured_LED_init(void) {}
red_led_on(void)72 __weak void red_led_on(void) {}
red_led_off(void)73 __weak void red_led_off(void) {}
green_led_on(void)74 __weak void green_led_on(void) {}
green_led_off(void)75 __weak void green_led_off(void) {}
yellow_led_on(void)76 __weak void yellow_led_on(void) {}
yellow_led_off(void)77 __weak void yellow_led_off(void) {}
blue_led_on(void)78 __weak void blue_led_on(void) {}
blue_led_off(void)79 __weak void blue_led_off(void) {}
80
81 /*
82 * Why is gd allocated a register? Prior to reloc it might be better to
83 * just pass it around to each function in this file?
84 *
85 * After reloc one could argue that it is hardly used and doesn't need
86 * to be in a register. Or if it is it should perhaps hold pointers to all
87 * global data for all modules, so that post-reloc we can avoid the massive
88 * literal pool we get on ARM. Or perhaps just encourage each module to use
89 * a structure...
90 */
91
92 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
init_func_watchdog_init(void)93 static int init_func_watchdog_init(void)
94 {
95 # if defined(CONFIG_HW_WATCHDOG) && \
96 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
97 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
98 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
99 defined(CONFIG_IMX_WATCHDOG))
100 hw_watchdog_init();
101 puts(" Watchdog enabled\n");
102 # endif
103 WATCHDOG_RESET();
104
105 return 0;
106 }
107
init_func_watchdog_reset(void)108 int init_func_watchdog_reset(void)
109 {
110 WATCHDOG_RESET();
111
112 return 0;
113 }
114 #endif /* CONFIG_WATCHDOG */
115
board_add_ram_info(int use_default)116 __weak void board_add_ram_info(int use_default)
117 {
118 /* please define platform specific board_add_ram_info() */
119 }
120
init_baud_rate(void)121 static int init_baud_rate(void)
122 {
123 if (gd && gd->serial.baudrate)
124 gd->baudrate = gd->serial.baudrate;
125 else
126 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
127
128 return 0;
129 }
130
display_text_info(void)131 static int display_text_info(void)
132 {
133 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
134 ulong bss_start, bss_end, text_base;
135
136 bss_start = (ulong)&__bss_start;
137 bss_end = (ulong)&__bss_end;
138
139 #ifdef CONFIG_SYS_TEXT_BASE
140 text_base = CONFIG_SYS_TEXT_BASE;
141 #else
142 text_base = CONFIG_SYS_MONITOR_BASE;
143 #endif
144
145 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
146 text_base, bss_start, bss_end);
147 #endif
148
149 return 0;
150 }
151
announce_serial(void)152 static int announce_serial(void)
153 {
154 if (gd && gd->serial.using_pre_serial)
155 printf("PreSerial: %d, ", gd->serial.id);
156 else
157 printf("Serial: ");
158
159 #ifdef CONFIG_DEBUG_UART_ALWAYS
160 printf("raw");
161 #else
162 printf("console");
163 #endif
164 printf(", 0x%lx\n", gd->serial.addr);
165
166 return 0;
167 }
168
announce_dram_init(void)169 static int announce_dram_init(void)
170 {
171 #ifndef CONFIG_SUPPORT_USBPLUG
172 puts("DRAM: ");
173 #endif
174 return 0;
175 }
176
show_dram_config(void)177 static int show_dram_config(void)
178 {
179 unsigned long long size;
180
181 #ifdef CONFIG_NR_DRAM_BANKS
182 int i;
183
184 debug("\nRAM Configuration:\n");
185 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
186 size += gd->bd->bi_dram[i].size;
187 debug("Bank #%d: %llx ", i,
188 (unsigned long long)(gd->bd->bi_dram[i].start));
189 #ifdef DEBUG
190 print_size(gd->bd->bi_dram[i].size, "\n");
191 #endif
192 }
193 debug("\nDRAM: ");
194 #else
195 size = gd->ram_size;
196 #endif
197
198 #ifdef CONFIG_BIDRAM
199 size += bidram_append_size();
200 #endif
201
202 #ifndef CONFIG_SUPPORT_USBPLUG
203 print_size(size, "");
204 board_add_ram_info(0);
205 putc('\n');
206 #endif
207 return 0;
208 }
209
dram_init_banksize(void)210 __weak int dram_init_banksize(void)
211 {
212 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
213 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
214 gd->bd->bi_dram[0].size = get_effective_memsize();
215 #endif
216
217 return 0;
218 }
219
220 #if defined(CONFIG_SYS_I2C)
init_func_i2c(void)221 static int init_func_i2c(void)
222 {
223 puts("I2C: ");
224 #ifdef CONFIG_SYS_I2C
225 i2c_init_all();
226 #else
227 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
228 #endif
229 puts("ready\n");
230 return 0;
231 }
232 #endif
233
234 #if defined(CONFIG_HARD_SPI)
init_func_spi(void)235 static int init_func_spi(void)
236 {
237 puts("SPI: ");
238 spi_init();
239 puts("ready\n");
240 return 0;
241 }
242 #endif
243
setup_mon_len(void)244 static int setup_mon_len(void)
245 {
246 #if defined(__ARM__) || defined(__MICROBLAZE__)
247 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
248 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
249 gd->mon_len = (ulong)&_end - (ulong)_init;
250 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
251 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
252 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
253 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
254 #elif defined(CONFIG_SYS_MONITOR_BASE)
255 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
256 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
257 #endif
258 #ifdef CONFIG_MP_BOOT
259 mpb_init_x(3);
260 #endif
261 return 0;
262 }
263
arch_cpu_init(void)264 __weak int arch_cpu_init(void)
265 {
266 return 0;
267 }
268
mach_cpu_init(void)269 __weak int mach_cpu_init(void)
270 {
271 return 0;
272 }
273
274 /* Get the top of usable RAM */
board_get_usable_ram_top(ulong total_size)275 __weak ulong board_get_usable_ram_top(ulong total_size)
276 {
277 #ifdef CONFIG_SYS_SDRAM_BASE
278 /*
279 * Detect whether we have so much RAM that it goes past the end of our
280 * 32-bit address space. If so, clip the usable RAM so it doesn't.
281 */
282 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
283 /*
284 * Will wrap back to top of 32-bit space when reservations
285 * are made.
286 */
287 return 0;
288 #endif
289 return gd->ram_top;
290 }
291
setup_dest_addr(void)292 static int setup_dest_addr(void)
293 {
294 debug("Monitor len: %08lX\n", gd->mon_len);
295 /*
296 * Ram is setup, size stored in gd !!
297 */
298 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
299 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
300 /*
301 * Subtract specified amount of memory to hide so that it won't
302 * get "touched" at all by U-Boot. By fixing up gd->ram_size
303 * the Linux kernel should now get passed the now "corrected"
304 * memory size and won't touch it either. This should work
305 * for arch/ppc and arch/powerpc. Only Linux board ports in
306 * arch/powerpc with bootwrapper support, that recalculate the
307 * memory size from the SDRAM controller setup will have to
308 * get fixed.
309 */
310 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
311 #endif
312 #ifdef CONFIG_SYS_SDRAM_BASE
313 gd->ram_top = CONFIG_SYS_SDRAM_BASE;
314 #endif
315 gd->ram_top += get_effective_memsize();
316 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
317 gd->relocaddr = gd->ram_top;
318 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
319 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
320 /*
321 * We need to make sure the location we intend to put secondary core
322 * boot code is reserved and not used by any part of u-boot
323 */
324 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
325 gd->relocaddr = determine_mp_bootpg(NULL);
326 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
327 }
328 #endif
329 return 0;
330 }
331
332 #ifdef CONFIG_PRAM
333 /* reserve protected RAM */
reserve_pram(void)334 static int reserve_pram(void)
335 {
336 ulong reg;
337
338 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
339 gd->relocaddr -= (reg << 10); /* size is in kB */
340 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
341 gd->relocaddr);
342 return 0;
343 }
344 #endif /* CONFIG_PRAM */
345
346 /* Round memory pointer down to next 4 kB limit */
reserve_round_4k(void)347 static int reserve_round_4k(void)
348 {
349 gd->relocaddr &= ~(4096 - 1);
350 return 0;
351 }
352
353 #ifdef CONFIG_ARM
reserve_mmu(void)354 __weak int reserve_mmu(void)
355 {
356 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
357 /* reserve TLB table */
358 gd->arch.tlb_size = PGTABLE_SIZE;
359 gd->relocaddr -= gd->arch.tlb_size;
360
361 /* round down to next 64 kB limit */
362 gd->relocaddr &= ~(0x10000 - 1);
363
364 gd->arch.tlb_addr = gd->relocaddr;
365 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
366 gd->arch.tlb_addr + gd->arch.tlb_size);
367
368 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
369 /*
370 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
371 * with location within secure ram.
372 */
373 gd->arch.tlb_allocated = gd->arch.tlb_addr;
374 #endif
375 #endif
376
377 return 0;
378 }
379 #endif
380
reserve_video(void)381 static int reserve_video(void)
382 {
383 #ifdef CONFIG_DM_VIDEO
384 ulong addr;
385 int ret;
386
387 addr = gd->relocaddr;
388 ret = video_reserve(&addr);
389 if (ret)
390 return ret;
391 gd->relocaddr = addr;
392 #elif defined(CONFIG_LCD)
393 # ifdef CONFIG_FB_ADDR
394 gd->fb_base = CONFIG_FB_ADDR;
395 # else
396 /* reserve memory for LCD display (always full pages) */
397 gd->relocaddr = lcd_setmem(gd->relocaddr);
398 gd->fb_base = gd->relocaddr;
399 # endif /* CONFIG_FB_ADDR */
400 #elif defined(CONFIG_VIDEO) && \
401 (!defined(CONFIG_PPC)) && \
402 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
403 !defined(CONFIG_M68K)
404 /* reserve memory for video display (always full pages) */
405 gd->relocaddr = video_setmem(gd->relocaddr);
406 gd->fb_base = gd->relocaddr;
407 #endif
408
409 return 0;
410 }
411
reserve_trace(void)412 static int reserve_trace(void)
413 {
414 #ifdef CONFIG_TRACE
415 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
416 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
417 debug("Reserving %dk for trace data at: %08lx\n",
418 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
419 #endif
420
421 return 0;
422 }
423
reserve_uboot(void)424 static int reserve_uboot(void)
425 {
426 /*
427 * reserve memory for U-Boot code, data & bss
428 * round down to next 4 kB limit
429 */
430 gd->relocaddr -= gd->mon_len;
431 gd->relocaddr &= ~(4096 - 1);
432 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
433 /* round down to next 64 kB limit so that IVPR stays aligned */
434 gd->relocaddr &= ~(65536 - 1);
435 #endif
436
437 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
438 gd->relocaddr);
439
440 gd->start_addr_sp = gd->relocaddr;
441
442 return 0;
443 }
444
445 /* reserve memory for malloc() area */
reserve_malloc(void)446 static int reserve_malloc(void)
447 {
448 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
449 debug("Reserving %dk for malloc() at: %08lx\n",
450 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
451 return 0;
452 }
453
454 #ifdef CONFIG_SYS_NONCACHED_MEMORY
reserve_noncached(void)455 static int reserve_noncached(void)
456 {
457 phys_addr_t start, end;
458 size_t size;
459
460 end = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
461 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
462 start = end - size;
463 gd->start_addr_sp = start;
464 debug("Reserving %zu for noncached_alloc() at: %08lx\n",
465 size, gd->start_addr_sp);
466
467 return 0;
468 }
469 #endif
470
471 /* (permanently) allocate a Board Info struct */
reserve_board(void)472 static int reserve_board(void)
473 {
474 if (!gd->bd) {
475 gd->start_addr_sp -= sizeof(bd_t);
476 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
477 memset(gd->bd, '\0', sizeof(bd_t));
478 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
479 sizeof(bd_t), gd->start_addr_sp);
480 }
481 return 0;
482 }
483
setup_machine(void)484 static int setup_machine(void)
485 {
486 #ifdef CONFIG_MACH_TYPE
487 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
488 #endif
489 return 0;
490 }
491
reserve_global_data(void)492 static int reserve_global_data(void)
493 {
494 gd->start_addr_sp -= sizeof(gd_t);
495 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
496 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
497 sizeof(gd_t), gd->start_addr_sp);
498 return 0;
499 }
500
reserve_fdt(void)501 static int reserve_fdt(void)
502 {
503 #ifndef CONFIG_OF_EMBED
504 /*
505 * If the device tree is sitting immediately above our image then we
506 * must relocate it. If it is embedded in the data section, then it
507 * will be relocated with other data.
508 */
509 if (gd->fdt_blob) {
510 u32 extrasize = 0;
511
512 if (gd->fdt_blob_kern)
513 extrasize = fdt_totalsize(gd->fdt_blob_kern);
514 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + extrasize + 0x1000, 32);
515 gd->start_addr_sp -= gd->fdt_size;
516
517 /* 8-byte align */
518 gd->start_addr_sp -= 8;
519 gd->start_addr_sp &= ~0x7;
520 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
521
522 if (gd->fdt_blob_kern)
523 gd->fdt_blob_kern = (ulong *)ALIGN((ulong)gd->new_fdt +
524 fdt_totalsize(gd->fdt_blob), 8);
525 debug("Reserving %lu Bytes for FDT at: %08lx\n",
526 gd->fdt_size, gd->start_addr_sp);
527 }
528 #endif
529
530 return 0;
531 }
532
reserve_bootstage(void)533 static int reserve_bootstage(void)
534 {
535 #ifdef CONFIG_BOOTSTAGE
536 int size = bootstage_get_size();
537
538 gd->start_addr_sp -= size;
539 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
540 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
541 gd->start_addr_sp);
542 #endif
543
544 return 0;
545 }
546
arch_reserve_stacks(void)547 int arch_reserve_stacks(void)
548 {
549 return 0;
550 }
551
reserve_stacks(void)552 static int reserve_stacks(void)
553 {
554 /* make stack pointer 16-byte aligned */
555 gd->start_addr_sp -= 16;
556 gd->start_addr_sp &= ~0xf;
557
558 /*
559 * let the architecture-specific code tailor gd->start_addr_sp and
560 * gd->irq_sp
561 */
562 return arch_reserve_stacks();
563 }
564
display_new_sp(void)565 static int display_new_sp(void)
566 {
567 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
568
569 return 0;
570 }
571
572 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
573 defined(CONFIG_SH)
setup_board_part1(void)574 static int setup_board_part1(void)
575 {
576 bd_t *bd = gd->bd;
577
578 /*
579 * Save local variables to board info struct
580 */
581 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
582 bd->bi_memsize = gd->ram_size; /* size in bytes */
583
584 #ifdef CONFIG_SYS_SRAM_BASE
585 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
586 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
587 #endif
588
589 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
590 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
591 #endif
592 #if defined(CONFIG_M68K)
593 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
594 #endif
595 #if defined(CONFIG_MPC83xx)
596 bd->bi_immrbar = CONFIG_SYS_IMMR;
597 #endif
598
599 return 0;
600 }
601 #endif
602
603 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
setup_board_part2(void)604 static int setup_board_part2(void)
605 {
606 bd_t *bd = gd->bd;
607
608 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
609 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
610 #if defined(CONFIG_CPM2)
611 bd->bi_cpmfreq = gd->arch.cpm_clk;
612 bd->bi_brgfreq = gd->arch.brg_clk;
613 bd->bi_sccfreq = gd->arch.scc_clk;
614 bd->bi_vco = gd->arch.vco_out;
615 #endif /* CONFIG_CPM2 */
616 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
617 bd->bi_pcifreq = gd->pci_clk;
618 #endif
619 #if defined(CONFIG_EXTRA_CLOCK)
620 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
621 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
622 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
623 #endif
624
625 return 0;
626 }
627 #endif
628
629 #ifdef CONFIG_POST
init_post(void)630 static int init_post(void)
631 {
632 post_bootmode_init();
633 post_run(NULL, POST_ROM | post_bootmode_get(0));
634
635 return 0;
636 }
637 #endif
638
reloc_fdt(void)639 static int reloc_fdt(void)
640 {
641 #ifndef CONFIG_OF_EMBED
642 if (gd->flags & GD_FLG_SKIP_RELOC)
643 return 0;
644 if (gd->new_fdt) {
645 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
646 gd->fdt_blob = gd->new_fdt;
647 #ifdef CONFIG_USING_KERNEL_DTB
648 gd->ufdt_blob = gd->new_fdt;
649 #endif
650 }
651 #endif
652
653 return 0;
654 }
655
reloc_bootstage(void)656 static int reloc_bootstage(void)
657 {
658 #ifdef CONFIG_BOOTSTAGE
659 if (gd->flags & GD_FLG_SKIP_RELOC)
660 return 0;
661 if (gd->new_bootstage) {
662 int size = bootstage_get_size();
663
664 debug("Copying bootstage from %p to %p, size %x\n",
665 gd->bootstage, gd->new_bootstage, size);
666 memcpy(gd->new_bootstage, gd->bootstage, size);
667 gd->bootstage = gd->new_bootstage;
668 }
669 #endif
670
671 return 0;
672 }
673
setup_reloc(void)674 static int setup_reloc(void)
675 {
676 if (gd->flags & GD_FLG_SKIP_RELOC) {
677 debug("Skipping relocation due to flag\n");
678 return 0;
679 }
680
681 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
682 #ifdef CONFIG_SYS_TEXT_BASE
683 #ifdef ARM
684 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
685 #elif defined(CONFIG_M68K)
686 /*
687 * On all ColdFire arch cpu, monitor code starts always
688 * just after the default vector table location, so at 0x400
689 */
690 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
691 #else
692 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
693 #endif
694 #endif
695
696 #else
697 gd->reloc_off = 0;
698 #endif
699 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
700
701 #ifndef CONFIG_SUPPORT_USBPLUG
702 printf("Relocation Offset: %08lx\n", gd->reloc_off);
703
704 printf("Relocation fdt: %08lx - %08lx", (ulong)gd->new_fdt,
705 (ulong)gd->new_fdt + fdt_totalsize(gd->fdt_blob));
706 if (gd->fdt_blob_kern) {
707 printf(", kfdt: %08lx - %08lx", (ulong)gd->fdt_blob_kern,
708 (ulong)gd->fdt_blob_kern + fdt_totalsize(gd->fdt_blob_kern));
709 }
710 puts("\n");
711 #endif
712 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
713 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
714 gd->start_addr_sp);
715
716 return 0;
717 }
718
719 #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt(void)720 static int fix_fdt(void)
721 {
722 return board_fix_fdt((void *)gd->fdt_blob);
723 }
724 #endif
725
726 /* ARM calls relocate_code from its crt0.S */
727 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
728 !CONFIG_IS_ENABLED(X86_64)
729
jump_to_copy(void)730 static int jump_to_copy(void)
731 {
732 if (gd->flags & GD_FLG_SKIP_RELOC)
733 return 0;
734 /*
735 * x86 is special, but in a nice way. It uses a trampoline which
736 * enables the dcache if possible.
737 *
738 * For now, other archs use relocate_code(), which is implemented
739 * similarly for all archs. When we do generic relocation, hopefully
740 * we can make all archs enable the dcache prior to relocation.
741 */
742 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
743 /*
744 * SDRAM and console are now initialised. The final stack can now
745 * be setup in SDRAM. Code execution will continue in Flash, but
746 * with the stack in SDRAM and Global Data in temporary memory
747 * (CPU cache)
748 */
749 arch_setup_gd(gd->new_gd);
750 board_init_f_r_trampoline(gd->start_addr_sp);
751 #else
752 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
753 #endif
754
755 return 0;
756 }
757 #endif
758
759 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
initf_bootstage(void)760 static int initf_bootstage(void)
761 {
762 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
763 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
764 int ret;
765
766 ret = bootstage_init(!from_spl);
767 if (ret)
768 return ret;
769 if (from_spl) {
770 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
771 CONFIG_BOOTSTAGE_STASH_SIZE);
772
773 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
774 if (ret && ret != -ENOENT) {
775 debug("Failed to unstash bootstage: err=%d\n", ret);
776 return ret;
777 }
778 }
779
780 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
781
782 return 0;
783 }
784
initf_console_record(void)785 static int initf_console_record(void)
786 {
787 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
788 return console_record_init();
789 #else
790 return 0;
791 #endif
792 }
793
initf_dm(void)794 static int initf_dm(void)
795 {
796 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
797 int ret;
798
799 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
800 ret = dm_init_and_scan(true);
801 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
802 if (ret)
803 return ret;
804 #endif
805 #ifdef CONFIG_TIMER_EARLY
806 ret = dm_timer_init();
807 if (ret)
808 return ret;
809 #endif
810
811 return 0;
812 }
813
814 /* Architecture-specific memory reservation */
reserve_arch(void)815 __weak int reserve_arch(void)
816 {
817 return 0;
818 }
819
arch_cpu_init_dm(void)820 __weak int arch_cpu_init_dm(void)
821 {
822 return 0;
823 }
824
825 static const init_fnc_t init_sequence_f[] = {
826 setup_mon_len,
827 #ifdef CONFIG_OF_CONTROL
828 fdtdec_setup,
829 #endif
830 #ifdef CONFIG_TRACE
831 trace_early_init,
832 #endif
833 initf_malloc,
834 log_init,
835 initf_bootstage, /* uses its own timer, so does not need DM */
836 initf_console_record,
837 #if defined(CONFIG_HAVE_FSP)
838 arch_fsp_init,
839 #endif
840 arch_cpu_init, /* basic arch cpu dependent setup */
841 mach_cpu_init, /* SoC/machine dependent CPU setup */
842 initf_dm,
843 arch_cpu_init_dm,
844 #if defined(CONFIG_BOARD_EARLY_INIT_F)
845 board_early_init_f,
846 #endif
847 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
848 /* get CPU and bus clocks according to the environment variable */
849 get_clocks, /* get CPU and bus clocks (etc.) */
850 #endif
851 #if !defined(CONFIG_M68K)
852 timer_init, /* initialize timer */
853 #endif
854 #if defined(CONFIG_BOARD_POSTCLK_INIT)
855 board_postclk_init,
856 #endif
857 env_init, /* initialize environment */
858 init_baud_rate, /* initialze baudrate settings */
859 serial_init, /* serial communications setup */
860 console_init_f, /* stage 1 init of console */
861 display_options, /* say that we are here */
862 display_text_info, /* show debugging info if required */
863 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \
864 defined(CONFIG_X86)
865 checkcpu,
866 #endif
867 #if defined(CONFIG_DISPLAY_CPUINFO)
868 print_cpuinfo, /* display cpu info (and speed) */
869 #endif
870 #if defined(CONFIG_DTB_RESELECT)
871 embedded_dtb_select,
872 #endif
873 #if defined(CONFIG_DISPLAY_BOARDINFO)
874 show_board_info,
875 #endif
876 INIT_FUNC_WATCHDOG_INIT
877 #if defined(CONFIG_MISC_INIT_F)
878 misc_init_f,
879 #endif
880 INIT_FUNC_WATCHDOG_RESET
881 #if defined(CONFIG_SYS_I2C)
882 init_func_i2c,
883 #endif
884 #if defined(CONFIG_HARD_SPI)
885 init_func_spi,
886 #endif
887 announce_serial,
888
889 announce_dram_init,
890 dram_init, /* configure available RAM banks */
891 #ifdef CONFIG_POST
892 post_init_f,
893 #endif
894 INIT_FUNC_WATCHDOG_RESET
895 #if defined(CONFIG_SYS_DRAM_TEST)
896 testdram,
897 #endif /* CONFIG_SYS_DRAM_TEST */
898 INIT_FUNC_WATCHDOG_RESET
899
900 #ifdef CONFIG_POST
901 init_post,
902 #endif
903 INIT_FUNC_WATCHDOG_RESET
904 /*
905 * Now that we have DRAM mapped and working, we can
906 * relocate the code and continue running from DRAM.
907 *
908 * Reserve memory at end of RAM for (top down in that order):
909 * - area that won't get touched by U-Boot and Linux (optional)
910 * - kernel log buffer
911 * - protected RAM
912 * - LCD framebuffer
913 * - monitor code
914 * - board info struct
915 */
916 setup_dest_addr,
917 #ifdef CONFIG_PRAM
918 reserve_pram,
919 #endif
920 reserve_round_4k,
921 #ifdef CONFIG_ARM
922 reserve_mmu,
923 #endif
924 reserve_video,
925 reserve_trace,
926 reserve_uboot,
927 reserve_malloc,
928 #ifdef CONFIG_SYS_NONCACHED_MEMORY
929 reserve_noncached,
930 #endif
931 reserve_board,
932 setup_machine,
933 reserve_global_data,
934 reserve_fdt,
935 reserve_bootstage,
936 reserve_arch,
937 reserve_stacks,
938 dram_init_banksize,
939 show_dram_config,
940 #ifdef CONFIG_SYSMEM
941 sysmem_init, /* Validate above reserve memory */
942 #endif
943 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
944 defined(CONFIG_SH)
945 setup_board_part1,
946 #endif
947 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
948 INIT_FUNC_WATCHDOG_RESET
949 setup_board_part2,
950 #endif
951 display_new_sp,
952 #ifdef CONFIG_OF_BOARD_FIXUP
953 fix_fdt,
954 #endif
955 INIT_FUNC_WATCHDOG_RESET
956 reloc_fdt,
957 reloc_bootstage,
958 setup_reloc,
959 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
960 copy_uboot_to_ram,
961 do_elf_reloc_fixups,
962 clear_bss,
963 #endif
964 #if defined(CONFIG_XTENSA)
965 clear_bss,
966 #endif
967 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
968 !CONFIG_IS_ENABLED(X86_64)
969 jump_to_copy,
970 #endif
971 NULL,
972 };
973
board_init_f(ulong boot_flags)974 void board_init_f(ulong boot_flags)
975 {
976 gd->flags = boot_flags;
977 gd->have_console = 0;
978
979 if (initcall_run_list(init_sequence_f))
980 hang();
981
982 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
983 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
984 /* NOTREACHED - jump_to_copy() does not return */
985 hang();
986 #endif
987 }
988
989 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
990 /*
991 * For now this code is only used on x86.
992 *
993 * init_sequence_f_r is the list of init functions which are run when
994 * U-Boot is executing from Flash with a semi-limited 'C' environment.
995 * The following limitations must be considered when implementing an
996 * '_f_r' function:
997 * - 'static' variables are read-only
998 * - Global Data (gd->xxx) is read/write
999 *
1000 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1001 * supported). It _should_, if possible, copy global data to RAM and
1002 * initialise the CPU caches (to speed up the relocation process)
1003 *
1004 * NOTE: At present only x86 uses this route, but it is intended that
1005 * all archs will move to this when generic relocation is implemented.
1006 */
1007 static const init_fnc_t init_sequence_f_r[] = {
1008 #if !CONFIG_IS_ENABLED(X86_64)
1009 init_cache_f_r,
1010 #endif
1011
1012 NULL,
1013 };
1014
board_init_f_r(void)1015 void board_init_f_r(void)
1016 {
1017 if (initcall_run_list(init_sequence_f_r))
1018 hang();
1019
1020 /*
1021 * The pre-relocation drivers may be using memory that has now gone
1022 * away. Mark serial as unavailable - this will fall back to the debug
1023 * UART if available.
1024 *
1025 * Do the same with log drivers since the memory may not be available.
1026 */
1027 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1028 #ifdef CONFIG_TIMER
1029 gd->timer = NULL;
1030 #endif
1031
1032 /*
1033 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1034 * Transfer execution from Flash to RAM by calculating the address
1035 * of the in-RAM copy of board_init_r() and calling it
1036 */
1037 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1038
1039 /* NOTREACHED - board_init_r() does not return */
1040 hang();
1041 }
1042 #endif /* CONFIG_X86 */
1043