1/* 2 * Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <common/bl_common.h> 11#include <el3_common_macros.S> 12#include <lib/pmf/aarch64/pmf_asm_macros.S> 13#include <lib/runtime_instr.h> 14#include <lib/xlat_tables/xlat_mmu_helpers.h> 15 16 .globl bl31_entrypoint 17 .globl bl31_warm_entrypoint 18 19 /* ----------------------------------------------------- 20 * bl31_entrypoint() is the cold boot entrypoint, 21 * executed only by the primary cpu. 22 * ----------------------------------------------------- 23 */ 24 25func bl31_entrypoint 26 /* --------------------------------------------------------------- 27 * Stash the previous bootloader arguments x0 - x3 for later use. 28 * --------------------------------------------------------------- 29 */ 30 mov x20, x0 31 mov x21, x1 32 mov x22, x2 33 mov x23, x3 34 35#if !RESET_TO_BL31 36 /* --------------------------------------------------------------------- 37 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches 38 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot 39 * and primary/secondary CPU logic should not be executed in this case. 40 * 41 * Also, assume that the previous bootloader has already initialised the 42 * SCTLR_EL3, including the endianness, and has initialised the memory. 43 * --------------------------------------------------------------------- 44 */ 45 el3_entrypoint_common \ 46 _init_sctlr=0 \ 47 _warm_boot_mailbox=0 \ 48 _secondary_cold_boot=0 \ 49 _init_memory=0 \ 50 _init_c_runtime=1 \ 51 _exception_vectors=runtime_exceptions \ 52 _pie_fixup_size=BL31_LIMIT - BL31_BASE 53#else 54 55 /* --------------------------------------------------------------------- 56 * For RESET_TO_BL31 systems which have a programmable reset address, 57 * bl31_entrypoint() is executed only on the cold boot path so we can 58 * skip the warm boot mailbox mechanism. 59 * --------------------------------------------------------------------- 60 */ 61 el3_entrypoint_common \ 62 _init_sctlr=1 \ 63 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 64 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 65 _init_memory=1 \ 66 _init_c_runtime=1 \ 67 _exception_vectors=runtime_exceptions \ 68 _pie_fixup_size=BL31_LIMIT - BL31_BASE 69#endif /* RESET_TO_BL31 */ 70 71 /* -------------------------------------------------------------------- 72 * Perform BL31 setup 73 * -------------------------------------------------------------------- 74 */ 75 mov x0, x20 76 mov x1, x21 77 mov x2, x22 78 mov x3, x23 79 80 /* -------------------------------------------------------------------- 81 * Jump to main function 82 * -------------------------------------------------------------------- 83 */ 84 bl bl31_main 85 86 /* -------------------------------------------------------------------- 87 * Clean the .data & .bss sections to main memory. This ensures 88 * that any global data which was initialised by the primary CPU 89 * is visible to secondary CPUs before they enable their data 90 * caches and participate in coherency. 91 * -------------------------------------------------------------------- 92 */ 93 adrp x0, __DATA_START__ 94 add x0, x0, :lo12:__DATA_START__ 95 adrp x1, __DATA_END__ 96 add x1, x1, :lo12:__DATA_END__ 97 sub x1, x1, x0 98 bl clean_dcache_range 99 100 adrp x0, __BSS_START__ 101 add x0, x0, :lo12:__BSS_START__ 102 adrp x1, __BSS_END__ 103 add x1, x1, :lo12:__BSS_END__ 104 sub x1, x1, x0 105 bl clean_dcache_range 106 107 adrp x0, __PER_CPU_START__ 108 add x0, x0, :lo12:__PER_CPU_START__ 109 adrp x1, __PER_CPU_END__ 110 add x1, x1, :lo12:__PER_CPU_END__ 111 sub x1, x1, x0 112 bl clean_dcache_range 113 114#if (PLATFORM_NODE_COUNT > 1) 115 /* 116 * dcache clean per-cpu sections defined by the platform. 117 * Care must be taken to preserve and retain the clobbered 118 * registers. A standard around the container for per-cpu nodes 119 * is not yet defined. 120 */ 121 122 bl plat_per_cpu_dcache_clean 123#endif /* (PLATFORM_NODE_COUNT > 1) */ 124 b el3_exit 125endfunc bl31_entrypoint 126 127 /* -------------------------------------------------------------------- 128 * This CPU has been physically powered up. It is either resuming from 129 * suspend or has simply been turned on. In both cases, call the BL31 130 * warmboot entrypoint 131 * -------------------------------------------------------------------- 132 */ 133func bl31_warm_entrypoint 134#if ENABLE_RUNTIME_INSTRUMENTATION 135 136 /* 137 * This timestamp update happens with cache off. The next 138 * timestamp collection will need to do cache maintenance prior 139 * to timestamp update. 140 */ 141 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR 142 mrs x1, cntpct_el0 143 str x1, [x0] 144#endif 145 146 /* 147 * On the warm boot path, most of the EL3 initialisations performed by 148 * 'el3_entrypoint_common' must be skipped: 149 * 150 * - Only when the platform bypasses the BL1/BL31 entrypoint by 151 * programming the reset address do we need to initialise SCTLR_EL3. 152 * In other cases, we assume this has been taken care by the 153 * entrypoint code. 154 * 155 * - No need to determine the type of boot, we know it is a warm boot. 156 * 157 * - Do not try to distinguish between primary and secondary CPUs, this 158 * notion only exists for a cold boot. 159 * 160 * - No need to initialise the memory or the C runtime environment, 161 * it has been done once and for all on the cold boot path. 162 */ 163 el3_entrypoint_common \ 164 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \ 165 _warm_boot_mailbox=0 \ 166 _secondary_cold_boot=0 \ 167 _init_memory=0 \ 168 _init_c_runtime=0 \ 169 _exception_vectors=runtime_exceptions \ 170 _pie_fixup_size=0 171 172 bl bl31_warmboot 173 174#if ENABLE_RUNTIME_INSTRUMENTATION 175 pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI 176 mov x19, x0 177 178 /* 179 * Invalidate before updating timestamp to ensure previous timestamp 180 * updates on the same cache line with caches disabled are properly 181 * seen by the same core. Without the cache invalidate, the core might 182 * write into a stale cache line. 183 */ 184 mov x1, #PMF_TS_SIZE 185 mov x20, x30 186 bl inv_dcache_range 187 mov x30, x20 188 189 mrs x0, cntpct_el0 190 str x0, [x19] 191#endif 192 b el3_exit 193endfunc bl31_warm_entrypoint 194