1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RV1108_H 8 #define _ASM_ARCH_SDRAM_RV1108_H 9 10 #include <common.h> 11 #include <ram.h> 12 #include <asm/arch/cru_rv1108.h> 13 #include <asm/arch/grf_rv1108.h> 14 #include <asm/arch/pmu_rv1108.h> 15 #include <asm/arch/sdram_rv1108_pctl_phy.h> 16 17 #define SR_IDLE 3 18 #define PD_IDLE 64 19 #define SDRAM_BEGIN_ADDR 0x60000000 20 #define SDRAM_END_ADDR 0x80000000 21 #define PATTERN (0x5aa5f00f) 22 23 struct rv1108_service_msch { 24 u32 id_coreid; 25 u32 id_revisionid; 26 u32 ddrconf; 27 u32 ddrtiming; 28 u32 ddrmode; 29 u32 readlatency; 30 u32 reserveds1[8]; 31 u32 activate; 32 u32 devtodev; 33 }; 34 35 enum { 36 /*memory scheduler ddrtiming*/ 37 BWRATIO_HALF_BW = 0x80000000, 38 BWRATIO_HALF_BW_DIS = 0x0, 39 }; 40 41 struct dram_info { 42 struct rv1108_cru *cru; 43 struct rv1108_grf *grf; 44 struct rv1108_pmu *pmu; 45 struct rv1108_pmu_grf *pmu_grf; 46 struct ddr_phy *phy; 47 struct ddr_pctl *pctl; 48 struct rv1108_service_msch *service_msch; 49 struct ram_info info; 50 }; 51 52 struct sdram_params { 53 u32 ddr_2t_en; 54 struct ddr_config ddr_config_t; 55 struct pll_div dpll_init_cfg; 56 struct ddr_timing ddr_timing_t; 57 }; 58 59 int check_rd_gate(struct dram_info *priv); 60 void enable_low_power(struct dram_info *priv, 61 struct sdram_params *params_priv); 62 void ddr_msch_cfg(struct dram_info *priv, 63 struct sdram_params *params_priv); 64 void ddr_msch_cfg_rbc(struct sdram_params *params_priv, 65 struct dram_info *priv); 66 void ddr_msch_get_max_col(struct dram_info *priv, 67 struct ddr_schedule *sch_priv); 68 void ddr_msch_get_max_row(struct dram_info *priv, 69 struct ddr_schedule *sch_priv); 70 void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq); 71 void ddr_phy_skew_cfg(struct dram_info *priv); 72 void enable_ddr_io_ret(struct dram_info *priv); 73 void modify_data_training(struct dram_info *priv, 74 struct sdram_params *params_priv); 75 void move_to_config_state(struct dram_info *priv); 76 void pctl_cfg_grf(struct dram_info *priv, 77 struct sdram_params *params_priv); 78 void phy_pctrl_reset_cru(struct dram_info *priv); 79 void rkdclk_init(struct dram_info *priv, 80 struct sdram_params *params_priv); 81 int rv1108_sdram_init(struct dram_info *sdram_priv, 82 struct sdram_params *params_priv); 83 void set_bw_grf(struct dram_info *priv); 84 void set_ds_odt(struct dram_info *priv, 85 struct sdram_params *params_priv); 86 87 #endif 88