1 /* 2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_RK3399_H 8 #define _ASM_ARCH_SDRAM_RK3399_H 9 #include <asm/arch/sdram_common.h> 10 #include <asm/arch/sdram_msch.h> 11 12 struct rk3399_ddr_pctl_regs { 13 u32 denali_ctl[332]; 14 }; 15 16 struct rk3399_ddr_publ_regs { 17 u32 denali_phy[959]; 18 }; 19 20 struct rk3399_ddr_pi_regs { 21 u32 denali_pi[200]; 22 }; 23 24 struct rk3399_ddr_cic_regs { 25 u32 cic_ctrl0; 26 u32 cic_ctrl1; 27 u32 cic_idle_th; 28 u32 cic_cg_wait_th; 29 u32 cic_status0; 30 u32 cic_status1; 31 u32 cic_ctrl2; 32 u32 cic_ctrl3; 33 u32 cic_ctrl4; 34 }; 35 36 /* DENALI_CTL_00 */ 37 #define START 1 38 39 /* DENALI_CTL_68 */ 40 #define PWRUP_SREFRESH_EXIT (1 << 16) 41 42 /* DENALI_CTL_274 */ 43 #define MEM_RST_VALID 1 44 45 struct msch_regs { 46 u32 coreid; 47 u32 revisionid; 48 u32 ddrconf; 49 u32 ddrsize; 50 union noc_ddrtiminga0 ddrtiminga0; 51 union noc_ddrtimingb0 ddrtimingb0; 52 union noc_ddrtimingc0 ddrtimingc0; 53 union noc_devtodev0 devtodev0; 54 u32 reserved0[(0x110 - 0x20) / 4]; 55 union noc_ddrmode ddrmode; 56 u32 reserved1[(0x1000 - 0x114) / 4]; 57 u32 agingx0; 58 }; 59 60 struct sdram_msch_timings { 61 union noc_ddrtiminga0 ddrtiminga0; 62 union noc_ddrtimingb0 ddrtimingb0; 63 union noc_ddrtimingc0 ddrtimingc0; 64 union noc_devtodev0 devtodev0; 65 union noc_ddrmode ddrmode; 66 u32 agingx0; 67 }; 68 69 struct rk3399_sdram_channel { 70 struct sdram_cap_info cap_info; 71 struct sdram_msch_timings noc_timings; 72 }; 73 74 struct rk3399_sdram_params { 75 struct rk3399_sdram_channel ch[2]; 76 struct sdram_base_params base; 77 struct rk3399_ddr_pctl_regs pctl_regs; 78 struct rk3399_ddr_pi_regs pi_regs; 79 struct rk3399_ddr_publ_regs phy_regs; 80 }; 81 82 #define PI_CA_TRAINING (1 << 0) 83 #define PI_WRITE_LEVELING (1 << 1) 84 #define PI_READ_GATE_TRAINING (1 << 2) 85 #define PI_READ_LEVELING (1 << 3) 86 #define PI_WDQ_LEVELING (1 << 4) 87 #define PI_FULL_TRAINING 0xff 88 89 enum { 90 STRIDE_128B = 0, 91 STRIDE_256B = 1, 92 STRIDE_512B = 2, 93 STRIDE_4KB = 3, 94 UN_STRIDE = 4, 95 PART_STRIDE = 5 96 }; 97 98 #endif 99