1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H 7 #define _ASM_ARCH_SDRAM_PCTL_PX30_H 8 #include <asm/arch/sdram_common.h> 9 10 struct ddr_pctl_regs { 11 u32 pctl[35][2]; 12 }; 13 14 /* ddr pctl registers define */ 15 #define DDR_PCTL2_MSTR 0x0 16 #define DDR_PCTL2_STAT 0x4 17 #define DDR_PCTL2_MSTR1 0x8 18 #define DDR_PCTL2_MRCTRL0 0x10 19 #define DDR_PCTL2_MRCTRL1 0x14 20 #define DDR_PCTL2_MRSTAT 0x18 21 #define DDR_PCTL2_MRCTRL2 0x1c 22 #define DDR_PCTL2_DERATEEN 0x20 23 #define DDR_PCTL2_DERATEINT 0x24 24 #define DDR_PCTL2_MSTR2 0x28 25 #define DDR_PCTL2_PWRCTL 0x30 26 #define DDR_PCTL2_PWRTMG 0x34 27 #define DDR_PCTL2_HWLPCTL 0x38 28 #define DDR_PCTL2_RFSHCTL0 0x50 29 #define DDR_PCTL2_RFSHCTL1 0x54 30 #define DDR_PCTL2_RFSHCTL2 0x58 31 #define DDR_PCTL2_RFSHCTL4 0x5c 32 #define DDR_PCTL2_RFSHCTL3 0x60 33 #define DDR_PCTL2_RFSHTMG 0x64 34 #define DDR_PCTL2_RFSHTMG1 0x68 35 #define DDR_PCTL2_RFSHCTL5 0x6c 36 #define DDR_PCTL2_ECCCFG0 0x70 37 #define DDR_PCTL2_ECCCFG1 0x74 38 #define DDR_PCTL2_ECCSTAT 0x78 39 #define DDR_PCTL2_ECCCTL 0x7c 40 #define DDR_PCTL2_ECCERRCNT 0x80 41 #define DDR_PCTL2_ECCCADDR0 0x84 42 #define DDR_PCTL2_ECCCADDR1 0x88 43 #define DDR_PCTL2_ECCCSYN0 0x8c 44 #define DDR_PCTL2_ECCCSYN1 0x90 45 #define DDR_PCTL2_ECCCSYN2 0x94 46 #define DDR_PCTL2_ECCBITMASK0 0x98 47 #define DDR_PCTL2_ECCBITMASK1 0x9c 48 #define DDR_PCTL2_ECCBITMASK2 0xa0 49 #define DDR_PCTL2_ECCUADR0 0xa4 50 #define DDR_PCTL2_ECCUADR1 0xa8 51 #define DDR_PCTL2_ECCUSYNC0 0xac 52 #define DDR_PCTL2_ECCUSYNC1 0xb0 53 #define DDR_PCTL2_ECCUSYNC2 0xb4 54 #define DDR_PCTL2_ECCPOSISONADDR0 0xb8 55 #define DDR_PCTL2_ECCPOSISONADDR1 0xbc 56 #define DDR_PCTL2_INIT0 0xd0 57 #define DDR_PCTL2_INIT1 0xd4 58 #define DDR_PCTL2_INIT2 0xd8 59 #define DDR_PCTL2_INIT3 0xdc 60 #define DDR_PCTL2_INIT4 0xe0 61 #define DDR_PCTL2_INIT5 0xe4 62 #define DDR_PCTL2_INIT6 0xe8 63 #define DDR_PCTL2_INIT7 0xec 64 #define DDR_PCTL2_DIMMCTL 0xf0 65 #define DDR_PCTL2_RANKCTL 0xf4 66 #define DDR_PCTL2_CHCTL 0xfc 67 #define DDR_PCTL2_DRAMTMG0 0x100 68 #define DDR_PCTL2_DRAMTMG1 0x104 69 #define DDR_PCTL2_DRAMTMG2 0x108 70 #define DDR_PCTL2_DRAMTMG3 0x10c 71 #define DDR_PCTL2_DRAMTMG4 0x110 72 #define DDR_PCTL2_DRAMTMG5 0x114 73 #define DDR_PCTL2_DRAMTMG6 0x118 74 #define DDR_PCTL2_DRAMTMG7 0x11c 75 #define DDR_PCTL2_DRAMTMG8 0x120 76 #define DDR_PCTL2_DRAMTMG9 0x124 77 #define DDR_PCTL2_DRAMTMG10 0x128 78 #define DDR_PCTL2_DRAMTMG11 0x12c 79 #define DDR_PCTL2_DRAMTMG12 0x130 80 #define DDR_PCTL2_DRAMTMG13 0x134 81 #define DDR_PCTL2_DRAMTMG14 0x138 82 #define DDR_PCTL2_DRAMTMG15 0x13c 83 #define DDR_PCTL2_DRAMTMG16 0x140 84 #define DDR_PCTL2_ZQCTL0 0x180 85 #define DDR_PCTL2_ZQCTL1 0x184 86 #define DDR_PCTL2_ZQCTL2 0x188 87 #define DDR_PCTL2_ZQSTAT 0x18c 88 #define DDR_PCTL2_DFITMG0 0x190 89 #define DDR_PCTL2_DFITMG1 0x194 90 #define DDR_PCTL2_DFILPCFG0 0x198 91 #define DDR_PCTL2_DFILPCFG1 0x19c 92 #define DDR_PCTL2_DFIUPD0 0x1a0 93 #define DDR_PCTL2_DFIUPD1 0x1a4 94 #define DDR_PCTL2_DFIUPD2 0x1a8 95 #define DDR_PCTL2_DFIMISC 0x1b0 96 #define DDR_PCTL2_DFITMG2 0x1b4 97 #define DDR_PCTL2_DFITMG3 0x1b8 98 #define DDR_PCTL2_DFISTAT 0x1bc 99 #define DDR_PCTL2_DBICTL 0x1c0 100 #define DDR_PCTL2_ADDRMAP0 0x200 101 #define DDR_PCTL2_ADDRMAP1 0x204 102 #define DDR_PCTL2_ADDRMAP2 0x208 103 #define DDR_PCTL2_ADDRMAP3 0x20c 104 #define DDR_PCTL2_ADDRMAP4 0x210 105 #define DDR_PCTL2_ADDRMAP5 0x214 106 #define DDR_PCTL2_ADDRMAP6 0x218 107 #define DDR_PCTL2_ADDRMAP7 0x21c 108 #define DDR_PCTL2_ADDRMAP8 0x220 109 #define DDR_PCTL2_ADDRMAP9 0x224 110 #define DDR_PCTL2_ADDRMAP10 0x228 111 #define DDR_PCTL2_ADDRMAP11 0x22c 112 #define DDR_PCTL2_ODTCFG 0x240 113 #define DDR_PCTL2_ODTMAP 0x244 114 #define DDR_PCTL2_SCHED 0x250 115 #define DDR_PCTL2_SCHED1 0x254 116 #define DDR_PCTL2_PERFHPR1 0x25c 117 #define DDR_PCTL2_PERFLPR1 0x264 118 #define DDR_PCTL2_PERFWR1 0x26c 119 #define DDR_PCTL2_DQMAP0 0x280 120 #define DDR_PCTL2_DQMAP1 0x284 121 #define DDR_PCTL2_DQMAP2 0x288 122 #define DDR_PCTL2_DQMAP3 0x28c 123 #define DDR_PCTL2_DQMAP4 0x290 124 #define DDR_PCTL2_DQMAP5 0x294 125 #define DDR_PCTL2_DBG0 0x300 126 #define DDR_PCTL2_DBG1 0x304 127 #define DDR_PCTL2_DBGCAM 0x308 128 #define DDR_PCTL2_DBGCMD 0x30c 129 #define DDR_PCTL2_DBGSTAT 0x310 130 #define DDR_PCTL2_SWCTL 0x320 131 #define DDR_PCTL2_SWSTAT 0x324 132 #define DDR_PCTL2_POISONCFG 0x36c 133 #define DDR_PCTL2_POISONSTAT 0x370 134 #define DDR_PCTL2_ADVECCINDEX 0x374 135 #define DDR_PCTL2_ADVECCSTAT 0x378 136 #define DDR_PCTL2_PSTAT 0x3fc 137 #define DDR_PCTL2_PCCFG 0x400 138 #define DDR_PCTL2_PCFGR_n 0x404 139 #define DDR_PCTL2_PCFGW_n 0x408 140 #define DDR_PCTL2_PCTRL_n 0x490 141 142 #define UMCTL2_REGS_FREQ(n) \ 143 ((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0))) 144 145 /* PCTL2_MSTR */ 146 #define PCTL2_FREQUENCY_MODE_MASK (1) 147 #define PCTL2_FREQUENCY_MODE_SHIFT (29) 148 #define PCTL2_DLL_OFF_MODE BIT(15) 149 /* PCTL2_STAT */ 150 #define PCTL2_SELFREF_TYPE_MASK (3 << 4) 151 #define PCTL2_SELFREF_TYPE_SR_NOT_AUTO (2 << 4) 152 #define PCTL2_OPERATING_MODE_MASK (7) 153 #define PCTL2_OPERATING_MODE_INIT (0) 154 #define PCTL2_OPERATING_MODE_NORMAL (1) 155 #define PCTL2_OPERATING_MODE_PD (2) 156 #define PCTL2_OPERATING_MODE_SR (3) 157 /* PCTL2_MRCTRL0 */ 158 #define PCTL2_MR_WR BIT(31) 159 #define PCTL2_MR_ADDR_SHIFT (12) 160 #define PCTL2_MR_RANK_SHIFT (4) 161 #define PCTL2_MR_TYPE_WR (0) 162 #define PCTL2_MR_TYPE_RD (1) 163 /* PCTL2_MRCTRL1 */ 164 #define PCTL2_MR_ADDRESS_SHIFT (8) 165 #define PCTL2_MR_DATA_MASK (0xff) 166 /* PCTL2_MRSTAT */ 167 #define PCTL2_MR_WR_BUSY BIT(0) 168 /* PCTL2_DERATEEN */ 169 #define PCTL2_DERATE_ENABLE (1) 170 /* PCTL2_PWRCTL */ 171 #define PCTL2_SELFREF_SW BIT(5) 172 #define PCTL2_POWERDOWN_EN BIT(1) 173 #define PCTL2_SELFREF_EN (1) 174 /* PCTL2_PWRTMG */ 175 #define PCTL2_SELFREF_TO_X32_MASK (0xFF) 176 #define PCTL2_SELFREF_TO_X32_SHIFT (16) 177 #define PCTL2_POWERDOWN_TO_X32_MASK (0x1F) 178 /* PCTL2_INIT3 */ 179 #define PCTL2_DDR34_MR0_SHIFT (16) 180 #define PCTL2_LPDDR234_MR1_SHIFT (16) 181 #define PCTL2_DDR34_MR1_SHIFT (0) 182 #define PCTL2_LPDDR234_MR2_SHIFT (0) 183 /* PCTL2_INIT4 */ 184 #define PCTL2_DDR34_MR2_SHIFT (16) 185 #define PCTL2_LPDDR234_MR3_SHIFT (16) 186 #define PCTL2_DDR34_MR3_SHIFT (0) 187 #define PCTL2_LPDDR4_MR13_SHIFT (0) 188 189 /* PCTL2_INIT6 */ 190 #define PCTL2_DDR4_MR4_SHIFT (16) 191 #define PCTL2_LPDDR4_MR11_SHIFT (16) 192 #define PCTL2_DDR4_MR5_SHIFT (0) 193 #define PCTL2_LPDDR4_MR12_SHIFT (0) 194 195 /* PCTL2_INIT7 */ 196 #define PCTL2_LPDDR4_MR22_SHIFT (16) 197 #define PCTL2_DDR4_MR6_SHIFT (0) 198 #define PCTL2_LPDDR4_MR14_SHIFT (0) 199 200 #define PCTL2_MR_MASK (0xffff) 201 202 /* PCTL2_RFSHCTL3 */ 203 #define PCTL2_DIS_AUTO_REFRESH (1) 204 /* PCTL2_ZQCTL0 */ 205 #define PCTL2_DIS_AUTO_ZQ BIT(31) 206 #define PCTL2_DIS_SRX_ZQCL BIT(30) 207 /* PCTL2_DFILPCFG0 */ 208 #define PCTL2_DFI_LP_EN_SR BIT(8) 209 #define PCTL2_DFI_LP_EN_SR_MASK BIT(8) 210 #define PCTL2_DFI_LP_EN_SR_SHIFT (8) 211 /* PCTL2_DFIMISC */ 212 #define PCTL2_DFI_INIT_COMPLETE_EN (1) 213 /* PCTL2_DFISTAT */ 214 #define PCTL2_DFI_LP_ACK BIT(1) 215 #define PCTL2_DFI_INIT_COMPLETE (1) 216 /* PCTL2_DBG1 */ 217 #define PCTL2_DIS_HIF BIT(1) 218 /* PCTL2_DBGCAM */ 219 #define PCTL2_DBG_WR_Q_EMPTY BIT(26) 220 #define PCTL2_DBG_RD_Q_EMPTY BIT(25) 221 #define PCTL2_DBG_LPR_Q_DEPTH_MASK (0xffff << 8) 222 #define PCTL2_DBG_LPR_Q_DEPTH_EMPTY (0x0 << 8) 223 /* PCTL2_DBGCMD */ 224 #define PCTL2_RANK1_REFRESH BIT(1) 225 #define PCTL2_RANK0_REFRESH (1) 226 /* PCTL2_DBGSTAT */ 227 #define PCTL2_RANK1_REFRESH_BUSY BIT(1) 228 #define PCTL2_RANK0_REFRESH_BUSY (1) 229 /* PCTL2_SWCTL */ 230 #define PCTL2_SW_DONE (1) 231 #define PCTL2_SW_DONE_CLEAR (0) 232 /* PCTL2_SWSTAT */ 233 #define PCTL2_SW_DONE_ACK (1) 234 /* PCTL2_PSTAT */ 235 #define PCTL2_WR_PORT_BUSY_0 BIT(16) 236 #define PCTL2_RD_PORT_BUSY_0 (1) 237 /* PCTL2_PCTRLn */ 238 #define PCTL2_PORT_EN (1) 239 240 /* PCTL2_ECCCFG0 */ 241 #define ECC_MODE_MASK (0x7) 242 #define ECC_MODE_DIS (0) 243 #define ECC_MODE_SEC (0x4) 244 #define ECC_MODE_ADV (0x5) 245 #define ECC_MODE_SHIFT (0) 246 #define ECC_TEST_MODE BIT(3) 247 #define ECC_DIS_SCRUB BIT(4) 248 #define ECC_TYPE_SIDEBAND (0) 249 #define ECC_TYPE_INLINE (1) 250 #define ECC_TYPE_MASK (1) 251 #define ECC_TYPE_SHIFT (5) 252 253 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num); 254 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, 255 u32 dramtype); 256 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate, 257 u32 dramtype); 258 259 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base); 260 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq); 261 262 u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs, 263 struct sdram_cap_info *cap_info, 264 u32 dram_type); 265 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs, 266 u32 sr_idle, u32 pd_idle); 267 268 #endif 269