1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_SHARE_H 7 #define _ASM_ARCH_SDRAM_SHARE_H 8 9 #ifndef MHZ 10 #define MHZ (1000 * 1000) 11 #endif 12 13 #define PATTERN (0x5aa5f00f) 14 15 #define MIN(a, b) (((a) > (b)) ? (b) : (a)) 16 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) 17 18 /* get head info for initial */ 19 #define DDR_FREQ_F0_SHIFT (0) 20 #define DDR_FREQ_F1_SHIFT (12) 21 #define DDR_FREQ_F2_SHIFT (0) 22 #define DDR_FREQ_F3_SHIFT (12) 23 #define DDR_FREQ_F4_SHIFT (0) 24 #define DDR_FREQ_F5_SHIFT (12) 25 #define DDR_FREQ_MASK (0xfff) 26 27 #define UART_INFO_ID_SHIFT (28) 28 #define UART_INFO_IOMUX_SHIFT (24) 29 #define UART_INFO_BAUD_SHIFT (0) 30 #define UART_INFO_ID(n) (((n) >> 28) & 0xf) 31 #define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf) 32 #define UART_INFO_BAUD(n) ((n) & 0xffffff) 33 34 /* g_ch_info[15:0]: g_stdby_idle */ 35 #define STANDBY_IDLE(n) ((n) & 0xffff) 36 37 #define SR_INFO(n) (((n) >> 16) & 0xffff) 38 #define PD_INFO(n) ((n) & 0xffff) 39 40 #define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf) 41 #define CHANNEL_MASK(n) (((n) >> 24) & 0xf) 42 #define STRIDE_TYPE(n) (((n) >> 16) & 0xff) 43 44 #define DDR_2T_INFO(n) ((n) & 1) 45 #define PLL_SSMOD_SPREAD(n) (((n) >> 1) & 0xff) 46 #define PLL_SSMOD_DIV(n) (((n) >> 9) & 0xff) 47 #define PLL_SSMOD_DOWNSPREAD(n) (((n) >> 17) & 0x3) 48 49 /* sdram_head_info_v2 define */ 50 /* for *_drv_odten and *_drv_odtoff */ 51 #define PHY_DQ_DRV_SHIFT 0 52 #define PHY_CA_DRV_SHIFT 8 53 #define PHY_CLK_DRV_SHIFT 16 54 #define DRAM_DQ_DRV_SHIFT 24 55 #define DRV_INFO_PHY_DQ_DRV(n) ((n) & 0xff) 56 #define DRV_INFO_PHY_CA_DRV(n) (((n) >> PHY_CA_DRV_SHIFT) & 0xff) 57 #define DRV_INFO_PHY_CLK_DRV(n) (((n) >> PHY_CLK_DRV_SHIFT) & 0xff) 58 #define DRV_INFO_DRAM_DQ_DRV(n) (((n) >> DRAM_DQ_DRV_SHIFT) & 0xff) 59 60 /* for *_odt_info */ 61 #define DRAM_ODT_SHIFT 0 62 #define PHY_ODT_SHIFT 8 63 #define PHY_ODT_PUUP_EN_SHIFT 18 64 #define PHY_ODT_PUDN_EN_SHIFT 19 65 #define ODT_INFO_DRAM_ODT(n) (((n) >> DRAM_ODT_SHIFT) & 0xff) 66 #define ODT_INFO_PHY_ODT(n) (((n) >> PHY_ODT_SHIFT) & 0x3ff) 67 #define ODT_INFO_PULLUP_EN(n) (((n) >> PHY_ODT_PUUP_EN_SHIFT) & 1) 68 #define ODT_INFO_PULLDOWN_EN(n) (((n) >> PHY_ODT_PUDN_EN_SHIFT) & 1) 69 70 /* for *odt_en_freq; */ 71 #define DRAM_ODT_EN_FREQ_SHIFT 0 72 #define PHY_ODT_EN_FREQ_SHIFT 12 73 #define DRAMODT_EN_FREQ(n) (((n) >> DRAM_ODT_EN_FREQ_SHIFT) & \ 74 0xfff) 75 #define PHYODT_EN_FREQ(n) (((n) >> PHY_ODT_EN_FREQ_SHIFT) & 0xfff) 76 77 #define PHY_DQ_SR_SHIFT 0 78 #define PHY_CA_SR_SHIFT 8 79 #define PHY_CLK_SR_SHIFT 16 80 #define DQ_SR_INFO(n) (((n) >> PHY_DQ_SR_SHIFT) & 0xff) 81 #define CA_SR_INFO(n) (((n) >> PHY_CA_SR_SHIFT) & 0xff) 82 #define CLK_SR_INFO(n) (((n) >> PHY_CLK_SR_SHIFT) & 0xff) 83 84 /* LP4 */ 85 #define LP4_CA_ODT_SHIFT (18) 86 #define LP4_DRV_PU_CAL_ODTEN_SHIFT (26) 87 #define LP4_DRV_PU_CAL_ODTOFF_SHIFT (27) 88 #define PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT (28) 89 #define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT (29) 90 #define ODT_INFO_LP4_CA_ODT(n) (((n) >> LP4_CA_ODT_SHIFT) & \ 91 0xff) 92 #define LP4_DRV_PU_CAL_ODTEN(n) \ 93 (((n) >> LP4_DRV_PU_CAL_ODTEN_SHIFT) & 1) 94 #define LP4_DRV_PU_CAL_ODTOFF(n) \ 95 (((n) >> LP4_DRV_PU_CAL_ODTOFF_SHIFT) & 1) 96 #define PHY_LP4_DRV_PULLDOWN_EN_ODTEN(n) \ 97 (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) & 1) 98 #define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(n) \ 99 (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT) & 1) 100 101 #define PHY_LP4_CS_DRV_ODTEN_SHIFT (0) 102 #define PHY_LP4_CS_DRV_ODTOFF_SHIFT (8) 103 #define LP4_ODTE_CK_SHIFT (16) 104 #define LP4_ODTE_CS_EN_SHIFT (17) 105 #define LP4_ODTD_CA_EN_SHIFT (18) 106 #define PHY_LP4_CS_DRV_ODTEN(n) \ 107 (((n) >> PHY_LP4_CS_DRV_ODTEN_SHIFT) & 0xff) 108 #define PHY_LP4_CS_DRV_ODTOFF(n) \ 109 (((n) >> PHY_LP4_CS_DRV_ODTOFF_SHIFT) & 0xff) 110 #define LP4_ODTE_CK_EN(n) (((n) >> LP4_ODTE_CK_SHIFT) & 1) 111 #define LP4_ODTE_CS_EN(n) (((n) >> LP4_ODTE_CS_EN_SHIFT) & 1) 112 #define LP4_ODTD_CA_EN(n) (((n) >> LP4_ODTD_CA_EN_SHIFT) & 1) 113 114 #define PHY_LP4_DQ_VREF_SHIFT (0) 115 #define LP4_DQ_VREF_SHIFT (10) 116 #define LP4_CA_VREF_SHIFT (20) 117 118 #define PHY_LP4_DQ_VREF(n) \ 119 (((n) >> PHY_LP4_DQ_VREF_SHIFT) & 0x3ff) 120 #define LP4_DQ_VREF(n) (((n) >> LP4_DQ_VREF_SHIFT) & 0x3ff) 121 #define LP4_CA_VREF(n) (((n) >> LP4_CA_VREF_SHIFT) & 0x3ff) 122 123 #define LP4_DQ_ODT_EN_FREQ_SHIFT (0) 124 #define PHY_LP4_ODT_EN_FREQ_SHIFT (12) 125 #define LP4_CA_ODT_EN_FREQ_SHIFT (0) 126 #define PHY_LP4_ODT_EN_FREQ(n) \ 127 (((n) >> PHY_LP4_ODT_EN_FREQ_SHIFT) & 0xfff) 128 #define LP4_DQ_ODT_EN_FREQ(n) \ 129 (((n) >> LP4_DQ_ODT_EN_FREQ_SHIFT) & 0xfff) 130 #define LP4_CA_ODT_EN_FREQ(n) \ 131 (((n) >> LP4_CA_ODT_EN_FREQ_SHIFT) & 0xfff) 132 133 struct sdram_head_info_v0 { 134 u32 start_tag; 135 u32 version_info; 136 u32 gcpu_gen_freq; 137 u32 g_d2_lp2_freq; 138 u32 g_d3_lp3_freq; 139 u32 g_d4_lp4_freq; 140 u32 g_uart_info; 141 u32 g_sr_pd_idle; 142 u32 g_ch_info; 143 u32 g_2t_info; 144 u32 reserved11; 145 u32 reserved12; 146 u32 reserved13; 147 }; 148 149 struct index_info { 150 u8 offset; 151 u8 size; 152 }; 153 154 struct sdram_head_info_index_v2 { 155 u32 start_tag; 156 u32 version_info; 157 struct index_info cpu_gen_index; 158 struct index_info global_index; 159 160 struct index_info ddr2_index; 161 struct index_info ddr3_index; 162 163 struct index_info ddr4_index; 164 struct index_info ddr5_index; 165 166 struct index_info lp2_index; 167 struct index_info lp3_index; 168 169 struct index_info lp4_index; 170 struct index_info lp5_index; 171 172 struct index_info skew_index; 173 struct index_info dq_map_index; 174 175 struct index_info lp4x_index; 176 struct index_info reserved; 177 }; 178 179 struct global_info { 180 u32 uart_info; 181 u32 sr_pd_info; 182 u32 ch_info; 183 u32 info_2t; 184 u32 reserved[4]; 185 }; 186 187 struct ddr2_3_4_lp2_3_info { 188 u32 ddr_freq0_1; 189 u32 ddr_freq2_3; 190 u32 ddr_freq4_5; 191 u32 drv_when_odten; 192 u32 drv_when_odtoff; 193 u32 odt_info; 194 u32 odten_freq; 195 u32 sr_when_odten; 196 u32 sr_when_odtoff; 197 }; 198 199 struct lp4_info { 200 u32 ddr_freq0_1; 201 u32 ddr_freq2_3; 202 u32 ddr_freq4_5; 203 u32 drv_when_odten; 204 u32 drv_when_odtoff; 205 u32 odt_info; 206 u32 dq_odten_freq; 207 u32 sr_when_odten; 208 u32 sr_when_odtoff; 209 u32 ca_odten_freq; 210 u32 cs_drv_ca_odt_info; 211 u32 vref_when_odten; 212 u32 vref_when_odtoff; 213 }; 214 215 struct dq_map_info { 216 u32 byte_map[2]; 217 u32 lp3_dq0_7_map; 218 u32 lp2_dq0_7_map; 219 u32 ddr4_dq_map[4]; 220 }; 221 222 struct sdram_cap_info { 223 unsigned int rank; 224 unsigned int col; 225 /* 3:8bank, 2:4bank */ 226 unsigned int bk; 227 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 228 unsigned int bw; 229 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 230 unsigned int dbw; 231 unsigned int row_3_4; 232 unsigned int cs0_row; 233 unsigned int cs1_row; 234 unsigned int cs2_row; 235 unsigned int cs3_row; 236 unsigned int cs0_high16bit_row; 237 unsigned int cs1_high16bit_row; 238 unsigned int cs2_high16bit_row; 239 unsigned int cs3_high16bit_row; 240 unsigned int ddrconfig; 241 }; 242 243 struct sdram_base_params { 244 unsigned int ddr_freq; 245 unsigned int dramtype; 246 unsigned int num_channels; 247 unsigned int stride; 248 unsigned int odt; 249 }; 250 251 /* store result of read and write training, for ddr_dq_eye tool in u-boot */ 252 #define DDR_DQ_EYE_FLAG 0xdddeefa0 253 254 #define FSP_NUM 4 255 #define CS_NUM 4 256 #define BYTE_NUM 5 257 258 struct dqs_rw_trn_result { 259 u16 dq_deskew[8]; 260 u16 dqs_deskew; 261 u16 dq_min[8]; 262 u16 dq_max[8]; 263 }; 264 265 struct cs_rw_trn_result { 266 struct dqs_rw_trn_result dqs[BYTE_NUM]; 267 }; 268 269 struct fsp_rw_trn_result { 270 u16 min_val; 271 struct cs_rw_trn_result cs[CS_NUM]; 272 }; 273 274 struct rw_trn_result { 275 u32 flag; 276 u8 cs_num; 277 u8 byte_en; 278 u16 fsp_mhz[FSP_NUM]; 279 struct fsp_rw_trn_result rd_fsp[FSP_NUM]; 280 struct fsp_rw_trn_result wr_fsp[FSP_NUM]; 281 }; 282 283 /* for modify tRFC and related timing */ 284 #define DIE_CAP_512MBIT 64 285 #define DIE_CAP_1GBIT 128 286 #define DIE_CAP_2GBIT 256 287 #define DIE_CAP_4GBIT 512 288 #define DIE_CAP_8GBIT 1024 289 #define DIE_CAP_16GBIT 2048 290 #define DIE_CAP_32GBIT 4096 291 292 /* 293 * sys_reg bitfield struct 294 * [31] row_3_4_ch1 295 * [30] row_3_4_ch0 296 * [29:28] chinfo 297 * [27] rank_ch1 298 * [26:25] col_ch1 299 * [24] bk_ch1 300 * [23:22] cs0_row_ch1 301 * [21:20] cs1_row_ch1 302 * [19:18] bw_ch1 303 * [17:16] dbw_ch1; 304 * [15:13] ddrtype 305 * [12] channelnum 306 * [11] rank_ch0 307 * [10:9] col_ch0 308 * [8] bk_ch0 309 * [7:6] cs0_row_ch0 310 * [5:4] cs1_row_ch0 311 * [3:2] bw_ch0 312 * [1:0] dbw_ch0 313 */ 314 315 #define DDR_SYS_REG_VERSION (0x2) 316 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 317 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 318 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 319 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) 320 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 321 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 322 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 323 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 324 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) 325 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1)) 326 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) 327 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3)) 328 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ 329 (8 + ((ch) * 16))) 330 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1)) 331 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) 332 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3)) 333 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) 334 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3)) 335 /* sys reg 3 */ 336 #define SYS_REG_ENC_VERSION(n) ((n) << 28) 337 #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf) 338 #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ 339 (os_reg2) &= (~(0x3 << (6 + 16 * (ch)))); \ 340 (os_reg3) &= (~(0x1 << (5 + 2 * (ch)))); \ 341 (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ 342 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 343 (5 + 2 * (ch)); \ 344 } while (0) 345 346 #define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \ 347 ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \ 348 ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 349 350 #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ 351 (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ 352 (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ 353 (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ 354 (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ 355 (4 + 2 * (ch)); \ 356 } while (0) 357 358 #define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \ 359 ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \ 360 ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12) 361 362 #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch))) 363 #define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3)) 364 365 /* DDR SYS REG Version 3 */ 366 #define DDR_SYS_REG_VERSION_3 (0x3) 367 #define SYS_REG_ENC_ROW_3_4_V3(row3_4, ch) SYS_REG_ENC_ROW_3_4(row3_4, ch) 368 #define SYS_REG_DEC_ROW_3_4_V3(reg2, ch) SYS_REG_DEC_ROW_3_4(reg2, ch) 369 #define SYS_REG_ENC_CHINFO_V3(ch) SYS_REG_ENC_CHINFO(ch) 370 #define SYS_REG_DEC_CHINFO_V3(reg2, ch) SYS_REG_DEC_CHINFO(reg2, ch) 371 #define SYS_REG_ENC_DDRTYPE_V3(n, reg2, reg3) do { \ 372 (reg2) &= (~(0x7 << 13)); \ 373 (reg3) &= (~(0x3 << 12)); \ 374 (reg2) |= (((n) & 0x7) << 13); \ 375 (reg3) |= (((n) >> 3) & 0x3) << 12; \ 376 } while (0) 377 #define SYS_REG_DEC_DDRTYPE_V3(reg2, reg3) \ 378 ((((reg2) >> 13) & 0x7) | \ 379 ((((reg3) >> 12) & 0x3) << 3)) 380 381 #define SYS_REG_ENC_NUM_CH_V3(n) SYS_REG_ENC_NUM_CH(n) 382 #define SYS_REG_DEC_NUM_CH_V3(reg2) SYS_REG_DEC_NUM_CH(reg2) 383 #define SYS_REG_ENC_CH1_3_RANK(cs) SYS_REG_ENC_RANK(cs, 1) 384 #define SYS_REG_DEC_CH1_3_RANK(reg2) SYS_REG_DEC_RANK(reg2, 1) 385 #define SYS_REG_ENC_CH0_2_RANK_V3(n, reg2, reg3) do { \ 386 (reg2) &= (~(1 << 11)); \ 387 (reg3) &= (~(1 << 14)); \ 388 (reg2) |= (((n) == 2) ? 1 : 0) << 11; \ 389 (reg3) |= (((n) == 4) ? 1 : 0) << 14; \ 390 } while (0) 391 #define SYS_REG_DEC_CH0_2_RANK_V3(reg2, reg3) \ 392 (1 << ((((reg2) >> 11) & 1) | ((((reg3) >> 14) & 1) << 1))) 393 #define SYS_REG_ENC_COL_V3(col, ch) SYS_REG_ENC_COL(col, ch) 394 #define SYS_REG_DEC_COL_V3(reg2, ch) SYS_REG_DEC_COL(reg2, ch) 395 #define SYS_REG_ENC_BK_V3(bk, ch) SYS_REG_ENC_BK(bk, ch) 396 #define SYS_REG_DEC_BK_V3(reg2, ch) SYS_REG_DEC_BK(reg2, ch) 397 #define SYS_REG_ENC_BW_V3(bw, ch) SYS_REG_ENC_BW(bw, ch) 398 #define SYS_REG_DEC_BW_V3(reg2, ch) SYS_REG_DEC_BW(reg2, ch) 399 #define SYS_REG_ENC_DBW_V3(dbw, ch) SYS_REG_ENC_DBW(dbw, ch) 400 #define SYS_REG_DEC_DBW_V3(reg2, ch) SYS_REG_DEC_DBW(reg2, ch) 401 #define SYS_REG_ENC_VERSION_V3(n) SYS_REG_ENC_VERSION(n) 402 #define SYS_REG_DEC_VERSION_V3(reg3) SYS_REG_DEC_VERSION(reg3) 403 #define SYS_REG_ENC_CS0_ROW_V3(row, reg2, reg3, ch) \ 404 SYS_REG_ENC_CS0_ROW(row, reg2, reg3, ch) 405 #define SYS_REG_DEC_CS0_ROW_V3(reg2, reg3, ch) \ 406 SYS_REG_DEC_CS0_ROW(reg2, reg3, ch) 407 #define SYS_REG_ENC_CS1_ROW_V3(row, reg2, reg3, ch) \ 408 SYS_REG_ENC_CS1_ROW(row, reg2, reg3, ch) 409 #define SYS_REG_DEC_CS1_ROW_V3(reg2, reg3, ch) \ 410 SYS_REG_DEC_CS1_ROW(reg2, reg3, ch) 411 #define SYS_REG_ENC_CS2_DELTA_ROW_V3(row_del) ((row_del) << 15) 412 #define SYS_REG_DEC_CS2_DELTA_ROW_V3(reg3) (((reg3) >> 15) & 1) 413 #define SYS_REG_ENC_CS3_DELTA_ROW_V3(row_del) ((row_del) << 16) 414 #define SYS_REG_DEC_CS3_DELTA_ROW_V3(reg3) (((reg3) >> 16) & 1) 415 416 #define SYS_REG_ENC_CS1_COL_V3(col, ch) SYS_REG_ENC_CS1_COL(col, ch) 417 #define SYS_REG_DEC_CS1_COL_V3(reg3, ch) SYS_REG_DEC_CS1_COL(reg3, ch) 418 419 void sdram_org_config(struct sdram_cap_info *cap_info, 420 struct sdram_base_params *base, 421 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); 422 void sdram_org_config_v3(struct sdram_cap_info *cap_info, 423 struct sdram_base_params *base, 424 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel); 425 int sdram_detect_bw(struct sdram_cap_info *cap_info); 426 int sdram_detect_cs(struct sdram_cap_info *cap_info); 427 int sdram_detect_col(struct sdram_cap_info *cap_info, 428 u32 coltmp); 429 int sdram_detect_bank(struct sdram_cap_info *cap_info, 430 u32 coltmp, u32 bktmp); 431 int sdram_detect_bg(struct sdram_cap_info *cap_info, 432 u32 coltmp); 433 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type); 434 int sdram_detect_row(struct sdram_cap_info *cap_info, 435 u32 coltmp, u32 bktmp, u32 rowtmp); 436 int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, 437 u32 coltmp, u32 bktmp); 438 int sdram_detect_high_row(struct sdram_cap_info *cap_info, u32 dramtype); 439 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type); 440 441 void sdram_print_dram_type(unsigned char dramtype); 442 void sdram_print_ddr_info(struct sdram_cap_info *cap_info, 443 struct sdram_base_params *base, u32 split); 444 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type); 445 void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n); 446 447 #endif 448