1 /* 2 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_SDRAM_H 8 #define _ASM_ARCH_SDRAM_H 9 10 enum { 11 DDR4 = 0, 12 DDR2 = 2, 13 DDR3 = 3, 14 LPDDR2 = 5, 15 LPDDR3 = 6, 16 LPDDR4 = 7, 17 LPDDR4X = 8, 18 LPDDR5 = 9, 19 DDR5 = 10, 20 UNUSED = 0xFF 21 }; 22 23 struct ddr_param { 24 u32 count; 25 u32 reserved; 26 u64 para[8]; 27 }; 28 29 /* 30 * sys_reg bitfield struct 31 * [31] row_3_4_ch1 32 * [30] row_3_4_ch0 33 * [29:28] chinfo 34 * [27] rank_ch1 35 * [26:25] col_ch1 36 * [24] bk_ch1 37 * [23:22] low bits of cs0_row_ch1 38 * [21:20] low bits of cs1_row_ch1 39 * [19:18] bw_ch1 40 * [17:16] dbw_ch1; 41 * [15:13] ddrtype 42 * [12] channelnum 43 * [11] rank_ch0 44 * [10:9] col_ch0, 45 * [8] bk_ch0 46 * [7:6] low bits of cs0_row_ch0 47 * [5:4] low bits of cs1_row_ch0 48 * [3:2] bw_ch0 49 * [1:0] dbw_ch0 50 * 51 * sys_reg1 bitfield struct 52 * [7] high bit of cs0_row_ch1 53 * [6] high bit of cs1_row_ch1 54 * [5] high bit of cs0_row_ch0 55 * [4] high bit of cs1_row_ch0 56 * [3:2] cs1_col_ch1 57 * [1:0] cs1_col_ch0 58 */ 59 #define SYS_REG_DDRTYPE_SHIFT 13 60 #define SYS_REG_DDRTYPE_MASK 7 61 #define SYS_REG_NUM_CH_SHIFT 12 62 #define SYS_REG_NUM_CH_MASK 1 63 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) 64 #define SYS_REG_ROW_3_4_MASK 1 65 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) 66 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) 67 #define SYS_REG_RANK_MASK 1 68 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) 69 #define SYS_REG_COL_MASK 3 70 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) 71 #define SYS_REG_BK_MASK 1 72 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) 73 #define SYS_REG_CS0_ROW_MASK 3 74 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) 75 #define SYS_REG_CS1_ROW_MASK 3 76 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) 77 #define SYS_REG_BW_MASK 3 78 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) 79 #define SYS_REG_DBW_MASK 3 80 81 #define SYS_REG1_VERSION_SHIFT 28 82 #define SYS_REG1_VERSION_MASK 0xf 83 #define SYS_REG1_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) 84 #define SYS_REG1_EXTEND_CS0_ROW_MASK 1 85 #define SYS_REG1_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2) 86 #define SYS_REG1_EXTEND_CS1_ROW_MASK 1 87 #define SYS_REG1_CS1_COL_SHIFT(ch) (0 + (ch) * 2) 88 #define SYS_REG1_CS1_COL_MASK 3 89 90 /* Get sdram size decode from reg */ 91 size_t rockchip_sdram_size(phys_addr_t reg); 92 unsigned int get_page_size(void); 93 unsigned int get_ddr_bw(void); 94 95 /* Called by U-Boot board_init_r for Rockchip SoCs */ 96 int dram_init(void); 97 98 /* Write ddr param to a known place for trustos */ 99 int rockchip_setup_ddr_param(struct ddr_param *info); 100 101 #endif 102