1 /* 2 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3 * Author: Zhihuan He <huan.he@rock-chips.com> 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARCH_GRF_RV1108_H 8 #define _ASM_ARCH_GRF_RV1108_H 9 10 #include <common.h> 11 12 struct rv1108_grf { 13 u32 reserved[4]; 14 u32 gpio1a_iomux; 15 u32 gpio1b_iomux; 16 u32 gpio1c_iomux; 17 u32 gpio1d_iomux; 18 u32 gpio2a_iomux; 19 u32 gpio2b_iomux; 20 u32 gpio2c_iomux; 21 u32 gpio2d_iomux; 22 u32 gpio3a_iomux; 23 u32 gpio3b_iomux; 24 u32 gpio3c_iomux; 25 u32 gpio3d_iomux; 26 u32 reserved1[52]; 27 u32 gpio1a_pull; 28 u32 gpio1b_pull; 29 u32 gpio1c_pull; 30 u32 gpio1d_pull; 31 u32 gpio2a_pull; 32 u32 gpio2b_pull; 33 u32 gpio2c_pull; 34 u32 gpio2d_pull; 35 u32 gpio3a_pull; 36 u32 gpio3b_pull; 37 u32 gpio3c_pull; 38 u32 gpio3d_pull; 39 u32 reserved2[52]; 40 u32 gpio1a_drv; 41 u32 gpio1b_drv; 42 u32 gpio1c_drv; 43 u32 gpio1d_drv; 44 u32 gpio2a_drv; 45 u32 gpio2b_drv; 46 u32 gpio2c_drv; 47 u32 gpio2d_drv; 48 u32 gpio3a_drv; 49 u32 gpio3b_drv; 50 u32 gpio3c_drv; 51 u32 gpio3d_drv; 52 u32 reserved3[50]; 53 u32 gpio1l_sr; 54 u32 gpio1h_sr; 55 u32 gpio2l_sr; 56 u32 gpio2h_sr; 57 u32 gpio3l_sr; 58 u32 gpio3h_sr; 59 u32 reserved4[26]; 60 u32 gpio1l_smt; 61 u32 gpio1h_smt; 62 u32 gpio2l_smt; 63 u32 gpio2h_smt; 64 u32 gpio3l_smt; 65 u32 gpio3h_smt; 66 u32 reserved5[24]; 67 u32 soc_con0; 68 u32 soc_con1; 69 u32 soc_con2; 70 u32 soc_con3; 71 u32 soc_con4; 72 u32 soc_con5; 73 u32 soc_con6; 74 u32 soc_con7; 75 u32 soc_con8; 76 u32 soc_con9; 77 u32 soc_con10; 78 u32 soc_con11; 79 u32 reserved6[20]; 80 u32 soc_status0; 81 u32 soc_status1; 82 u32 reserved7[30]; 83 u32 cpu_con0; 84 u32 cpu_con1; 85 u32 reserved8[30]; 86 u32 os_reg0; 87 u32 os_reg1; 88 u32 os_reg2; 89 u32 os_reg3; 90 u32 reserved9[29]; 91 u32 ddr_status; 92 u32 reserved10[30]; 93 u32 sig_det_con; 94 u32 reserved11[3]; 95 u32 sig_det_status; 96 u32 reserved12[3]; 97 u32 sig_det_clr; 98 u32 reserved13[23]; 99 u32 host_con0; 100 u32 host_con1; 101 u32 reserved14[2]; 102 u32 dma_con0; 103 u32 dma_con1; 104 u32 reserved15[59]; 105 u32 uoc_status; 106 u32 reserved16[2]; 107 u32 host_status; 108 u32 reserved17[59]; 109 u32 gmac_con0; 110 u32 reserved18[191]; 111 u32 chip_id; 112 }; 113 114 check_member(rv1108_grf, chip_id, 0x0c00); 115 116 struct rv1108_pmu_grf { 117 u32 gpioa_iomux; 118 u32 gpiob_iomux; 119 u32 gpioc_iomux; 120 u32 reserved1; 121 u32 gpioa_p; 122 u32 gpiob_p; 123 u32 gpioc_p; 124 u32 reserved2; 125 u32 gpioa_e; 126 u32 gpiob_e; 127 u32 gpioc_e; 128 u32 reserved3; 129 u32 gpioa_smt; 130 u32 gpiob_smt; 131 u32 gpioc_smt; 132 u32 reserved4; 133 u32 gpio0a_sr; 134 u32 gpio0b_sr; 135 u32 gpio0c_sr; 136 u32 reserved5[(0x100-0x4c)/4]; 137 u32 soc_con[4]; 138 u32 reserved6[(0x180-0x110)/4]; 139 u32 dll_con[2]; 140 u32 reserved7[2]; 141 u32 dll_status[2]; 142 u32 reserved8[(0x200-0x198)/4]; 143 u32 os_reg[4]; 144 u32 reserved9[(0x300-0x210)/4]; 145 u32 fast_boot_addr; 146 u32 reserved10[(0x380-0x304)/4]; 147 u32 a7_jtag_mask; 148 u32 reserved11[(0x388-0x384)/4]; 149 u32 ceva_jtag_mask; 150 }; 151 check_member(rv1108_pmu_grf, ceva_jtag_mask, 0x388); 152 153 enum { 154 /* GRF_SOC_CON0 */ 155 MSCH_MAINDDR3_SHIFT = 4, 156 MSCH_MAINDDR3 = 1 << MSCH_MAINDDR3_SHIFT, 157 MSCH_MAINPARTIALPOP_SHIFT = 5, 158 MSCH_MAINPARTIALPOP = 1 << MSCH_MAINPARTIALPOP_SHIFT, 159 MSCH_MAINPARTIALPOP_MASK = 1 << MSCH_MAINPARTIALPOP_SHIFT, 160 }; 161 162 enum { 163 /* PMU_GRF_SOC_CON0 */ 164 DDRPHY_BUFFEREN_CORE_SHIFT = 2, 165 DDRPHY_BUFFEREN_CORE_MASK = 1 << DDRPHY_BUFFEREN_CORE_SHIFT, 166 DDRPHY_BUFFEREN_CORE_EN = 1 << DDRPHY_BUFFEREN_CORE_SHIFT, 167 }; 168 #endif 169