1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1106_H 8 #define _ASM_ARCH_CRU_RV1106_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 16 #ifdef CONFIG_SPL_KERNEL_BOOT 17 #define APLL_HZ (1104 * MHz) 18 #else 19 #define APLL_HZ (816 * MHz) 20 #endif 21 #define GPLL_HZ (1188 * MHz) 22 #define CPLL_HZ (1000 * MHz) 23 24 /* RV1106 pll id */ 25 enum rv1106_pll_id { 26 APLL, 27 DPLL, 28 CPLL, 29 GPLL, 30 PLL_COUNT, 31 }; 32 33 struct rv1106_clk_info { 34 unsigned long id; 35 char *name; 36 bool is_cru; 37 }; 38 39 struct rv1106_clk_priv { 40 struct rv1106_cru *cru; 41 struct rv1106_grf *grf; 42 ulong gpll_hz; 43 ulong cpll_hz; 44 ulong armclk_hz; 45 ulong armclk_enter_hz; 46 ulong armclk_init_hz; 47 bool sync_kernel; 48 bool set_armclk_rate; 49 }; 50 51 struct rv1106_grf_clk_priv { 52 struct rv1106_grf *grf; 53 }; 54 55 struct rv1106_pll { 56 unsigned int con0; 57 unsigned int con1; 58 unsigned int con2; 59 unsigned int con3; 60 unsigned int con4; 61 unsigned int reserved0[3]; 62 }; 63 64 struct rv1106_cru { 65 unsigned int reserved0[192]; 66 unsigned int pmu_clksel_con[8]; 67 unsigned int reserved1[312]; 68 unsigned int pmu_clkgate_con[3]; 69 unsigned int reserved2[125]; 70 unsigned int pmu_softrst_con[3]; 71 unsigned int reserved3[15741]; 72 struct rv1106_pll pll[4]; 73 unsigned int reserved4[128]; 74 unsigned int mode; 75 unsigned int reserved5[31]; 76 unsigned int clksel_con[34]; 77 unsigned int reserved6[286]; 78 unsigned int clkgate_con[4]; 79 unsigned int reserved7[124]; 80 unsigned int softrst_con[3]; 81 unsigned int reserved8[125]; 82 unsigned int glb_cnt_th; 83 unsigned int glb_rst_st; 84 unsigned int glb_srst_fst; 85 unsigned int glb_srst_snd; 86 unsigned int glb_rst_con; 87 unsigned int con[2]; 88 unsigned int sdmmc_con[2]; 89 unsigned int emmc_con[2]; 90 unsigned int reserved9[1461]; 91 unsigned int peri_clksel_con[12]; 92 unsigned int reserved10[308]; 93 unsigned int peri_clkgate_con[8]; 94 unsigned int reserved11[120]; 95 unsigned int peri_softrst_con[8]; 96 unsigned int reserved12[1592]; 97 unsigned int vi_clksel_con[4]; 98 unsigned int reserved13[316]; 99 unsigned int vi_clkgate_con[3]; 100 unsigned int reserved14[125]; 101 unsigned int vi_softrst_con[3]; 102 unsigned int reserved15[3645]; 103 unsigned int core_clksel_con[5]; 104 unsigned int reserved16[2043]; 105 unsigned int vepu_clksel_con[2]; 106 unsigned int reserved17[318]; 107 unsigned int vepu_clkgate_con[3]; 108 unsigned int reserved18[125]; 109 unsigned int vepu_softrst_con[2]; 110 unsigned int reserved19[1598]; 111 unsigned int vo_clksel_con[4]; 112 unsigned int reserved20[316]; 113 unsigned int vo_clkgate_con[3]; 114 unsigned int reserved21[125]; 115 unsigned int vo_softrst_con[4]; 116 }; 117 check_member(rv1106_cru, vo_softrst_con[0], 0x1ca00); 118 119 struct pll_rate_table { 120 unsigned long rate; 121 unsigned int fbdiv; 122 unsigned int postdiv1; 123 unsigned int refdiv; 124 unsigned int postdiv2; 125 unsigned int dsmpd; 126 unsigned int frac; 127 }; 128 129 #define RV1106_TOPCRU_BASE 0x10000 130 #define RV1106_SUBDDRCRU_BASE 0x1F000 131 132 #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE) 133 #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE) 134 #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE) 135 136 enum { 137 /* CRU_PMU_CLK_SEL0_CON */ 138 CLK_I2C1_SEL_SHIFT = 6, 139 CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, 140 CLK_I2C1_SEL_200M = 0, 141 CLK_I2C1_SEL_100M, 142 CLK_I2C1_SEL_24M, 143 CLK_I2C1_SEL_32K, 144 HCLK_PMU_SEL_SHIFT = 4, 145 HCLK_PMU_SEL_MASK = 0x3 << HCLK_PMU_SEL_SHIFT, 146 HCLK_PMU_SEL_200M = 0, 147 HCLK_PMU_SEL_100M, 148 HCLK_PMU_SEL_24M, 149 PCLK_PMU_SEL_SHIFT = 3, 150 PCLK_PMU_SEL_MASK = 0x1 << PCLK_PMU_SEL_SHIFT, 151 PCLK_PMU_SEL_100M = 0, 152 PCLK_PMU_SEL_24M, 153 154 /* CRU_CLK_SEL5_CON */ 155 CLK_UART_SRC_SEL_SHIFT = 5, 156 CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT, 157 CLK_UART_SRC_SEL_GPLL = 0, 158 CLK_UART_SRC_SEL_CPLL, 159 CLK_UART_SRC_DIV_SHIFT = 0, 160 CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT, 161 162 /* CRU_CLK_SEL6_CON */ 163 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 164 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 165 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 166 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 167 168 /* CRU_CLK_SEL7_CON */ 169 CLK_UART_SEL_SHIFT = 0, 170 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 171 CLK_UART_SEL_SRC = 0, 172 CLK_UART_SEL_FRAC, 173 CLK_UART_SEL_XIN24M, 174 175 /* CRU_CLK_SEL23_CON */ 176 DCLK_VOP_SEL_SHIFT = 8, 177 DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT, 178 DCLK_VOP_SEL_GPLL = 0, 179 DCLK_VOP_SEL_CPLL, 180 DCLK_VOP_DIV_SHIFT = 3, 181 DCLK_VOP_DIV_MASK = 0x1f << DCLK_VOP_DIV_SHIFT, 182 183 /* CRU_CLK_SEL24_CON */ 184 PCLK_TOP_SEL_SHIFT = 5, 185 PCLK_TOP_SEL_MASK = 0x3 << PCLK_TOP_SEL_SHIFT, 186 PCLK_TOP_SEL_100M = 0, 187 PCLK_TOP_SEL_50M, 188 PCLK_TOP_SEL_24M, 189 190 /* CRU_PERI_CLK_SEL1_CON */ 191 CLK_I2C3_SEL_SHIFT = 14, 192 CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, 193 CLK_I2C2_SEL_SHIFT = 12, 194 CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 195 CLK_I2C0_SEL_SHIFT = 8, 196 CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, 197 CLK_I2C0_SEL_200M = 0, 198 CLK_I2C0_SEL_100M, 199 CLK_I2C0_SEL_50M, 200 CLK_I2C0_SEL_24M, 201 HCLK_PERI_SEL_SHIFT = 4, 202 HCLK_PERI_SEL_MASK = 0x3 << HCLK_PERI_SEL_SHIFT, 203 HCLK_PERI_SEL_200M = 0, 204 HCLK_PERI_SEL_100M, 205 HCLK_PERI_SEL_50M, 206 HCLK_PERI_SEL_24M, 207 ACLK_PERI_SEL_SHIFT = 2, 208 ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT, 209 ACLK_PERI_SEL_400M = 0, 210 ACLK_PERI_SEL_200M, 211 ACLK_PERI_SEL_100M, 212 ACLK_PERI_SEL_24M, 213 PCLK_PERI_SEL_SHIFT = 0, 214 PCLK_PERI_SEL_MASK = 0x3 << PCLK_PERI_SEL_SHIFT, 215 PCLK_PERI_SEL_100M = 0, 216 PCLK_PERI_SEL_50M, 217 PCLK_PERI_SEL_24M, 218 219 /* CRU_PERI_CLK_SEL2_CON */ 220 CLK_I2C4_SEL_SHIFT = 0, 221 CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, 222 223 /* CRU_PERI_CLK_SEL6_CON */ 224 CLK_PWM2_SEL_SHIFT = 11, 225 CLK_PWM2_SEL_MASK = 0x3 << CLK_PWM2_SEL_SHIFT, 226 CLK_PWM1_SEL_SHIFT = 9, 227 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 228 CLK_PWM_SEL_100M = 0, 229 CLK_PWM_SEL_50M, 230 CLK_PWM_SEL_24M, 231 CLK_PKA_CRYPTO_SEL_SHIFT = 7, 232 CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 233 CLK_CORE_CRYPTO_SEL_SHIFT = 5, 234 CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 235 CLK_CRYPTO_SEL_300M = 0, 236 CLK_CRYPTO_SEL_200M, 237 CLK_CRYPTO_SEL_100M, 238 CLK_CRYPTO_SEL_24M, 239 CLK_SARADC_DIV_SHIFT = 0, 240 CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 241 CLK_SPI1_SEL_SHIFT = 3, 242 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 243 244 /* CRU_PERI_CLK_SEL7_CON */ 245 DCLK_DECOM_SEL_SHIFT = 14, 246 DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT, 247 DCLK_DECOM_SEL_400M = 0, 248 DCLK_DECOM_SEL_200M, 249 DCLK_DECOM_SEL_100M, 250 DCLK_DECOM_SEL_24M, 251 CLK_SFC_SEL_SHIFT = 12, 252 CLK_SFC_SEL_MASK = 0x3 << CLK_SFC_SEL_SHIFT, 253 CLK_SFC_SEL_500M = 0, 254 CLK_SFC_SEL_300M, 255 CLK_SFC_SEL_200M, 256 CLK_SFC_SEL_24M, 257 CLK_SFC_DIV_SHIFT = 7, 258 CLK_SFC_DIV_MASK = 0x1f << CLK_SFC_DIV_SHIFT, 259 CLK_EMMC_SEL_SHIFT = 6, 260 CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT, 261 CLK_MMC_SEL_400M = 0, 262 CLK_MMC_SEL_24M, 263 CLK_EMMC_DIV_SHIFT = 0, 264 CLK_EMMC_DIV_MASK = 0x3f << CLK_EMMC_DIV_SHIFT, 265 266 /* CRU_PERI_CLK_SEL9_CON */ 267 ACLK_BUS_SEL_SHIFT = 0, 268 ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, 269 ACLK_BUS_SEL_300M = 0, 270 ACLK_BUS_SEL_200M, 271 ACLK_BUS_SEL_100M, 272 ACLK_BUS_SEL_24M, 273 274 /* CRU_PERI_CLK_SEL11_CON */ 275 CLK_PWM0_SEL_SHIFT = 0, 276 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, 277 278 /* CRU_VEPU_CLK_SEL0_CON */ 279 CLK_SPI0_SEL_SHIFT = 12, 280 CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 281 CLK_SPI0_SEL_200M = 0, 282 CLK_SPI0_SEL_100M, 283 CLK_SPI0_SEL_50M, 284 CLK_SPI0_SEL_24M, 285 286 /* CRU_CORE_CLK_SEL0_CON */ 287 CLK_CORE_DIV_SHIFT = 0, 288 CLK_CORE_DIV_MASK = 0x1f << CLK_CORE_DIV_SHIFT, 289 290 /* CRU_VI_CLK_SEL1_CON */ 291 CLK_SDMMC_SEL_SHIFT = 14, 292 CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT, 293 CLK_SDMMC_DIV_SHIFT = 8, 294 CLK_SDMMC_DIV_MASK = 0x3f << CLK_SDMMC_DIV_SHIFT, 295 296 /* CRU_VO_CLK_SEL1_CON */ 297 ACLK_VOP_SEL_SHIFT = 10, 298 ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT, 299 ACLK_VOP_SEL_300M = 0, 300 ACLK_VOP_SEL_200M, 301 ACLK_VOP_SEL_100M, 302 ACLK_VOP_SEL_24M, 303 304 /* CRU_VO_CLK_SEL3_CON */ 305 CLK_TSADC_TSEN_DIV_SHIFT = 5, 306 CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, 307 CLK_TSADC_DIV_SHIFT = 0, 308 CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, 309 }; 310 #endif 311