1 /*
2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <bl1/bl1.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <lib/fconf/fconf.h>
16 #include <lib/fconf/fconf_dyn_cfg_getter.h>
17 #if TRANSFER_LIST
18 #include <transfer_list.h>
19 #endif
20 #include <lib/utils.h>
21 #include <lib/xlat_tables/xlat_tables_compat.h>
22 #include <plat/arm/common/plat_arm.h>
23 #include <plat/common/platform.h>
24
25 /* Weak definitions may be overridden in specific ARM standard platform */
26 #pragma weak bl1_early_platform_setup
27 #pragma weak bl1_plat_arch_setup
28 #pragma weak bl1_plat_sec_mem_layout
29 #pragma weak arm_bl1_early_platform_setup
30 #pragma weak bl1_plat_prepare_exit
31 #pragma weak bl1_plat_get_next_image_id
32 #pragma weak plat_arm_bl1_fwu_needed
33 #pragma weak arm_bl1_plat_arch_setup
34 #pragma weak arm_bl1_platform_setup
35
36 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \
37 bl1_tzram_layout.total_base, \
38 bl1_tzram_layout.total_size, \
39 MT_MEMORY | MT_RW | EL3_PAS)
40 /*
41 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
42 * otherwise one region is defined containing both
43 */
44 #if SEPARATE_CODE_AND_RODATA
45 #define MAP_BL1_RO MAP_REGION_FLAT( \
46 BL_CODE_BASE, \
47 BL1_CODE_END - BL_CODE_BASE, \
48 MT_CODE | EL3_PAS), \
49 MAP_REGION_FLAT( \
50 BL1_RO_DATA_BASE, \
51 BL1_RO_DATA_END \
52 - BL_RO_DATA_BASE, \
53 MT_RO_DATA | EL3_PAS)
54 #else
55 #define MAP_BL1_RO MAP_REGION_FLAT( \
56 BL_CODE_BASE, \
57 BL1_CODE_END - BL_CODE_BASE, \
58 MT_CODE | EL3_PAS)
59 #endif
60
61 /* Data structure which holds the extents of the trusted SRAM for BL1*/
62 static meminfo_t bl1_tzram_layout;
63
64 /* Boolean variable to hold condition whether firmware update needed or not */
65 static bool is_fwu_needed;
66
67 struct transfer_list_header *secure_tl;
68
bl1_plat_sec_mem_layout(void)69 struct meminfo *bl1_plat_sec_mem_layout(void)
70 {
71 return &bl1_tzram_layout;
72 }
73
74 /*******************************************************************************
75 * BL1 specific platform actions shared between ARM standard platforms.
76 ******************************************************************************/
arm_bl1_early_platform_setup(void)77 void arm_bl1_early_platform_setup(void)
78 {
79
80 #if !ARM_DISABLE_TRUSTED_WDOG
81 /* Enable watchdog */
82 plat_arm_secure_wdt_start();
83 #endif
84
85 /* Initialize the console to provide early debug support */
86 arm_console_boot_init();
87
88 /* Allow BL1 to see the whole Trusted RAM */
89 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
90 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
91
92 #if TRANSFER_LIST
93 secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
94 PLAT_ARM_FW_HANDOFF_SIZE);
95 assert(secure_tl != NULL);
96 #endif
97 }
98
bl1_early_platform_setup(void)99 void bl1_early_platform_setup(void)
100 {
101 arm_bl1_early_platform_setup();
102 #if !HW_ASSISTED_COHERENCY
103 /*
104 * Initialize Interconnect for this cluster during cold boot.
105 * No need for locks as no other CPU is active.
106 */
107 plat_arm_interconnect_init();
108 /*
109 * Enable Interconnect coherency for the primary CPU's cluster.
110 */
111 plat_arm_interconnect_enter_coherency();
112 #endif
113 }
114
115 /******************************************************************************
116 * Perform the very early platform specific architecture setup shared between
117 * ARM standard platforms. This only does basic initialization. Later
118 * architectural setup (bl1_arch_setup()) does not do anything platform
119 * specific.
120 *****************************************************************************/
arm_bl1_plat_arch_setup(void)121 void arm_bl1_plat_arch_setup(void)
122 {
123 #if USE_COHERENT_MEM
124 /* Ensure ARM platforms don't use coherent memory in BL1. */
125 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
126 #endif
127
128 const mmap_region_t bl_regions[] = {
129 MAP_BL1_TOTAL,
130 MAP_BL1_RO,
131 #if USE_ROMLIB
132 ARM_MAP_ROMLIB_CODE,
133 ARM_MAP_ROMLIB_DATA,
134 #endif
135 {0}
136 };
137
138 setup_page_tables(bl_regions, plat_arm_get_mmap());
139 #ifdef __aarch64__
140 enable_mmu_el3(0);
141 #else
142 enable_mmu_svc_mon(0);
143 #endif /* __aarch64__ */
144
145 arm_setup_romlib();
146 }
147
bl1_plat_arch_setup(void)148 void bl1_plat_arch_setup(void)
149 {
150 arm_bl1_plat_arch_setup();
151 }
152
153 /*
154 * Perform the platform specific architecture setup shared between
155 * ARM standard platforms.
156 */
arm_bl1_platform_setup(void)157 void arm_bl1_platform_setup(void)
158 {
159 const struct dyn_cfg_dtb_info_t *config_info __unused;
160 uint32_t fw_config_max_size __unused;
161 image_info_t config_image_info __unused;
162 struct transfer_list_entry *te __unused;
163
164 image_desc_t *desc;
165
166 int err __unused = 1;
167
168 /* Initialise the IO layer and register platform IO devices */
169 plat_arm_io_setup();
170
171 /* Check if we need FWU before further processing */
172 is_fwu_needed = plat_arm_bl1_fwu_needed();
173 if (is_fwu_needed) {
174 ERROR("Skip platform setup as FWU detected\n");
175 return;
176 }
177
178 #if TRANSFER_LIST
179 #if CRYPTO_SUPPORT
180 te = transfer_list_add(secure_tl, TL_TAG_MBEDTLS_HEAP_INFO,
181 sizeof(struct crypto_heap_info), NULL);
182 assert(te != NULL);
183
184 struct crypto_heap_info *heap_info =
185 (struct crypto_heap_info *)transfer_list_entry_data(te);
186 arm_get_mbedtls_heap(&heap_info->addr, &heap_info->size);
187 #endif /* CRYPTO_SUPPORT */
188
189 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
190
191 /*
192 * The event log might have been updated prior to this, make sure we have an
193 * up to date tl before setting the handoff arguments.
194 */
195 transfer_list_update_checksum(secure_tl);
196 transfer_list_set_handoff_args(secure_tl, &desc->ep_info);
197 #else
198 /* Set global DTB info for fixed fw_config information */
199 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
200 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
201
202 /* Fill the device tree information struct with the info from the config dtb */
203 err = fconf_load_config(FW_CONFIG_ID);
204 if (err < 0) {
205 ERROR("Loading of FW_CONFIG failed %d\n", err);
206 plat_error_handler(err);
207 }
208
209 /*
210 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
211 * is successful then load TB_FW_CONFIG device tree.
212 */
213 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
214 if (config_info != NULL) {
215 err = fconf_populate_dtb_registry(config_info->config_addr);
216 if (err < 0) {
217 ERROR("Parsing of FW_CONFIG failed %d\n", err);
218 plat_error_handler(err);
219 }
220
221 /* load TB_FW_CONFIG */
222 err = fconf_load_config(TB_FW_CONFIG_ID);
223 if (err < 0) {
224 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
225 plat_error_handler(err);
226 }
227 } else {
228 ERROR("Invalid FW_CONFIG address\n");
229 plat_error_handler(err);
230 }
231
232 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
233
234 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
235 assert(desc != NULL);
236 desc->ep_info.args.arg0 = config_info->config_addr;
237
238 #if CRYPTO_SUPPORT
239 /* Share the Mbed TLS heap info with other images */
240 arm_bl1_set_mbedtls_heap();
241 #endif /* CRYPTO_SUPPORT */
242 #endif /* TRANSFER_LIST */
243
244 /*
245 * Allow access to the System counter timer module and program
246 * counter frequency for non secure images during FWU
247 */
248 #ifdef ARM_SYS_TIMCTL_BASE
249 arm_configure_sys_timer();
250 #endif
251 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
252 write_cntfrq_el0(plat_get_syscnt_freq2());
253 #endif
254 }
255
bl1_plat_prepare_exit(entry_point_info_t * ep_info)256 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
257 {
258 #if !ARM_DISABLE_TRUSTED_WDOG
259 /* Disable watchdog before leaving BL1 */
260 plat_arm_secure_wdt_stop();
261 #endif
262
263 #ifdef EL3_PAYLOAD_BASE
264 /*
265 * Program the EL3 payload's entry point address into the CPUs mailbox
266 * in order to release secondary CPUs from their holding pen and make
267 * them jump there.
268 */
269 plat_arm_program_trusted_mailbox(ep_info->pc);
270 dsbsy();
271 sev();
272 #endif
273 }
274
275 /*
276 * On Arm platforms, the FWU process is triggered when the FIP image has
277 * been tampered with.
278 */
plat_arm_bl1_fwu_needed(void)279 bool plat_arm_bl1_fwu_needed(void)
280 {
281 return !arm_io_is_toc_valid();
282 }
283
284 /*******************************************************************************
285 * The following function checks if Firmware update is needed,
286 * by checking if TOC in FIP image is valid or not.
287 ******************************************************************************/
bl1_plat_get_next_image_id(void)288 unsigned int bl1_plat_get_next_image_id(void)
289 {
290 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
291 }
292
293 #if TRANSFER_LIST
bl1_plat_handle_post_image_load(unsigned int image_id)294 int bl1_plat_handle_post_image_load(unsigned int image_id)
295 {
296 struct transfer_list_entry *te;
297
298 if (image_id != BL2_IMAGE_ID) {
299 return 0;
300 }
301
302 /* Convey this information to BL2 via its TL. */
303 te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT,
304 sizeof(meminfo_t), NULL);
305 assert(te != NULL);
306
307 bl1_plat_calc_bl2_layout(&bl1_tzram_layout,
308 (meminfo_t *)transfer_list_entry_data(te));
309
310 transfer_list_update_checksum(secure_tl);
311
312 /**
313 * Before exiting make sure the contents of the TL are flushed in case there's no
314 * support for hardware cache coherency.
315 */
316 flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
317 return 0;
318 }
319 #endif /* TRANSFER_LIST*/
320
321 /* For ARM platform, the NV ctr is shared among all components */
bl1_plat_is_shared_nv_ctr(void)322 bool bl1_plat_is_shared_nv_ctr(void)
323 {
324 return true;
325 }
326