1 /*
2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <bl1/bl1.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <lib/fconf/fconf.h>
16 #include <lib/fconf/fconf_dyn_cfg_getter.h>
17 #if TRANSFER_LIST
18 #include <transfer_list.h>
19 #endif
20 #include <lib/utils.h>
21 #include <lib/xlat_tables/xlat_tables_compat.h>
22 #include <plat/arm/common/plat_arm.h>
23 #include <plat/common/platform.h>
24
25 /* Weak definitions may be overridden in specific ARM standard platform */
26 #pragma weak bl1_early_platform_setup
27 #pragma weak bl1_plat_arch_setup
28 #pragma weak bl1_plat_sec_mem_layout
29 #pragma weak arm_bl1_early_platform_setup
30 #pragma weak bl1_plat_prepare_exit
31 #pragma weak bl1_plat_get_next_image_id
32 #pragma weak plat_arm_bl1_fwu_needed
33 #pragma weak arm_bl1_plat_arch_setup
34 #pragma weak arm_bl1_platform_setup
35
36 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \
37 bl1_tzram_layout.total_base, \
38 bl1_tzram_layout.total_size, \
39 MT_MEMORY | MT_RW | EL3_PAS)
40 /*
41 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
42 * otherwise one region is defined containing both
43 */
44 #if SEPARATE_CODE_AND_RODATA
45 #define MAP_BL1_RO MAP_REGION_FLAT( \
46 BL_CODE_BASE, \
47 BL1_CODE_END - BL_CODE_BASE, \
48 MT_CODE | EL3_PAS), \
49 MAP_REGION_FLAT( \
50 BL1_RO_DATA_BASE, \
51 BL1_RO_DATA_END \
52 - BL_RO_DATA_BASE, \
53 MT_RO_DATA | EL3_PAS)
54 #else
55 #define MAP_BL1_RO MAP_REGION_FLAT( \
56 BL_CODE_BASE, \
57 BL1_CODE_END - BL_CODE_BASE, \
58 MT_CODE | EL3_PAS)
59 #endif
60
61 /* Data structure which holds the extents of the trusted SRAM for BL1*/
62 static meminfo_t bl1_tzram_layout;
63
64 /* Boolean variable to hold condition whether firmware update needed or not */
65 static bool is_fwu_needed;
66
67 struct transfer_list_header *secure_tl;
68
bl1_plat_sec_mem_layout(void)69 struct meminfo *bl1_plat_sec_mem_layout(void)
70 {
71 return &bl1_tzram_layout;
72 }
73
74 /*******************************************************************************
75 * BL1 specific platform actions shared between ARM standard platforms.
76 ******************************************************************************/
arm_bl1_early_platform_setup(void)77 void arm_bl1_early_platform_setup(void)
78 {
79
80 /*
81 * If BL2 is compiled to run at EL3, then it boots BL31, never returning
82 * control to BL1, so the watchdog is not enabled.
83 */
84 #if !ARM_DISABLE_TRUSTED_WDOG && !BL2_RUNS_AT_EL3
85 plat_arm_secure_wdt_start();
86 #endif
87
88 /* Initialize the console to provide early debug support */
89 arm_console_boot_init();
90
91 /* Allow BL1 to see the whole Trusted RAM */
92 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
93 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
94
95 #if TRANSFER_LIST
96 secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
97 PLAT_ARM_FW_HANDOFF_SIZE);
98 assert(secure_tl != NULL);
99 #endif
100 }
101
bl1_early_platform_setup(void)102 void bl1_early_platform_setup(void)
103 {
104 arm_bl1_early_platform_setup();
105 #if !HW_ASSISTED_COHERENCY
106 /*
107 * Initialize Interconnect for this cluster during cold boot.
108 * No need for locks as no other CPU is active.
109 */
110 plat_arm_interconnect_init();
111 /*
112 * Enable Interconnect coherency for the primary CPU's cluster.
113 */
114 plat_arm_interconnect_enter_coherency();
115 #endif
116 }
117
118 /******************************************************************************
119 * Perform the very early platform specific architecture setup shared between
120 * ARM standard platforms. This only does basic initialization. Later
121 * architectural setup (bl1_arch_setup()) does not do anything platform
122 * specific.
123 *****************************************************************************/
arm_bl1_plat_arch_setup(void)124 void arm_bl1_plat_arch_setup(void)
125 {
126 #if USE_COHERENT_MEM
127 /* Ensure ARM platforms don't use coherent memory in BL1. */
128 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
129 #endif
130
131 const mmap_region_t bl_regions[] = {
132 MAP_BL1_TOTAL,
133 MAP_BL1_RO,
134 #if USE_ROMLIB
135 ARM_MAP_ROMLIB_CODE,
136 ARM_MAP_ROMLIB_DATA,
137 #endif
138 {0}
139 };
140
141 setup_page_tables(bl_regions, plat_arm_get_mmap());
142 #ifdef __aarch64__
143 enable_mmu_el3(0);
144 #else
145 enable_mmu_svc_mon(0);
146 #endif /* __aarch64__ */
147
148 arm_setup_romlib();
149 }
150
bl1_plat_arch_setup(void)151 void bl1_plat_arch_setup(void)
152 {
153 arm_bl1_plat_arch_setup();
154 }
155
156 /*
157 * Perform the platform specific architecture setup shared between
158 * ARM standard platforms.
159 */
arm_bl1_platform_setup(void)160 void arm_bl1_platform_setup(void)
161 {
162 const struct dyn_cfg_dtb_info_t *config_info __unused;
163 uint32_t fw_config_max_size __unused;
164 image_info_t config_image_info __unused;
165 struct transfer_list_entry *te __unused;
166
167 image_desc_t *desc;
168
169 int err __unused = 1;
170
171 /* Initialise the IO layer and register platform IO devices */
172 plat_arm_io_setup();
173
174 /* Check if we need FWU before further processing */
175 is_fwu_needed = plat_arm_bl1_fwu_needed();
176 if (is_fwu_needed) {
177 ERROR("Skip platform setup as FWU detected\n");
178 return;
179 }
180
181 #if TRANSFER_LIST
182 #if CRYPTO_SUPPORT
183 te = transfer_list_add(secure_tl, TL_TAG_MBEDTLS_HEAP_INFO,
184 sizeof(struct crypto_heap_info), NULL);
185 assert(te != NULL);
186
187 struct crypto_heap_info *heap_info =
188 (struct crypto_heap_info *)transfer_list_entry_data(te);
189 arm_get_mbedtls_heap(&heap_info->addr, &heap_info->size);
190 #endif /* CRYPTO_SUPPORT */
191
192 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
193
194 #if BL2_ENABLE_SP_LOAD && defined(PLAT_ARM_TB_FW_CONFIG_TL_TAG)
195 /*
196 * To populate the sp_mem_params_descs, load TB_FW_CONFIG.
197 */
198 te = transfer_list_add(secure_tl, PLAT_ARM_TB_FW_CONFIG_TL_TAG,
199 PLAT_ARM_TB_FW_CONFIG_SIZE, NULL);
200 assert(te != NULL);
201
202 SET_PARAM_HEAD(&config_image_info, PARAM_IMAGE_BINARY, VERSION_2, 0);
203 config_image_info.image_base = (uintptr_t) transfer_list_entry_data(te);
204 config_image_info.image_max_size = PLAT_ARM_HW_CONFIG_SIZE;
205
206 err = load_auth_image(TB_FW_CONFIG_ID, &config_image_info);
207 if (err < 0) {
208 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
209 plat_error_handler(err);
210 }
211 #endif
212
213 /*
214 * The event log might have been updated prior to this, make sure we have an
215 * up to date tl before setting the handoff arguments.
216 */
217 transfer_list_update_checksum(secure_tl);
218 transfer_list_set_handoff_args(secure_tl, &desc->ep_info);
219 #else
220 /* Set global DTB info for fixed fw_config information */
221 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
222 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
223
224 /* Fill the device tree information struct with the info from the config dtb */
225 err = fconf_load_config(FW_CONFIG_ID);
226 if (err < 0) {
227 ERROR("Loading of FW_CONFIG failed %d\n", err);
228 plat_error_handler(err);
229 }
230
231 /*
232 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
233 * is successful then load TB_FW_CONFIG device tree.
234 */
235 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
236 if (config_info != NULL) {
237 err = fconf_populate_dtb_registry(config_info->config_addr);
238 if (err < 0) {
239 ERROR("Parsing of FW_CONFIG failed %d\n", err);
240 plat_error_handler(err);
241 }
242
243 /* load TB_FW_CONFIG */
244 err = fconf_load_config(TB_FW_CONFIG_ID);
245 if (err < 0) {
246 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
247 plat_error_handler(err);
248 }
249 } else {
250 ERROR("Invalid FW_CONFIG address\n");
251 plat_error_handler(err);
252 }
253
254 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
255
256 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
257 assert(desc != NULL);
258 desc->ep_info.args.arg0 = config_info->config_addr;
259
260 #if CRYPTO_SUPPORT
261 /* Share the Mbed TLS heap info with other images */
262 arm_bl1_set_mbedtls_heap();
263 #endif /* CRYPTO_SUPPORT */
264 #endif /* TRANSFER_LIST */
265
266 /*
267 * Allow access to the System counter timer module and program
268 * counter frequency for non secure images during FWU
269 */
270 #ifdef ARM_SYS_TIMCTL_BASE
271 arm_configure_sys_timer();
272 #endif
273 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
274 write_cntfrq_el0(plat_get_syscnt_freq2());
275 #endif
276 }
277
bl1_plat_prepare_exit(entry_point_info_t * ep_info)278 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
279 {
280 #if !ARM_DISABLE_TRUSTED_WDOG && !BL2_RUNS_AT_EL3
281 /* Disable watchdog before leaving BL1 */
282 plat_arm_secure_wdt_stop();
283 #endif
284
285 #ifdef EL3_PAYLOAD_BASE
286 /*
287 * Program the EL3 payload's entry point address into the CPUs mailbox
288 * in order to release secondary CPUs from their holding pen and make
289 * them jump there.
290 */
291 plat_arm_program_trusted_mailbox(ep_info->pc);
292 dsbsy();
293 sev();
294 #endif
295 }
296
297 /*
298 * On Arm platforms, the FWU process is triggered when the FIP image has
299 * been tampered with.
300 */
plat_arm_bl1_fwu_needed(void)301 bool plat_arm_bl1_fwu_needed(void)
302 {
303 return !arm_io_is_toc_valid();
304 }
305
306 /*******************************************************************************
307 * The following function checks if Firmware update is needed,
308 * by checking if TOC in FIP image is valid or not.
309 ******************************************************************************/
bl1_plat_get_next_image_id(void)310 unsigned int bl1_plat_get_next_image_id(void)
311 {
312 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
313 }
314
315 #if TRANSFER_LIST
bl1_plat_handle_post_image_load(unsigned int image_id)316 int bl1_plat_handle_post_image_load(unsigned int image_id)
317 {
318 struct transfer_list_entry *te;
319
320 if (image_id != BL2_IMAGE_ID) {
321 return 0;
322 }
323
324 /* Convey this information to BL2 via its TL. */
325 te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT,
326 sizeof(meminfo_t), NULL);
327 assert(te != NULL);
328
329 bl1_plat_calc_bl2_layout(&bl1_tzram_layout,
330 (meminfo_t *)transfer_list_entry_data(te));
331
332 transfer_list_update_checksum(secure_tl);
333
334 /**
335 * Before exiting make sure the contents of the TL are flushed in case there's no
336 * support for hardware cache coherency.
337 */
338 flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
339 return 0;
340 }
341 #endif /* TRANSFER_LIST*/
342
343 /* For ARM platform, the NV ctr is shared among all components */
bl1_plat_is_shared_nv_ctr(void)344 bool bl1_plat_is_shared_nv_ctr(void)
345 {
346 return true;
347 }
348