1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 3 4#include <dt-bindings/reset/rk628-rgu.h> 5#include <dt-bindings/clock/rk628-cgu.h> 6 7/ { 8 rk628_xin_osc0_func: rk628-xin-osc0-func { 9 compatible = "fixed-clock"; 10 #clock-cells = <0>; 11 clock-frequency = <24000000>; 12 clock-output-names = "rk628_xin_osc0_func"; 13 }; 14 15 rk628_xin_osc0_half: rk628-xin-osc0-half { 16 compatible = "fixed-factor-clock"; 17 #clock-cells = <0>; 18 clocks = <&rk628_xin_osc0_func>; 19 clock-mult = <1>; 20 clock-div = <2>; 21 clock-output-names = "rk628_xin_osc0_half"; 22 }; 23}; 24 25&rk628 { 26 compatible = "rockchip,rk628"; 27 28 rk628_cru: cru { 29 compatible = "rockchip,rk628-cru"; 30 #clock-cells = <1>; 31 #reset-cells = <1>; 32 status = "okay"; 33 }; 34 35 rk628_efuse: efuse { 36 compatible = "rockchip,rk628-efuse"; 37 clocks = <&rk628_cru CGU_PCLK_EFUSE>; 38 clock-names = "pclk"; 39 resets = <&rk628_cru RGU_EFUSE>; 40 #phy-cells = <0>; 41 status = "disabled"; 42 }; 43 44 rk628_pinctrl: pinctrl { 45 compatible = "rockchip,rk628-pinctrl"; 46 status = "okay"; 47 48 rk628_gpio0: rk628-gpio0 { 49 clocks = <&rk628_cru CGU_PCLK_GPIO0>; 50 clock-names = "pclk"; 51 resets = <&rk628_cru RGU_GPIO0>; 52 gpio-controller; 53 #gpio-cells = <2>; 54 interrupt-controller; 55 #interrupt-cells = <2>; 56 }; 57 58 rk628_gpio1: rk628-gpio1 { 59 clocks = <&rk628_cru CGU_PCLK_GPIO1>; 60 clock-names = "pclk"; 61 resets = <&rk628_cru RGU_GPIO1>; 62 gpio-controller; 63 #gpio-cells = <2>; 64 interrupt-controller; 65 #interrupt-cells = <2>; 66 }; 67 68 rk628_gpio2: rk628-gpio2 { 69 clocks = <&rk628_cru CGU_PCLK_GPIO2>; 70 clock-names = "pclk"; 71 resets = <&rk628_cru RGU_GPIO2>; 72 gpio-controller; 73 #gpio-cells = <2>; 74 interrupt-controller; 75 #interrupt-cells = <2>; 76 }; 77 78 rk628_gpio3: rk628-gpio3 { 79 clocks = <&rk628_cru CGU_PCLK_GPIO3>; 80 clock-names = "pclk"; 81 resets = <&rk628_cru RGU_GPIO3>; 82 gpio-controller; 83 #gpio-cells = <2>; 84 interrupt-controller; 85 #interrupt-cells = <2>; 86 }; 87 88 rk628_i2sm0_pins: i2sm0 { 89 pins = "gpio0a2", /* i2sm0_sck */ 90 "gpio0a3", /* i2sm0_lr */ 91 "gpio0a4", /* i2sm0_d0 */ 92 "gpio0a5", /* i2sm0_d1 */ 93 "gpio0a6", /* i2sm0_d2 */ 94 "gpio0a7"; /* i2sm0_d3 */ 95 function = "i2sm0"; 96 }; 97 98 rk628_hpd_in_pins: hpd-in { 99 pins = "gpio0b0"; 100 function = "hpd_in"; 101 }; 102 103 rk628_ddc_tx_pins: ddc-tx { 104 pins = "gpio0b1", /* ddc_tx_sda */ 105 "gpio0b2"; /* ddc_tx_scl */ 106 function = "ddc_tx"; 107 }; 108 109 rk628_cec_tx_pins: cec-tx { 110 pins = "gpio0b3"; 111 function = "cec_tx"; 112 }; 113 114 rk628_test_clkout_pins: test-clkout { 115 pins = "gpio1a0"; 116 function = "test_clkout"; 117 }; 118 119 rk628_i2sm1_pins: i2sm1 { 120 pins = "gpio1a2", /* i2sm1_sck */ 121 "gpio1a3", /* i2sm1_lr */ 122 "gpio1a4", /* i2sm1_d0 */ 123 "gpio1a5", /* i2sm1_d1 */ 124 "gpio1a6", /* i2sm1_d2 */ 125 "gpio1a7"; /* i2sm1_d3 */ 126 function = "i2sm1"; 127 }; 128 129 rk628_hpdm0_out_pins: hpdm0-out { 130 pins = "gpio1b0"; 131 function = "hpdm0_out"; 132 }; 133 134 rk628_ddcm0_rx_pins: ddcm0-rx { 135 pins = "gpio1b1", /* ddcm0_rx_sda */ 136 "gpio1b2"; /* ddcm0_rx_scl */ 137 function = "ddcm0_rx"; 138 }; 139 140 rk628_cecm0_rx_pins: cecm0_rx { 141 pins = "gpio1b3"; 142 function = "cecm0_rx"; 143 }; 144 145 rk628_vop_pins: vop { 146 pins = "gpio2a0", /* vop_d0 */ 147 "gpio2a1", /* vop_d1 */ 148 "gpio2a2", /* vop_d2 */ 149 "gpio2a3", /* vop_d3 */ 150 "gpio2a4", /* vop_d4 */ 151 "gpio2a5", /* vop_d5 */ 152 "gpio2a6", /* vop_d6 */ 153 "gpio2a7", /* vop_d7 */ 154 "gpio2b0", /* vop_d8 */ 155 "gpio2b1", /* vop_d9 */ 156 "gpio2b2", /* vop_d10 */ 157 "gpio2b3", /* vop_d11 */ 158 "gpio2b4", /* vop_d12 */ 159 "gpio2b5", /* vop_d13 */ 160 "gpio2b6", /* vop_d14 */ 161 "gpio2b7", /* vop_d15 */ 162 "gpio2c0", /* vop_d16 */ 163 "gpio2c1", /* vop_d17 */ 164 "gpio2c2", /* vop_d18 */ 165 "gpio2c3", /* vop_d19 */ 166 "gpio2c4", /* vop_d20 */ 167 "gpio2c5", /* vop_d21 */ 168 "gpio2c6", /* vop_d22 */ 169 "gpio2c7", /* vop_d23 */ 170 "gpio3a0", /* vop_den */ 171 "gpio3a1", /* vop_hsync */ 172 "gpio3a3", /* vop_vsync */ 173 "gpio3b0"; /* vop_dclk */ 174 function = "vop"; 175 drive-strength = <1>; 176 }; 177 178 rk628_hpdm1_out: hpdm1-out { 179 pins = "gpio3a4"; 180 function = "hpdm1_out"; 181 }; 182 183 rk628_ddcm1_rx_pins: ddcm1-rx { 184 pins = "gpio3a5", /* ddcm1_rx_sda */ 185 "gpio3a6"; /* ddcm1_rx_scl */ 186 function = "ddcm1_rx"; 187 }; 188 189 rk628_cecm1_rx_pins: cecm1-rx { 190 pins = "gpio3a7"; 191 function = "cecm1_rx"; 192 }; 193 194 rk628_gvi_hpd_pins: gvi-hpd { 195 pins = "gpio3b1"; 196 function = "gvi_hpd"; 197 }; 198 199 rk628_gvi_lock_pins: gvi-lock { 200 pins = "gpio3b2"; 201 function = "gvi_lock"; 202 }; 203 204 rk628_hdmirx_cec0: hdmirx-cec0 { 205 pins = "hdmirx_cec"; 206 function = "hdmirx_cec0"; 207 }; 208 209 rk628_hdmirx_cec1: hdmirx-cec1 { 210 pins = "hdmirx_cec"; 211 function = "hdmirx_cec1"; 212 }; 213 214 rk628_rxddc_input0: rxddc-input0 { 215 pins = "rxddc_scl", 216 "rxddc_sda"; 217 function = "rxddc_input0"; 218 }; 219 220 rk628_rxddc_input1: rxddc-input1 { 221 pins = "rxddc_scl", 222 "rxddc_sda"; 223 function = "rxddc_input1"; 224 }; 225 226 rk628_i2sm0_input: i2sm0-input { 227 pins = "i2sm_sck", 228 "i2sm_d", 229 "i2sm_lr"; 230 function = "i2sm0_input"; 231 }; 232 233 rk628_i2sm1_input: i2sm1-input { 234 pins = "i2sm_sck", 235 "i2sm_d", 236 "i2sm_lr"; 237 function = "i2sm1_input"; 238 }; 239 }; 240 241 rk628_combtxphy: combtxphy { 242 compatible = "rockchip,rk628-combtxphy"; 243 clocks = <&rk628_cru CGU_PCLK_TXPHY_CON>, <&rk628_cru CGU_SCLK_VOP>; 244 clock-names = "pclk", "ref_clk"; 245 resets = <&rk628_cru RGU_TXPHY_CON>; 246 #phy-cells = <0>; 247 status = "disabled"; 248 }; 249 250 rk628_combrxphy: combrxphy { 251 compatible = "rockchip,rk628-combrxphy"; 252 clocks = <&rk628_cru CGU_PCLK_RXPHY>; 253 clock-names = "pclk"; 254 resets = <&rk628_cru RGU_RXPHY>; 255 #phy-cells = <0>; 256 status = "disabled"; 257 }; 258 259 rk628_dsi0: dsi0 { 260 compatible = "rockchip,rk628-dsi0"; 261 clocks = <&rk628_cru CGU_PCLK_DSI0>, 262 <&rk628_cru CGU_CLK_CFG_DPHY0>; 263 clock-names = "pclk", "cfg"; 264 resets = <&rk628_cru RGU_DSI0>; 265 phys = <&rk628_combtxphy>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 rk628_dsi1: dsi1 { 272 compatible = "rockchip,rk628-dsi1"; 273 clocks = <&rk628_cru CGU_PCLK_DSI1>, 274 <&rk628_cru CGU_CLK_CFG_DPHY1>; 275 clock-names = "pclk", "cfg"; 276 resets = <&rk628_cru RGU_DSI1>; 277 phys = <&rk628_combtxphy>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 rk628_lvds: lvds { 284 compatible = "rockchip,rk628-lvds"; 285 phys = <&rk628_combtxphy>; 286 status = "disabled"; 287 }; 288 289 rk628_gvi: gvi { 290 compatible = "rockchip,rk628-gvi"; 291 clocks = <&rk628_cru CGU_PCLK_GVIHOST>; 292 clock-names = "pclk"; 293 resets = <&rk628_cru RGU_GVIHOST>; 294 phys = <&rk628_combtxphy>; 295 status = "disabled"; 296 }; 297 298 rk628_rgb_tx: rgb-tx { 299 compatible = "rockchip,rk628-rgb-tx"; 300 status = "disabled"; 301 }; 302 303 rk628_yuv_rx: yuv-rx { 304 compatible = "rockchip,rk628-yuv-rx"; 305 status = "disabled"; 306 }; 307 308 rk628_yuv_tx: yuv-tx { 309 compatible = "rockchip,rk628-yuv-tx"; 310 status = "disabled"; 311 }; 312 313 rk628_bt1120_rx: bt1120-rx { 314 compatible = "rockchip,rk628-bt1120-rx"; 315 clocks = <&rk628_cru CGU_BT1120DEC>; 316 clock-names = "bt1120dec"; 317 resets = <&rk628_cru RGU_BT1120DEC>; 318 status = "disabled"; 319 }; 320 321 rk628_bt1120_tx: bt1120-tx { 322 compatible = "rockchip,rk628-bt1120-tx"; 323 status = "disabled"; 324 }; 325 326 rk628_post_process: post-process { 327 compatible = "rockchip,rk628-post-process"; 328 clocks = <&rk628_cru CGU_SCLK_VOP>, 329 <&rk628_cru CGU_CLK_RX_READ>; 330 clock-names = "sclk_vop", "rx_read"; 331 resets = <&rk628_cru RGU_DECODER>, 332 <&rk628_cru RGU_CLK_RX>, 333 <&rk628_cru RGU_VOP>; 334 reset-names = "decoder", "clk_rx", "vop"; 335 status = "disabled"; 336 }; 337 338 rk628_hdmi: hdmi { 339 compatible = "rockchip,rk628-hdmi"; 340 clocks = <&rk628_cru CGU_PCLK_HDMITX>, 341 <&rk628_cru CGU_SCLK_VOP>; 342 clock-names = "pclk", "dclk"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&rk628_hpd_in_pins &rk628_ddc_tx_pins &rk628_i2sm0_pins>; 345 #sound-dai-cells = <0>; 346 status = "disabled"; 347 }; 348 349 rk628_hdmirx: hdmirx { 350 compatible = "rockchip,rk628-hdmirx"; 351 clocks = <&rk628_cru CGU_PCLK_HDMIRX>, 352 <&rk628_cru CGU_CLK_HDMIRX_CEC>, 353 <&rk628_cru CGU_CLK_HDMIRX_AUD>, 354 <&rk628_cru CGU_CLK_IMODET>; 355 clock-names = "pclk", "cec", "audio", "imodet"; 356 resets = <&rk628_cru RGU_HDMIRX>, 357 <&rk628_cru RGU_HDMIRX_PON>; 358 reset-names = "hdmirx", "hdmirx_pon"; 359 phys = <&rk628_combrxphy>; 360 status = "disabled"; 361 }; 362 363 rk628_csi: csi { 364 compatible = "rockchip,rk628-csi"; 365 clocks = <&rk628_cru CGU_PCLK_HDMIRX>, 366 <&rk628_cru CGU_CLK_IMODET>, 367 <&rk628_cru CGU_CLK_HDMIRX_AUD>, 368 <&rk628_cru CGU_CLK_HDMIRX_CEC>, 369 <&rk628_cru CGU_SCLK_VOP>, 370 <&rk628_cru CGU_CLK_RX_READ>, 371 <&rk628_cru CGU_PCLK_CSI>, 372 <&rk628_cru CGU_CLK_TESTOUT>; 373 clock-names = "hdmirx", "imodet", "hdmirx_aud", "hdmirx_cec", 374 "vop", "rx_read", "csi0", "i2s_mclk"; 375 assigned-clocks = <&rk628_cru CGU_CLK_TESTOUT>; 376 assigned-clock-parents = <&rk628_cru CGU_CLK_HDMIRX_AUD>; 377 resets = <&rk628_cru RGU_HDMIRX>, 378 <&rk628_cru RGU_HDMIRX_PON>, 379 <&rk628_cru RGU_DECODER>, 380 <&rk628_cru RGU_CLK_RX>, 381 <&rk628_cru RGU_VOP>, 382 <&rk628_cru RGU_CSI>; 383 reset-names = "hdmirx", "hdmirx_pon", "decoder", "clk_rx", 384 "vop", "csi0"; 385 phys = <&rk628_combrxphy>, <&rk628_combtxphy>; 386 phy-names = "combrxphy", "combtxphy"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins &rk628_i2sm0_pins &rk628_test_clkout_pins>; 389 status = "disabled"; 390 }; 391}; 392