1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mm/mmu.c
4 *
5 * Copyright (C) 1995-2005 Russell King
6 */
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
14 #include <linux/fs.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
17
18 #include <asm/cp15.h>
19 #include <asm/cputype.h>
20 #include <asm/cachetype.h>
21 #include <asm/fixmap.h>
22 #include <asm/sections.h>
23 #include <asm/setup.h>
24 #include <asm/smp_plat.h>
25 #include <asm/tlb.h>
26 #include <asm/highmem.h>
27 #include <asm/system_info.h>
28 #include <asm/traps.h>
29 #include <asm/procinfo.h>
30 #include <asm/memory.h>
31 #include <asm/pgalloc.h>
32
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
37
38 #include "fault.h"
39 #include "mm.h"
40 #include "tcm.h"
41
42 extern unsigned long __atags_pointer;
43
44 /*
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
47 */
48 struct page *empty_zero_page;
49 EXPORT_SYMBOL(empty_zero_page);
50
51 /*
52 * The pmd table for the upper-most set of pages.
53 */
54 pmd_t *top_pmd;
55
56 pmdval_t user_pmd_table = _PAGE_USER_TABLE;
57
58 #define CPOLICY_UNCACHED 0
59 #define CPOLICY_BUFFERED 1
60 #define CPOLICY_WRITETHROUGH 2
61 #define CPOLICY_WRITEBACK 3
62 #define CPOLICY_WRITEALLOC 4
63
64 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
65 static unsigned int ecc_mask __initdata = 0;
66 pgprot_t pgprot_user;
67 pgprot_t pgprot_kernel;
68
69 EXPORT_SYMBOL(pgprot_user);
70 EXPORT_SYMBOL(pgprot_kernel);
71
72 struct cachepolicy {
73 const char policy[16];
74 unsigned int cr_mask;
75 pmdval_t pmd;
76 pteval_t pte;
77 };
78
79 static struct cachepolicy cache_policies[] __initdata = {
80 {
81 .policy = "uncached",
82 .cr_mask = CR_W|CR_C,
83 .pmd = PMD_SECT_UNCACHED,
84 .pte = L_PTE_MT_UNCACHED,
85 }, {
86 .policy = "buffered",
87 .cr_mask = CR_C,
88 .pmd = PMD_SECT_BUFFERED,
89 .pte = L_PTE_MT_BUFFERABLE,
90 }, {
91 .policy = "writethrough",
92 .cr_mask = 0,
93 .pmd = PMD_SECT_WT,
94 .pte = L_PTE_MT_WRITETHROUGH,
95 }, {
96 .policy = "writeback",
97 .cr_mask = 0,
98 .pmd = PMD_SECT_WB,
99 .pte = L_PTE_MT_WRITEBACK,
100 }, {
101 .policy = "writealloc",
102 .cr_mask = 0,
103 .pmd = PMD_SECT_WBWA,
104 .pte = L_PTE_MT_WRITEALLOC,
105 }
106 };
107
108 #ifdef CONFIG_CPU_CP15
109 static unsigned long initial_pmd_value __initdata = 0;
110
111 /*
112 * Initialise the cache_policy variable with the initial state specified
113 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
114 * the C code sets the page tables up with the same policy as the head
115 * assembly code, which avoids an illegal state where the TLBs can get
116 * confused. See comments in early_cachepolicy() for more information.
117 */
init_default_cache_policy(unsigned long pmd)118 void __init init_default_cache_policy(unsigned long pmd)
119 {
120 int i;
121
122 initial_pmd_value = pmd;
123
124 pmd &= PMD_SECT_CACHE_MASK;
125
126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
127 if (cache_policies[i].pmd == pmd) {
128 cachepolicy = i;
129 break;
130 }
131
132 if (i == ARRAY_SIZE(cache_policies))
133 pr_err("ERROR: could not find cache policy\n");
134 }
135
136 /*
137 * These are useful for identifying cache coherency problems by allowing
138 * the cache or the cache and writebuffer to be turned off. (Note: the
139 * write buffer should not be on and the cache off).
140 */
early_cachepolicy(char * p)141 static int __init early_cachepolicy(char *p)
142 {
143 int i, selected = -1;
144
145 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
146 int len = strlen(cache_policies[i].policy);
147
148 if (memcmp(p, cache_policies[i].policy, len) == 0) {
149 selected = i;
150 break;
151 }
152 }
153
154 if (selected == -1)
155 pr_err("ERROR: unknown or unsupported cache policy\n");
156
157 /*
158 * This restriction is partly to do with the way we boot; it is
159 * unpredictable to have memory mapped using two different sets of
160 * memory attributes (shared, type, and cache attribs). We can not
161 * change these attributes once the initial assembly has setup the
162 * page tables.
163 */
164 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
166 cache_policies[cachepolicy].policy);
167 return 0;
168 }
169
170 if (selected != cachepolicy) {
171 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
172 cachepolicy = selected;
173 flush_cache_all();
174 set_cr(cr);
175 }
176 return 0;
177 }
178 early_param("cachepolicy", early_cachepolicy);
179
early_nocache(char * __unused)180 static int __init early_nocache(char *__unused)
181 {
182 char *p = "buffered";
183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
184 early_cachepolicy(p);
185 return 0;
186 }
187 early_param("nocache", early_nocache);
188
early_nowrite(char * __unused)189 static int __init early_nowrite(char *__unused)
190 {
191 char *p = "uncached";
192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
193 early_cachepolicy(p);
194 return 0;
195 }
196 early_param("nowb", early_nowrite);
197
198 #ifndef CONFIG_ARM_LPAE
early_ecc(char * p)199 static int __init early_ecc(char *p)
200 {
201 if (memcmp(p, "on", 2) == 0)
202 ecc_mask = PMD_PROTECTION;
203 else if (memcmp(p, "off", 3) == 0)
204 ecc_mask = 0;
205 return 0;
206 }
207 early_param("ecc", early_ecc);
208 #endif
209
210 #else /* ifdef CONFIG_CPU_CP15 */
211
early_cachepolicy(char * p)212 static int __init early_cachepolicy(char *p)
213 {
214 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
215 return 0;
216 }
217 early_param("cachepolicy", early_cachepolicy);
218
noalign_setup(char * __unused)219 static int __init noalign_setup(char *__unused)
220 {
221 pr_warn("noalign kernel parameter not supported without cp15\n");
222 return 1;
223 }
224 __setup("noalign", noalign_setup);
225
226 #endif /* ifdef CONFIG_CPU_CP15 / else */
227
228 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
229 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
230 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
231
232 static struct mem_type mem_types[] __ro_after_init = {
233 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
234 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
235 L_PTE_SHARED,
236 .prot_l1 = PMD_TYPE_TABLE,
237 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
238 .domain = DOMAIN_IO,
239 },
240 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
241 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
242 .prot_l1 = PMD_TYPE_TABLE,
243 .prot_sect = PROT_SECT_DEVICE,
244 .domain = DOMAIN_IO,
245 },
246 [MT_DEVICE_CACHED] = { /* ioremap_cache */
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
248 .prot_l1 = PMD_TYPE_TABLE,
249 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
250 .domain = DOMAIN_IO,
251 },
252 [MT_DEVICE_WC] = { /* ioremap_wc */
253 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
254 .prot_l1 = PMD_TYPE_TABLE,
255 .prot_sect = PROT_SECT_DEVICE,
256 .domain = DOMAIN_IO,
257 },
258 [MT_UNCACHED] = {
259 .prot_pte = PROT_PTE_DEVICE,
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
262 .domain = DOMAIN_IO,
263 },
264 [MT_CACHECLEAN] = {
265 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
266 .domain = DOMAIN_KERNEL,
267 },
268 #ifndef CONFIG_ARM_LPAE
269 [MT_MINICLEAN] = {
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
271 .domain = DOMAIN_KERNEL,
272 },
273 #endif
274 [MT_LOW_VECTORS] = {
275 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
276 L_PTE_RDONLY,
277 .prot_l1 = PMD_TYPE_TABLE,
278 .domain = DOMAIN_VECTORS,
279 },
280 [MT_HIGH_VECTORS] = {
281 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
282 L_PTE_USER | L_PTE_RDONLY,
283 .prot_l1 = PMD_TYPE_TABLE,
284 .domain = DOMAIN_VECTORS,
285 },
286 [MT_MEMORY_RWX] = {
287 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
288 .prot_l1 = PMD_TYPE_TABLE,
289 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
290 .domain = DOMAIN_KERNEL,
291 },
292 [MT_MEMORY_RW] = {
293 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
294 L_PTE_XN,
295 .prot_l1 = PMD_TYPE_TABLE,
296 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
297 .domain = DOMAIN_KERNEL,
298 },
299 [MT_MEMORY_RO] = {
300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
301 L_PTE_XN | L_PTE_RDONLY,
302 .prot_l1 = PMD_TYPE_TABLE,
303 #ifdef CONFIG_ARM_LPAE
304 .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2,
305 #else
306 .prot_sect = PMD_TYPE_SECT,
307 #endif
308 .domain = DOMAIN_KERNEL,
309 },
310 [MT_ROM] = {
311 .prot_sect = PMD_TYPE_SECT,
312 .domain = DOMAIN_KERNEL,
313 },
314 [MT_MEMORY_RWX_NONCACHED] = {
315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
316 L_PTE_MT_BUFFERABLE,
317 .prot_l1 = PMD_TYPE_TABLE,
318 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
319 .domain = DOMAIN_KERNEL,
320 },
321 [MT_MEMORY_RW_DTCM] = {
322 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
323 L_PTE_XN,
324 .prot_l1 = PMD_TYPE_TABLE,
325 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
326 .domain = DOMAIN_KERNEL,
327 },
328 [MT_MEMORY_RWX_ITCM] = {
329 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .domain = DOMAIN_KERNEL,
332 },
333 [MT_MEMORY_RW_SO] = {
334 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
335 L_PTE_MT_UNCACHED | L_PTE_XN,
336 .prot_l1 = PMD_TYPE_TABLE,
337 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
338 PMD_SECT_UNCACHED | PMD_SECT_XN,
339 .domain = DOMAIN_KERNEL,
340 },
341 [MT_MEMORY_DMA_READY] = {
342 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
343 L_PTE_XN,
344 .prot_l1 = PMD_TYPE_TABLE,
345 .domain = DOMAIN_KERNEL,
346 },
347 };
348
get_mem_type(unsigned int type)349 const struct mem_type *get_mem_type(unsigned int type)
350 {
351 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
352 }
353 EXPORT_SYMBOL(get_mem_type);
354
355 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
356
357 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
358 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
359
pte_offset_early_fixmap(pmd_t * dir,unsigned long addr)360 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
361 {
362 return &bm_pte[pte_index(addr)];
363 }
364
pte_offset_late_fixmap(pmd_t * dir,unsigned long addr)365 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
366 {
367 return pte_offset_kernel(dir, addr);
368 }
369
fixmap_pmd(unsigned long addr)370 static inline pmd_t * __init fixmap_pmd(unsigned long addr)
371 {
372 return pmd_off_k(addr);
373 }
374
early_fixmap_init(void)375 void __init early_fixmap_init(void)
376 {
377 pmd_t *pmd;
378
379 /*
380 * The early fixmap range spans multiple pmds, for which
381 * we are not prepared:
382 */
383 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
384 != FIXADDR_TOP >> PMD_SHIFT);
385
386 pmd = fixmap_pmd(FIXADDR_TOP);
387 pmd_populate_kernel(&init_mm, pmd, bm_pte);
388
389 pte_offset_fixmap = pte_offset_early_fixmap;
390 }
391
392 /*
393 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
394 * As a result, this can only be called with preemption disabled, as under
395 * stop_machine().
396 */
__set_fixmap(enum fixed_addresses idx,phys_addr_t phys,pgprot_t prot)397 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
398 {
399 unsigned long vaddr = __fix_to_virt(idx);
400 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
401
402 /* Make sure fixmap region does not exceed available allocation. */
403 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
404 FIXADDR_END);
405 BUG_ON(idx >= __end_of_fixed_addresses);
406
407 /* We support only device mappings before pgprot_kernel is set. */
408 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
409 pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
410 return;
411
412 if (pgprot_val(prot))
413 set_pte_at(NULL, vaddr, pte,
414 pfn_pte(phys >> PAGE_SHIFT, prot));
415 else
416 pte_clear(NULL, vaddr, pte);
417 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
418 }
419
420 /*
421 * Adjust the PMD section entries according to the CPU in use.
422 */
build_mem_type_table(void)423 static void __init build_mem_type_table(void)
424 {
425 struct cachepolicy *cp;
426 unsigned int cr = get_cr();
427 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
428 int cpu_arch = cpu_architecture();
429 int i;
430
431 if (cpu_arch < CPU_ARCH_ARMv6) {
432 #if defined(CONFIG_CPU_DCACHE_DISABLE)
433 if (cachepolicy > CPOLICY_BUFFERED)
434 cachepolicy = CPOLICY_BUFFERED;
435 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
436 if (cachepolicy > CPOLICY_WRITETHROUGH)
437 cachepolicy = CPOLICY_WRITETHROUGH;
438 #endif
439 }
440 if (cpu_arch < CPU_ARCH_ARMv5) {
441 if (cachepolicy >= CPOLICY_WRITEALLOC)
442 cachepolicy = CPOLICY_WRITEBACK;
443 ecc_mask = 0;
444 }
445
446 if (is_smp()) {
447 if (cachepolicy != CPOLICY_WRITEALLOC) {
448 pr_warn("Forcing write-allocate cache policy for SMP\n");
449 cachepolicy = CPOLICY_WRITEALLOC;
450 }
451 if (!(initial_pmd_value & PMD_SECT_S)) {
452 pr_warn("Forcing shared mappings for SMP\n");
453 initial_pmd_value |= PMD_SECT_S;
454 }
455 }
456
457 /*
458 * Strip out features not present on earlier architectures.
459 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
460 * without extended page tables don't have the 'Shared' bit.
461 */
462 if (cpu_arch < CPU_ARCH_ARMv5)
463 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
464 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
465 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
466 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
467 mem_types[i].prot_sect &= ~PMD_SECT_S;
468
469 /*
470 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
471 * "update-able on write" bit on ARM610). However, Xscale and
472 * Xscale3 require this bit to be cleared.
473 */
474 if (cpu_is_xscale_family()) {
475 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
476 mem_types[i].prot_sect &= ~PMD_BIT4;
477 mem_types[i].prot_l1 &= ~PMD_BIT4;
478 }
479 } else if (cpu_arch < CPU_ARCH_ARMv6) {
480 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
481 if (mem_types[i].prot_l1)
482 mem_types[i].prot_l1 |= PMD_BIT4;
483 if (mem_types[i].prot_sect)
484 mem_types[i].prot_sect |= PMD_BIT4;
485 }
486 }
487
488 /*
489 * Mark the device areas according to the CPU/architecture.
490 */
491 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
492 if (!cpu_is_xsc3()) {
493 /*
494 * Mark device regions on ARMv6+ as execute-never
495 * to prevent speculative instruction fetches.
496 */
497 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
498 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
499 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
501
502 /* Also setup NX memory mapping */
503 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
504 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN;
505 }
506 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
507 /*
508 * For ARMv7 with TEX remapping,
509 * - shared device is SXCB=1100
510 * - nonshared device is SXCB=0100
511 * - write combine device mem is SXCB=0001
512 * (Uncached Normal memory)
513 */
514 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
515 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
516 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
517 } else if (cpu_is_xsc3()) {
518 /*
519 * For Xscale3,
520 * - shared device is TEXCB=00101
521 * - nonshared device is TEXCB=01000
522 * - write combine device mem is TEXCB=00100
523 * (Inner/Outer Uncacheable in xsc3 parlance)
524 */
525 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
526 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
527 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
528 } else {
529 /*
530 * For ARMv6 and ARMv7 without TEX remapping,
531 * - shared device is TEXCB=00001
532 * - nonshared device is TEXCB=01000
533 * - write combine device mem is TEXCB=00100
534 * (Uncached Normal in ARMv6 parlance).
535 */
536 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
537 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
538 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
539 }
540 } else {
541 /*
542 * On others, write combining is "Uncached/Buffered"
543 */
544 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
545 }
546
547 /*
548 * Now deal with the memory-type mappings
549 */
550 cp = &cache_policies[cachepolicy];
551 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
552
553 #ifndef CONFIG_ARM_LPAE
554 /*
555 * We don't use domains on ARMv6 (since this causes problems with
556 * v6/v7 kernels), so we must use a separate memory type for user
557 * r/o, kernel r/w to map the vectors page.
558 */
559 if (cpu_arch == CPU_ARCH_ARMv6)
560 vecs_pgprot |= L_PTE_MT_VECTORS;
561
562 /*
563 * Check is it with support for the PXN bit
564 * in the Short-descriptor translation table format descriptors.
565 */
566 if (cpu_arch == CPU_ARCH_ARMv7 &&
567 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
568 user_pmd_table |= PMD_PXNTABLE;
569 }
570 #endif
571
572 /*
573 * ARMv6 and above have extended page tables.
574 */
575 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
576 #ifndef CONFIG_ARM_LPAE
577 /*
578 * Mark cache clean areas and XIP ROM read only
579 * from SVC mode and no access from userspace.
580 */
581 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
582 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
583 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
584 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
585 #endif
586
587 /*
588 * If the initial page tables were created with the S bit
589 * set, then we need to do the same here for the same
590 * reasons given in early_cachepolicy().
591 */
592 if (initial_pmd_value & PMD_SECT_S) {
593 user_pgprot |= L_PTE_SHARED;
594 kern_pgprot |= L_PTE_SHARED;
595 vecs_pgprot |= L_PTE_SHARED;
596 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
597 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
598 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
599 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
600 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
601 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
602 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
603 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
604 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S;
605 mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED;
606 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
607 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
608 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
609 }
610 }
611
612 /*
613 * Non-cacheable Normal - intended for memory areas that must
614 * not cause dirty cache line writebacks when used
615 */
616 if (cpu_arch >= CPU_ARCH_ARMv6) {
617 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
618 /* Non-cacheable Normal is XCB = 001 */
619 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
620 PMD_SECT_BUFFERED;
621 } else {
622 /* For both ARMv6 and non-TEX-remapping ARMv7 */
623 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
624 PMD_SECT_TEX(1);
625 }
626 } else {
627 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
628 }
629
630 #ifdef CONFIG_ARM_LPAE
631 /*
632 * Do not generate access flag faults for the kernel mappings.
633 */
634 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
635 mem_types[i].prot_pte |= PTE_EXT_AF;
636 if (mem_types[i].prot_sect)
637 mem_types[i].prot_sect |= PMD_SECT_AF;
638 }
639 kern_pgprot |= PTE_EXT_AF;
640 vecs_pgprot |= PTE_EXT_AF;
641
642 /*
643 * Set PXN for user mappings
644 */
645 user_pgprot |= PTE_EXT_PXN;
646 #endif
647
648 for (i = 0; i < 16; i++) {
649 pteval_t v = pgprot_val(protection_map[i]);
650 protection_map[i] = __pgprot(v | user_pgprot);
651 }
652
653 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
654 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
655
656 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
657 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
658 L_PTE_DIRTY | kern_pgprot);
659
660 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
661 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
662 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
663 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
664 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
665 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
666 mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd;
667 mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot;
668 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
669 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
670 mem_types[MT_ROM].prot_sect |= cp->pmd;
671
672 switch (cp->pmd) {
673 case PMD_SECT_WT:
674 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
675 break;
676 case PMD_SECT_WB:
677 case PMD_SECT_WBWA:
678 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
679 break;
680 }
681 pr_info("Memory policy: %sData cache %s\n",
682 ecc_mask ? "ECC enabled, " : "", cp->policy);
683
684 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
685 struct mem_type *t = &mem_types[i];
686 if (t->prot_l1)
687 t->prot_l1 |= PMD_DOMAIN(t->domain);
688 if (t->prot_sect)
689 t->prot_sect |= PMD_DOMAIN(t->domain);
690 }
691 }
692
693 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
phys_mem_access_prot(struct file * file,unsigned long pfn,unsigned long size,pgprot_t vma_prot)694 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
695 unsigned long size, pgprot_t vma_prot)
696 {
697 if (!pfn_valid(pfn))
698 return pgprot_noncached(vma_prot);
699 else if (file->f_flags & O_SYNC)
700 return pgprot_writecombine(vma_prot);
701 return vma_prot;
702 }
703 EXPORT_SYMBOL(phys_mem_access_prot);
704 #endif
705
706 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
707
early_alloc(unsigned long sz)708 static void __init *early_alloc(unsigned long sz)
709 {
710 void *ptr = memblock_alloc(sz, sz);
711
712 if (!ptr)
713 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
714 __func__, sz, sz);
715
716 return ptr;
717 }
718
late_alloc(unsigned long sz)719 static void *__init late_alloc(unsigned long sz)
720 {
721 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
722
723 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
724 BUG();
725 return ptr;
726 }
727
arm_pte_alloc(pmd_t * pmd,unsigned long addr,unsigned long prot,void * (* alloc)(unsigned long sz))728 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
729 unsigned long prot,
730 void *(*alloc)(unsigned long sz))
731 {
732 if (pmd_none(*pmd)) {
733 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
734 __pmd_populate(pmd, __pa(pte), prot);
735 }
736 BUG_ON(pmd_bad(*pmd));
737 return pte_offset_kernel(pmd, addr);
738 }
739
early_pte_alloc(pmd_t * pmd,unsigned long addr,unsigned long prot)740 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
741 unsigned long prot)
742 {
743 return arm_pte_alloc(pmd, addr, prot, early_alloc);
744 }
745
alloc_init_pte(pmd_t * pmd,unsigned long addr,unsigned long end,unsigned long pfn,const struct mem_type * type,void * (* alloc)(unsigned long sz),bool ng)746 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
747 unsigned long end, unsigned long pfn,
748 const struct mem_type *type,
749 void *(*alloc)(unsigned long sz),
750 bool ng)
751 {
752 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
753 do {
754 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
755 ng ? PTE_EXT_NG : 0);
756 pfn++;
757 } while (pte++, addr += PAGE_SIZE, addr != end);
758 }
759
__map_init_section(pmd_t * pmd,unsigned long addr,unsigned long end,phys_addr_t phys,const struct mem_type * type,bool ng)760 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
761 unsigned long end, phys_addr_t phys,
762 const struct mem_type *type, bool ng)
763 {
764 pmd_t *p = pmd;
765
766 #ifndef CONFIG_ARM_LPAE
767 /*
768 * In classic MMU format, puds and pmds are folded in to
769 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
770 * group of L1 entries making up one logical pointer to
771 * an L2 table (2MB), where as PMDs refer to the individual
772 * L1 entries (1MB). Hence increment to get the correct
773 * offset for odd 1MB sections.
774 * (See arch/arm/include/asm/pgtable-2level.h)
775 */
776 if (addr & SECTION_SIZE)
777 pmd++;
778 #endif
779 do {
780 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
781 phys += SECTION_SIZE;
782 } while (pmd++, addr += SECTION_SIZE, addr != end);
783
784 flush_pmd_entry(p);
785 }
786
alloc_init_pmd(pud_t * pud,unsigned long addr,unsigned long end,phys_addr_t phys,const struct mem_type * type,void * (* alloc)(unsigned long sz),bool ng)787 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
788 unsigned long end, phys_addr_t phys,
789 const struct mem_type *type,
790 void *(*alloc)(unsigned long sz), bool ng)
791 {
792 pmd_t *pmd = pmd_offset(pud, addr);
793 unsigned long next;
794
795 do {
796 /*
797 * With LPAE, we must loop over to map
798 * all the pmds for the given range.
799 */
800 next = pmd_addr_end(addr, end);
801
802 /*
803 * Try a section mapping - addr, next and phys must all be
804 * aligned to a section boundary.
805 */
806 if (type->prot_sect &&
807 ((addr | next | phys) & ~SECTION_MASK) == 0) {
808 __map_init_section(pmd, addr, next, phys, type, ng);
809 } else {
810 alloc_init_pte(pmd, addr, next,
811 __phys_to_pfn(phys), type, alloc, ng);
812 }
813
814 phys += next - addr;
815
816 } while (pmd++, addr = next, addr != end);
817 }
818
alloc_init_pud(p4d_t * p4d,unsigned long addr,unsigned long end,phys_addr_t phys,const struct mem_type * type,void * (* alloc)(unsigned long sz),bool ng)819 static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
820 unsigned long end, phys_addr_t phys,
821 const struct mem_type *type,
822 void *(*alloc)(unsigned long sz), bool ng)
823 {
824 pud_t *pud = pud_offset(p4d, addr);
825 unsigned long next;
826
827 do {
828 next = pud_addr_end(addr, end);
829 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
830 phys += next - addr;
831 } while (pud++, addr = next, addr != end);
832 }
833
alloc_init_p4d(pgd_t * pgd,unsigned long addr,unsigned long end,phys_addr_t phys,const struct mem_type * type,void * (* alloc)(unsigned long sz),bool ng)834 static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
835 unsigned long end, phys_addr_t phys,
836 const struct mem_type *type,
837 void *(*alloc)(unsigned long sz), bool ng)
838 {
839 p4d_t *p4d = p4d_offset(pgd, addr);
840 unsigned long next;
841
842 do {
843 next = p4d_addr_end(addr, end);
844 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
845 phys += next - addr;
846 } while (p4d++, addr = next, addr != end);
847 }
848
849 #ifndef CONFIG_ARM_LPAE
create_36bit_mapping(struct mm_struct * mm,struct map_desc * md,const struct mem_type * type,bool ng)850 static void __init create_36bit_mapping(struct mm_struct *mm,
851 struct map_desc *md,
852 const struct mem_type *type,
853 bool ng)
854 {
855 unsigned long addr, length, end;
856 phys_addr_t phys;
857 pgd_t *pgd;
858
859 addr = md->virtual;
860 phys = __pfn_to_phys(md->pfn);
861 length = PAGE_ALIGN(md->length);
862
863 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
864 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
865 (long long)__pfn_to_phys((u64)md->pfn), addr);
866 return;
867 }
868
869 /* N.B. ARMv6 supersections are only defined to work with domain 0.
870 * Since domain assignments can in fact be arbitrary, the
871 * 'domain == 0' check below is required to insure that ARMv6
872 * supersections are only allocated for domain 0 regardless
873 * of the actual domain assignments in use.
874 */
875 if (type->domain) {
876 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
877 (long long)__pfn_to_phys((u64)md->pfn), addr);
878 return;
879 }
880
881 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
882 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
883 (long long)__pfn_to_phys((u64)md->pfn), addr);
884 return;
885 }
886
887 /*
888 * Shift bits [35:32] of address into bits [23:20] of PMD
889 * (See ARMv6 spec).
890 */
891 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
892
893 pgd = pgd_offset(mm, addr);
894 end = addr + length;
895 do {
896 p4d_t *p4d = p4d_offset(pgd, addr);
897 pud_t *pud = pud_offset(p4d, addr);
898 pmd_t *pmd = pmd_offset(pud, addr);
899 int i;
900
901 for (i = 0; i < 16; i++)
902 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
903 (ng ? PMD_SECT_nG : 0));
904
905 addr += SUPERSECTION_SIZE;
906 phys += SUPERSECTION_SIZE;
907 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
908 } while (addr != end);
909 }
910 #endif /* !CONFIG_ARM_LPAE */
911
__create_mapping(struct mm_struct * mm,struct map_desc * md,void * (* alloc)(unsigned long sz),bool ng)912 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
913 void *(*alloc)(unsigned long sz),
914 bool ng)
915 {
916 unsigned long addr, length, end;
917 phys_addr_t phys;
918 const struct mem_type *type;
919 pgd_t *pgd;
920
921 type = &mem_types[md->type];
922
923 #ifndef CONFIG_ARM_LPAE
924 /*
925 * Catch 36-bit addresses
926 */
927 if (md->pfn >= 0x100000) {
928 create_36bit_mapping(mm, md, type, ng);
929 return;
930 }
931 #endif
932
933 addr = md->virtual & PAGE_MASK;
934 phys = __pfn_to_phys(md->pfn);
935 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
936
937 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
938 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
939 (long long)__pfn_to_phys(md->pfn), addr);
940 return;
941 }
942
943 pgd = pgd_offset(mm, addr);
944 end = addr + length;
945 do {
946 unsigned long next = pgd_addr_end(addr, end);
947
948 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
949
950 phys += next - addr;
951 addr = next;
952 } while (pgd++, addr != end);
953 }
954
955 /*
956 * Create the page directory entries and any necessary
957 * page tables for the mapping specified by `md'. We
958 * are able to cope here with varying sizes and address
959 * offsets, and we take full advantage of sections and
960 * supersections.
961 */
create_mapping(struct map_desc * md)962 static void __init create_mapping(struct map_desc *md)
963 {
964 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
965 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
966 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
967 return;
968 }
969
970 if (md->type == MT_DEVICE &&
971 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
972 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
973 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
974 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
975 }
976
977 __create_mapping(&init_mm, md, early_alloc, false);
978 }
979
create_mapping_late(struct mm_struct * mm,struct map_desc * md,bool ng)980 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
981 bool ng)
982 {
983 #ifdef CONFIG_ARM_LPAE
984 p4d_t *p4d;
985 pud_t *pud;
986
987 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
988 if (WARN_ON(!p4d))
989 return;
990 pud = pud_alloc(mm, p4d, md->virtual);
991 if (WARN_ON(!pud))
992 return;
993 pmd_alloc(mm, pud, 0);
994 #endif
995 __create_mapping(mm, md, late_alloc, ng);
996 }
997
998 /*
999 * Create the architecture specific mappings
1000 */
iotable_init(struct map_desc * io_desc,int nr)1001 void __init iotable_init(struct map_desc *io_desc, int nr)
1002 {
1003 struct map_desc *md;
1004 struct vm_struct *vm;
1005 struct static_vm *svm;
1006
1007 if (!nr)
1008 return;
1009
1010 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
1011 if (!svm)
1012 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1013 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1014
1015 for (md = io_desc; nr; md++, nr--) {
1016 create_mapping(md);
1017
1018 vm = &svm->vm;
1019 vm->addr = (void *)(md->virtual & PAGE_MASK);
1020 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1021 vm->phys_addr = __pfn_to_phys(md->pfn);
1022 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1023 vm->flags |= VM_ARM_MTYPE(md->type);
1024 vm->caller = iotable_init;
1025 add_static_vm_early(svm++);
1026 }
1027 }
1028
vm_reserve_area_early(unsigned long addr,unsigned long size,void * caller)1029 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1030 void *caller)
1031 {
1032 struct vm_struct *vm;
1033 struct static_vm *svm;
1034
1035 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1036 if (!svm)
1037 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1038 __func__, sizeof(*svm), __alignof__(*svm));
1039
1040 vm = &svm->vm;
1041 vm->addr = (void *)addr;
1042 vm->size = size;
1043 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1044 vm->caller = caller;
1045 add_static_vm_early(svm);
1046 }
1047
1048 #ifndef CONFIG_ARM_LPAE
1049
1050 /*
1051 * The Linux PMD is made of two consecutive section entries covering 2MB
1052 * (see definition in include/asm/pgtable-2level.h). However a call to
1053 * create_mapping() may optimize static mappings by using individual
1054 * 1MB section mappings. This leaves the actual PMD potentially half
1055 * initialized if the top or bottom section entry isn't used, leaving it
1056 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1057 * the virtual space left free by that unused section entry.
1058 *
1059 * Let's avoid the issue by inserting dummy vm entries covering the unused
1060 * PMD halves once the static mappings are in place.
1061 */
1062
pmd_empty_section_gap(unsigned long addr)1063 static void __init pmd_empty_section_gap(unsigned long addr)
1064 {
1065 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1066 }
1067
fill_pmd_gaps(void)1068 static void __init fill_pmd_gaps(void)
1069 {
1070 struct static_vm *svm;
1071 struct vm_struct *vm;
1072 unsigned long addr, next = 0;
1073 pmd_t *pmd;
1074
1075 list_for_each_entry(svm, &static_vmlist, list) {
1076 vm = &svm->vm;
1077 addr = (unsigned long)vm->addr;
1078 if (addr < next)
1079 continue;
1080
1081 /*
1082 * Check if this vm starts on an odd section boundary.
1083 * If so and the first section entry for this PMD is free
1084 * then we block the corresponding virtual address.
1085 */
1086 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1087 pmd = pmd_off_k(addr);
1088 if (pmd_none(*pmd))
1089 pmd_empty_section_gap(addr & PMD_MASK);
1090 }
1091
1092 /*
1093 * Then check if this vm ends on an odd section boundary.
1094 * If so and the second section entry for this PMD is empty
1095 * then we block the corresponding virtual address.
1096 */
1097 addr += vm->size;
1098 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1099 pmd = pmd_off_k(addr) + 1;
1100 if (pmd_none(*pmd))
1101 pmd_empty_section_gap(addr);
1102 }
1103
1104 /* no need to look at any vm entry until we hit the next PMD */
1105 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1106 }
1107 }
1108
1109 #else
1110 #define fill_pmd_gaps() do { } while (0)
1111 #endif
1112
1113 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
pci_reserve_io(void)1114 static void __init pci_reserve_io(void)
1115 {
1116 struct static_vm *svm;
1117
1118 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1119 if (svm)
1120 return;
1121
1122 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1123 }
1124 #else
1125 #define pci_reserve_io() do { } while (0)
1126 #endif
1127
1128 #ifdef CONFIG_DEBUG_LL
debug_ll_io_init(void)1129 void __init debug_ll_io_init(void)
1130 {
1131 struct map_desc map;
1132
1133 debug_ll_addr(&map.pfn, &map.virtual);
1134 if (!map.pfn || !map.virtual)
1135 return;
1136 map.pfn = __phys_to_pfn(map.pfn);
1137 map.virtual &= PAGE_MASK;
1138 map.length = PAGE_SIZE;
1139 map.type = MT_DEVICE;
1140 iotable_init(&map, 1);
1141 }
1142 #endif
1143
1144 static void * __initdata vmalloc_min =
1145 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1146
1147 /*
1148 * vmalloc=size forces the vmalloc area to be exactly 'size'
1149 * bytes. This can be used to increase (or decrease) the vmalloc
1150 * area - the default is 240m.
1151 */
early_vmalloc(char * arg)1152 static int __init early_vmalloc(char *arg)
1153 {
1154 unsigned long vmalloc_reserve = memparse(arg, NULL);
1155
1156 if (vmalloc_reserve < SZ_16M) {
1157 vmalloc_reserve = SZ_16M;
1158 pr_warn("vmalloc area too small, limiting to %luMB\n",
1159 vmalloc_reserve >> 20);
1160 }
1161
1162 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1163 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1164 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1165 vmalloc_reserve >> 20);
1166 }
1167
1168 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1169 return 0;
1170 }
1171 early_param("vmalloc", early_vmalloc);
1172
1173 phys_addr_t arm_lowmem_limit __initdata = 0;
1174
adjust_lowmem_bounds(void)1175 void __init adjust_lowmem_bounds(void)
1176 {
1177 phys_addr_t block_start, block_end, memblock_limit = 0;
1178 u64 vmalloc_limit, i;
1179 phys_addr_t lowmem_limit = 0;
1180
1181 /*
1182 * Let's use our own (unoptimized) equivalent of __pa() that is
1183 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1184 * The result is used as the upper bound on physical memory address
1185 * and may itself be outside the valid range for which phys_addr_t
1186 * and therefore __pa() is defined.
1187 */
1188 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1189
1190 /*
1191 * The first usable region must be PMD aligned. Mark its start
1192 * as MEMBLOCK_NOMAP if it isn't
1193 */
1194 for_each_mem_range(i, &block_start, &block_end) {
1195 if (!IS_ALIGNED(block_start, PMD_SIZE)) {
1196 phys_addr_t len;
1197
1198 len = round_up(block_start, PMD_SIZE) - block_start;
1199 memblock_mark_nomap(block_start, len);
1200 }
1201 break;
1202 }
1203
1204 for_each_mem_range(i, &block_start, &block_end) {
1205 if (block_start < vmalloc_limit) {
1206 if (block_end > lowmem_limit)
1207 /*
1208 * Compare as u64 to ensure vmalloc_limit does
1209 * not get truncated. block_end should always
1210 * fit in phys_addr_t so there should be no
1211 * issue with assignment.
1212 */
1213 lowmem_limit = min_t(u64,
1214 vmalloc_limit,
1215 block_end);
1216
1217 /*
1218 * Find the first non-pmd-aligned page, and point
1219 * memblock_limit at it. This relies on rounding the
1220 * limit down to be pmd-aligned, which happens at the
1221 * end of this function.
1222 *
1223 * With this algorithm, the start or end of almost any
1224 * bank can be non-pmd-aligned. The only exception is
1225 * that the start of the bank 0 must be section-
1226 * aligned, since otherwise memory would need to be
1227 * allocated when mapping the start of bank 0, which
1228 * occurs before any free memory is mapped.
1229 */
1230 if (!memblock_limit) {
1231 if (!IS_ALIGNED(block_start, PMD_SIZE))
1232 memblock_limit = block_start;
1233 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1234 memblock_limit = lowmem_limit;
1235 }
1236
1237 }
1238 }
1239
1240 arm_lowmem_limit = lowmem_limit;
1241
1242 high_memory = __va(arm_lowmem_limit - 1) + 1;
1243
1244 if (!memblock_limit)
1245 memblock_limit = arm_lowmem_limit;
1246
1247 /*
1248 * Round the memblock limit down to a pmd size. This
1249 * helps to ensure that we will allocate memory from the
1250 * last full pmd, which should be mapped.
1251 */
1252 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1253
1254 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1255 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1256 phys_addr_t end = memblock_end_of_DRAM();
1257
1258 pr_notice("Ignoring RAM at %pa-%pa\n",
1259 &memblock_limit, &end);
1260 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1261
1262 memblock_remove(memblock_limit, end - memblock_limit);
1263 }
1264 }
1265
1266 memblock_set_current_limit(memblock_limit);
1267 }
1268
prepare_page_table(void)1269 static inline void prepare_page_table(void)
1270 {
1271 unsigned long addr;
1272 phys_addr_t end;
1273
1274 /*
1275 * Clear out all the mappings below the kernel image.
1276 */
1277 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1278 pmd_clear(pmd_off_k(addr));
1279
1280 #ifdef CONFIG_XIP_KERNEL
1281 /* The XIP kernel is mapped in the module area -- skip over it */
1282 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1283 #endif
1284 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1285 pmd_clear(pmd_off_k(addr));
1286
1287 /*
1288 * Find the end of the first block of lowmem.
1289 */
1290 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1291 if (end >= arm_lowmem_limit)
1292 end = arm_lowmem_limit;
1293
1294 /*
1295 * Clear out all the kernel space mappings, except for the first
1296 * memory bank, up to the vmalloc region.
1297 */
1298 for (addr = __phys_to_virt(end);
1299 addr < VMALLOC_START; addr += PMD_SIZE)
1300 pmd_clear(pmd_off_k(addr));
1301 }
1302
1303 #ifdef CONFIG_ARM_LPAE
1304 /* the first page is reserved for pgd */
1305 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1306 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1307 #else
1308 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1309 #endif
1310
1311 /*
1312 * Reserve the special regions of memory
1313 */
arm_mm_memblock_reserve(void)1314 void __init arm_mm_memblock_reserve(void)
1315 {
1316 /*
1317 * Reserve the page tables. These are already in use,
1318 * and can only be in node 0.
1319 */
1320 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1321
1322 #ifdef CONFIG_SA1111
1323 /*
1324 * Because of the SA1111 DMA bug, we want to preserve our
1325 * precious DMA-able memory...
1326 */
1327 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1328 #endif
1329 }
1330
1331 /*
1332 * Set up the device mappings. Since we clear out the page tables for all
1333 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1334 * device mappings. This means earlycon can be used to debug this function
1335 * Any other function or debugging method which may touch any device _will_
1336 * crash the kernel.
1337 */
devicemaps_init(const struct machine_desc * mdesc)1338 static void __init devicemaps_init(const struct machine_desc *mdesc)
1339 {
1340 struct map_desc map;
1341 unsigned long addr;
1342 void *vectors;
1343
1344 /*
1345 * Allocate the vector page early.
1346 */
1347 vectors = early_alloc(PAGE_SIZE * 2);
1348
1349 early_trap_init(vectors);
1350
1351 /*
1352 * Clear page table except top pmd used by early fixmaps
1353 */
1354 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1355 pmd_clear(pmd_off_k(addr));
1356
1357 if (__atags_pointer) {
1358 /* create a read-only mapping of the device tree */
1359 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
1360 map.virtual = FDT_FIXED_BASE;
1361 map.length = FDT_FIXED_SIZE;
1362 map.type = MT_MEMORY_RO;
1363 create_mapping(&map);
1364 }
1365
1366 /*
1367 * Map the kernel if it is XIP.
1368 * It is always first in the modulearea.
1369 */
1370 #ifdef CONFIG_XIP_KERNEL
1371 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1372 map.virtual = MODULES_VADDR;
1373 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1374 map.type = MT_ROM;
1375 create_mapping(&map);
1376 #endif
1377
1378 /*
1379 * Map the cache flushing regions.
1380 */
1381 #ifdef FLUSH_BASE
1382 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1383 map.virtual = FLUSH_BASE;
1384 map.length = SZ_1M;
1385 map.type = MT_CACHECLEAN;
1386 create_mapping(&map);
1387 #endif
1388 #ifdef FLUSH_BASE_MINICACHE
1389 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1390 map.virtual = FLUSH_BASE_MINICACHE;
1391 map.length = SZ_1M;
1392 map.type = MT_MINICLEAN;
1393 create_mapping(&map);
1394 #endif
1395
1396 /*
1397 * Create a mapping for the machine vectors at the high-vectors
1398 * location (0xffff0000). If we aren't using high-vectors, also
1399 * create a mapping at the low-vectors virtual address.
1400 */
1401 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1402 map.virtual = 0xffff0000;
1403 map.length = PAGE_SIZE;
1404 #ifdef CONFIG_KUSER_HELPERS
1405 map.type = MT_HIGH_VECTORS;
1406 #else
1407 map.type = MT_LOW_VECTORS;
1408 #endif
1409 create_mapping(&map);
1410
1411 if (!vectors_high()) {
1412 map.virtual = 0;
1413 map.length = PAGE_SIZE * 2;
1414 map.type = MT_LOW_VECTORS;
1415 create_mapping(&map);
1416 }
1417
1418 /* Now create a kernel read-only mapping */
1419 map.pfn += 1;
1420 map.virtual = 0xffff0000 + PAGE_SIZE;
1421 map.length = PAGE_SIZE;
1422 map.type = MT_LOW_VECTORS;
1423 create_mapping(&map);
1424
1425 /*
1426 * Ask the machine support to map in the statically mapped devices.
1427 */
1428 if (mdesc->map_io)
1429 mdesc->map_io();
1430 else
1431 debug_ll_io_init();
1432 fill_pmd_gaps();
1433
1434 /* Reserve fixed i/o space in VMALLOC region */
1435 pci_reserve_io();
1436
1437 /*
1438 * Finally flush the caches and tlb to ensure that we're in a
1439 * consistent state wrt the writebuffer. This also ensures that
1440 * any write-allocated cache lines in the vector page are written
1441 * back. After this point, we can start to touch devices again.
1442 */
1443 local_flush_tlb_all();
1444 flush_cache_all();
1445
1446 /* Enable asynchronous aborts */
1447 early_abt_enable();
1448 }
1449
kmap_init(void)1450 static void __init kmap_init(void)
1451 {
1452 #ifdef CONFIG_HIGHMEM
1453 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1454 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1455 #endif
1456
1457 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1458 _PAGE_KERNEL_TABLE);
1459 }
1460
map_lowmem(void)1461 static void __init map_lowmem(void)
1462 {
1463 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1464 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1465 phys_addr_t start, end;
1466 u64 i;
1467
1468 /* Map all the lowmem memory banks. */
1469 for_each_mem_range(i, &start, &end) {
1470 struct map_desc map;
1471
1472 if (end > arm_lowmem_limit)
1473 end = arm_lowmem_limit;
1474 if (start >= end)
1475 break;
1476
1477 if (end < kernel_x_start) {
1478 map.pfn = __phys_to_pfn(start);
1479 map.virtual = __phys_to_virt(start);
1480 map.length = end - start;
1481 map.type = MT_MEMORY_RWX;
1482
1483 create_mapping(&map);
1484 } else if (start >= kernel_x_end) {
1485 map.pfn = __phys_to_pfn(start);
1486 map.virtual = __phys_to_virt(start);
1487 map.length = end - start;
1488 map.type = MT_MEMORY_RW;
1489
1490 create_mapping(&map);
1491 } else {
1492 /* This better cover the entire kernel */
1493 if (start < kernel_x_start) {
1494 map.pfn = __phys_to_pfn(start);
1495 map.virtual = __phys_to_virt(start);
1496 map.length = kernel_x_start - start;
1497 map.type = MT_MEMORY_RW;
1498
1499 create_mapping(&map);
1500 }
1501
1502 map.pfn = __phys_to_pfn(kernel_x_start);
1503 map.virtual = __phys_to_virt(kernel_x_start);
1504 map.length = kernel_x_end - kernel_x_start;
1505 map.type = MT_MEMORY_RWX;
1506
1507 create_mapping(&map);
1508
1509 if (kernel_x_end < end) {
1510 map.pfn = __phys_to_pfn(kernel_x_end);
1511 map.virtual = __phys_to_virt(kernel_x_end);
1512 map.length = end - kernel_x_end;
1513 map.type = MT_MEMORY_RW;
1514
1515 create_mapping(&map);
1516 }
1517 }
1518 }
1519 }
1520
1521 #ifdef CONFIG_ARM_PV_FIXUP
1522 typedef void pgtables_remap(long long offset, unsigned long pgd);
1523 pgtables_remap lpae_pgtables_remap_asm;
1524
1525 /*
1526 * early_paging_init() recreates boot time page table setup, allowing machines
1527 * to switch over to a high (>4G) address space on LPAE systems
1528 */
early_paging_init(const struct machine_desc * mdesc)1529 static void __init early_paging_init(const struct machine_desc *mdesc)
1530 {
1531 pgtables_remap *lpae_pgtables_remap;
1532 unsigned long pa_pgd;
1533 unsigned int cr, ttbcr;
1534 long long offset;
1535
1536 if (!mdesc->pv_fixup)
1537 return;
1538
1539 offset = mdesc->pv_fixup();
1540 if (offset == 0)
1541 return;
1542
1543 /*
1544 * Get the address of the remap function in the 1:1 identity
1545 * mapping setup by the early page table assembly code. We
1546 * must get this prior to the pv update. The following barrier
1547 * ensures that this is complete before we fixup any P:V offsets.
1548 */
1549 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1550 pa_pgd = __pa(swapper_pg_dir);
1551 barrier();
1552
1553 pr_info("Switching physical address space to 0x%08llx\n",
1554 (u64)PHYS_OFFSET + offset);
1555
1556 /* Re-set the phys pfn offset, and the pv offset */
1557 __pv_offset += offset;
1558 __pv_phys_pfn_offset += PFN_DOWN(offset);
1559
1560 /* Run the patch stub to update the constants */
1561 fixup_pv_table(&__pv_table_begin,
1562 (&__pv_table_end - &__pv_table_begin) << 2);
1563
1564 /*
1565 * We changing not only the virtual to physical mapping, but also
1566 * the physical addresses used to access memory. We need to flush
1567 * all levels of cache in the system with caching disabled to
1568 * ensure that all data is written back, and nothing is prefetched
1569 * into the caches. We also need to prevent the TLB walkers
1570 * allocating into the caches too. Note that this is ARMv7 LPAE
1571 * specific.
1572 */
1573 cr = get_cr();
1574 set_cr(cr & ~(CR_I | CR_C));
1575 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1576 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1577 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1578 flush_cache_all();
1579
1580 /*
1581 * Fixup the page tables - this must be in the idmap region as
1582 * we need to disable the MMU to do this safely, and hence it
1583 * needs to be assembly. It's fairly simple, as we're using the
1584 * temporary tables setup by the initial assembly code.
1585 */
1586 lpae_pgtables_remap(offset, pa_pgd);
1587
1588 /* Re-enable the caches and cacheable TLB walks */
1589 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1590 set_cr(cr);
1591 }
1592
1593 #else
1594
early_paging_init(const struct machine_desc * mdesc)1595 static void __init early_paging_init(const struct machine_desc *mdesc)
1596 {
1597 long long offset;
1598
1599 if (!mdesc->pv_fixup)
1600 return;
1601
1602 offset = mdesc->pv_fixup();
1603 if (offset == 0)
1604 return;
1605
1606 pr_crit("Physical address space modification is only to support Keystone2.\n");
1607 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1608 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1609 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1610 }
1611
1612 #endif
1613
early_fixmap_shutdown(void)1614 static void __init early_fixmap_shutdown(void)
1615 {
1616 int i;
1617 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1618
1619 pte_offset_fixmap = pte_offset_late_fixmap;
1620 pmd_clear(fixmap_pmd(va));
1621 local_flush_tlb_kernel_page(va);
1622
1623 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1624 pte_t *pte;
1625 struct map_desc map;
1626
1627 map.virtual = fix_to_virt(i);
1628 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1629
1630 /* Only i/o device mappings are supported ATM */
1631 if (pte_none(*pte) ||
1632 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1633 continue;
1634
1635 map.pfn = pte_pfn(*pte);
1636 map.type = MT_DEVICE;
1637 map.length = PAGE_SIZE;
1638
1639 create_mapping(&map);
1640 }
1641 }
1642
1643 /*
1644 * paging_init() sets up the page tables, initialises the zone memory
1645 * maps, and sets up the zero page, bad page and bad page tables.
1646 */
paging_init(const struct machine_desc * mdesc)1647 void __init paging_init(const struct machine_desc *mdesc)
1648 {
1649 void *zero_page;
1650
1651 prepare_page_table();
1652 map_lowmem();
1653 memblock_set_current_limit(arm_lowmem_limit);
1654 dma_contiguous_remap();
1655 early_fixmap_shutdown();
1656 devicemaps_init(mdesc);
1657 kmap_init();
1658 tcm_init();
1659
1660 top_pmd = pmd_off_k(0xffff0000);
1661
1662 /* allocate the zero page. */
1663 zero_page = early_alloc(PAGE_SIZE);
1664
1665 bootmem_init();
1666
1667 empty_zero_page = virt_to_page(zero_page);
1668 __flush_dcache_page(NULL, empty_zero_page);
1669 }
1670
early_mm_init(const struct machine_desc * mdesc)1671 void __init early_mm_init(const struct machine_desc *mdesc)
1672 {
1673 build_mem_type_table();
1674 early_paging_init(mdesc);
1675 }
1676
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pteval)1677 void set_pte_at(struct mm_struct *mm, unsigned long addr,
1678 pte_t *ptep, pte_t pteval)
1679 {
1680 unsigned long ext = 0;
1681
1682 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1683 if (!pte_special(pteval))
1684 __sync_icache_dcache(pteval);
1685 ext |= PTE_EXT_NG;
1686 }
1687
1688 set_pte_ext(ptep, pteval, ext);
1689 }
1690