1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 imply PANIC_HANG 11 12config ARCH_LS1043A 13 bool 14 select ARMV8_SET_SMPEN 15 select FSL_LSCH2 16 select SYS_FSL_DDR 17 select SYS_FSL_DDR_BE 18 select SYS_FSL_DDR_VER_50 19 select SYS_FSL_ERRATUM_A008850 20 select SYS_FSL_ERRATUM_A009660 21 select SYS_FSL_ERRATUM_A009663 22 select SYS_FSL_ERRATUM_A009929 23 select SYS_FSL_ERRATUM_A009942 24 select SYS_FSL_ERRATUM_A010315 25 select SYS_FSL_ERRATUM_A010539 26 select SYS_FSL_HAS_DDR3 27 select SYS_FSL_HAS_DDR4 28 select ARCH_EARLY_INIT_R 29 select BOARD_EARLY_INIT_F 30 imply SCSI 31 imply CMD_PCI 32 33config ARCH_LS1046A 34 bool 35 select ARMV8_SET_SMPEN 36 select FSL_LSCH2 37 select SYS_FSL_DDR 38 select SYS_FSL_DDR_BE 39 select SYS_FSL_DDR_VER_50 40 select SYS_FSL_ERRATUM_A008336 41 select SYS_FSL_ERRATUM_A008511 42 select SYS_FSL_ERRATUM_A008850 43 select SYS_FSL_ERRATUM_A009801 44 select SYS_FSL_ERRATUM_A009803 45 select SYS_FSL_ERRATUM_A009942 46 select SYS_FSL_ERRATUM_A010165 47 select SYS_FSL_ERRATUM_A010539 48 select SYS_FSL_HAS_DDR4 49 select SYS_FSL_SRDS_2 50 select ARCH_EARLY_INIT_R 51 select BOARD_EARLY_INIT_F 52 imply SCSI 53 54config ARCH_LS2080A 55 bool 56 select ARMV8_SET_SMPEN 57 select ARM_ERRATA_826974 58 select ARM_ERRATA_828024 59 select ARM_ERRATA_829520 60 select ARM_ERRATA_833471 61 select FSL_LSCH3 62 select SYS_FSL_DDR 63 select SYS_FSL_DDR_LE 64 select SYS_FSL_DDR_VER_50 65 select SYS_FSL_HAS_DP_DDR 66 select SYS_FSL_HAS_SEC 67 select SYS_FSL_HAS_DDR4 68 select SYS_FSL_SEC_COMPAT_5 69 select SYS_FSL_SEC_LE 70 select SYS_FSL_SRDS_2 71 select FSL_TZASC_1 72 select FSL_TZASC_2 73 select SYS_FSL_ERRATUM_A008336 74 select SYS_FSL_ERRATUM_A008511 75 select SYS_FSL_ERRATUM_A008514 76 select SYS_FSL_ERRATUM_A008585 77 select SYS_FSL_ERRATUM_A009635 78 select SYS_FSL_ERRATUM_A009663 79 select SYS_FSL_ERRATUM_A009801 80 select SYS_FSL_ERRATUM_A009803 81 select SYS_FSL_ERRATUM_A009942 82 select SYS_FSL_ERRATUM_A010165 83 select SYS_FSL_ERRATUM_A009203 84 select ARCH_EARLY_INIT_R 85 select BOARD_EARLY_INIT_F 86 imply PANIC_HANG 87 88config FSL_LSCH2 89 bool 90 select SYS_FSL_HAS_SEC 91 select SYS_FSL_SEC_COMPAT_5 92 select SYS_FSL_SEC_BE 93 select SYS_FSL_SRDS_1 94 select SYS_HAS_SERDES 95 96config FSL_LSCH3 97 bool 98 select SYS_FSL_SRDS_1 99 select SYS_HAS_SERDES 100 101config FSL_MC_ENET 102 bool "Management Complex network" 103 depends on ARCH_LS2080A 104 default y 105 select RESV_RAM 106 help 107 Enable Management Complex (MC) network 108 109menu "Layerscape architecture" 110 depends on FSL_LSCH2 || FSL_LSCH3 111 112config FSL_PCIE_COMPAT 113 string "PCIe compatible of Kernel DT" 114 depends on PCIE_LAYERSCAPE 115 default "fsl,ls1012a-pcie" if ARCH_LS1012A 116 default "fsl,ls1043a-pcie" if ARCH_LS1043A 117 default "fsl,ls1046a-pcie" if ARCH_LS1046A 118 default "fsl,ls2080a-pcie" if ARCH_LS2080A 119 help 120 This compatible is used to find pci controller node in Kernel DT 121 to complete fixup. 122 123config HAS_FEATURE_GIC64K_ALIGN 124 bool 125 default y if ARCH_LS1043A 126 127config HAS_FEATURE_ENHANCED_MSI 128 bool 129 default y if ARCH_LS1043A 130 131menu "Layerscape PPA" 132config FSL_LS_PPA 133 bool "FSL Layerscape PPA firmware support" 134 depends on !ARMV8_PSCI 135 select ARMV8_SEC_FIRMWARE_SUPPORT 136 select SEC_FIRMWARE_ARMV8_PSCI 137 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 138 help 139 The FSL Primary Protected Application (PPA) is a software component 140 which is loaded during boot stage, and then remains resident in RAM 141 and runs in the TrustZone after boot. 142 Say y to enable it. 143 144config SPL_FSL_LS_PPA 145 bool "FSL Layerscape PPA firmware support for SPL build" 146 depends on !ARMV8_PSCI 147 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 148 select SEC_FIRMWARE_ARMV8_PSCI 149 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 150 help 151 The FSL Primary Protected Application (PPA) is a software component 152 which is loaded during boot stage, and then remains resident in RAM 153 and runs in the TrustZone after boot. This is to load PPA during SPL 154 stage instead of the RAM version of U-Boot. Once PPA is initialized, 155 the rest of U-Boot (including RAM version) runs at EL2. 156choice 157 prompt "FSL Layerscape PPA firmware loading-media select" 158 depends on FSL_LS_PPA 159 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 160 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 161 default SYS_LS_PPA_FW_IN_XIP 162 163config SYS_LS_PPA_FW_IN_XIP 164 bool "XIP" 165 help 166 Say Y here if the PPA firmware locate at XIP flash, such 167 as NOR or QSPI flash. 168 169config SYS_LS_PPA_FW_IN_MMC 170 bool "eMMC or SD Card" 171 help 172 Say Y here if the PPA firmware locate at eMMC/SD card. 173 174config SYS_LS_PPA_FW_IN_NAND 175 bool "NAND" 176 help 177 Say Y here if the PPA firmware locate at NAND flash. 178 179endchoice 180 181config SYS_LS_PPA_FW_ADDR 182 hex "Address of PPA firmware loading from" 183 depends on FSL_LS_PPA 184 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 185 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 186 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 187 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 188 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 189 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 190 191 help 192 If the PPA firmware locate at XIP flash, such as NOR or 193 QSPI flash, this address is a directly memory-mapped. 194 If it is in a serial accessed flash, such as NAND and SD 195 card, it is a byte offset. 196 197config SYS_LS_PPA_ESBC_ADDR 198 hex "hdr address of PPA firmware loading from" 199 depends on FSL_LS_PPA && CHAIN_OF_TRUST 200 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 201 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 202 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 203 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 204 default 0x700000 if SYS_LS_PPA_FW_IN_MMC 205 default 0x700000 if SYS_LS_PPA_FW_IN_NAND 206 help 207 If the PPA header firmware locate at XIP flash, such as NOR or 208 QSPI flash, this address is a directly memory-mapped. 209 If it is in a serial accessed flash, such as NAND and SD 210 card, it is a byte offset. 211 212config LS_PPA_ESBC_HDR_SIZE 213 hex "Length of PPA ESBC header" 214 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 215 default 0x2000 216 help 217 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 218 NAND to memory to validate PPA image. 219 220endmenu 221 222config SYS_FSL_ERRATUM_A010315 223 bool "Workaround for PCIe erratum A010315" 224 225config SYS_FSL_ERRATUM_A010539 226 bool "Workaround for PIN MUX erratum A010539" 227 228config MAX_CPUS 229 int "Maximum number of CPUs permitted for Layerscape" 230 default 4 if ARCH_LS1043A 231 default 4 if ARCH_LS1046A 232 default 16 if ARCH_LS2080A 233 default 1 234 help 235 Set this number to the maximum number of possible CPUs in the SoC. 236 SoCs may have multiple clusters with each cluster may have multiple 237 ports. If some ports are reserved but higher ports are used for 238 cores, count the reserved ports. This will allocate enough memory 239 in spin table to properly handle all cores. 240 241config SECURE_BOOT 242 bool "Secure Boot" 243 help 244 Enable Freescale Secure Boot feature 245 246config QSPI_AHB_INIT 247 bool "Init the QSPI AHB bus" 248 help 249 The default setting for QSPI AHB bus just support 3bytes addressing. 250 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 251 bus for those flashes to support the full QSPI flash size. 252 253config SYS_FSL_IFC_BANK_COUNT 254 int "Maximum banks of Integrated flash controller" 255 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 256 default 4 if ARCH_LS1043A 257 default 4 if ARCH_LS1046A 258 default 8 if ARCH_LS2080A 259 260config SYS_FSL_HAS_DP_DDR 261 bool 262 263config SYS_FSL_SRDS_1 264 bool 265 266config SYS_FSL_SRDS_2 267 bool 268 269config SYS_HAS_SERDES 270 bool 271 272config FSL_TZASC_1 273 bool 274 275config FSL_TZASC_2 276 bool 277 278endmenu 279 280menu "Layerscape clock tree configuration" 281 depends on FSL_LSCH2 || FSL_LSCH3 282 283config SYS_FSL_CLK 284 bool "Enable clock tree initialization" 285 default y 286 287config CLUSTER_CLK_FREQ 288 int "Reference clock of core cluster" 289 depends on ARCH_LS1012A 290 default 100000000 291 help 292 This number is the reference clock frequency of core PLL. 293 For most platforms, the core PLL and Platform PLL have the same 294 reference clock, but for some platforms, LS1012A for instance, 295 they are provided sepatately. 296 297config SYS_FSL_PCLK_DIV 298 int "Platform clock divider" 299 default 1 if ARCH_LS1043A 300 default 1 if ARCH_LS1046A 301 default 2 302 help 303 This is the divider that is used to derive Platform clock from 304 Platform PLL, in another word: 305 Platform_clk = Platform_PLL_freq / this_divider 306 307config SYS_FSL_DSPI_CLK_DIV 308 int "DSPI clock divider" 309 default 1 if ARCH_LS1043A 310 default 2 311 help 312 This is the divider that is used to derive DSPI clock from Platform 313 clock, in another word DSPI_clk = Platform_clk / this_divider. 314 315config SYS_FSL_DUART_CLK_DIV 316 int "DUART clock divider" 317 default 1 if ARCH_LS1043A 318 default 2 319 help 320 This is the divider that is used to derive DUART clock from Platform 321 clock, in another word DUART_clk = Platform_clk / this_divider. 322 323config SYS_FSL_I2C_CLK_DIV 324 int "I2C clock divider" 325 default 1 if ARCH_LS1043A 326 default 2 327 help 328 This is the divider that is used to derive I2C clock from Platform 329 clock, in another word I2C_clk = Platform_clk / this_divider. 330 331config SYS_FSL_IFC_CLK_DIV 332 int "IFC clock divider" 333 default 1 if ARCH_LS1043A 334 default 2 335 help 336 This is the divider that is used to derive IFC clock from Platform 337 clock, in another word IFC_clk = Platform_clk / this_divider. 338 339config SYS_FSL_LPUART_CLK_DIV 340 int "LPUART clock divider" 341 default 1 if ARCH_LS1043A 342 default 2 343 help 344 This is the divider that is used to derive LPUART clock from Platform 345 clock, in another word LPUART_clk = Platform_clk / this_divider. 346 347config SYS_FSL_SDHC_CLK_DIV 348 int "SDHC clock divider" 349 default 1 if ARCH_LS1043A 350 default 1 if ARCH_LS1012A 351 default 2 352 help 353 This is the divider that is used to derive SDHC clock from Platform 354 clock, in another word SDHC_clk = Platform_clk / this_divider. 355endmenu 356 357config RESV_RAM 358 bool 359 help 360 Reserve memory from the top, tracked by gd->arch.resv_ram. This 361 reserved RAM can be used by special driver that resides in memory 362 after U-Boot exits. It's up to implementation to allocate and allow 363 access to this reserved memory. For example, the reserved RAM can 364 be at the high end of physical memory. The reserve RAM may be 365 excluded from memory bank(s) passed to OS, or marked as reserved. 366 367config SYS_FSL_ERRATUM_A008336 368 bool 369 370config SYS_FSL_ERRATUM_A008514 371 bool 372 373config SYS_FSL_ERRATUM_A008585 374 bool 375 376config SYS_FSL_ERRATUM_A008850 377 bool 378 379config SYS_FSL_ERRATUM_A009203 380 bool 381 382config SYS_FSL_ERRATUM_A009635 383 bool 384 385config SYS_FSL_ERRATUM_A009660 386 bool 387 388config SYS_FSL_ERRATUM_A009929 389 bool 390 391config SYS_MC_RSV_MEM_ALIGN 392 hex "Management Complex reserved memory alignment" 393 depends on RESV_RAM 394 default 0x20000000 395 help 396 Reserved memory needs to be aligned for MC to use. Default value 397 is 512MB. 398 399config SPL_LDSCRIPT 400 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 401