1/dts-v1/; 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/pwm/pwm.h> 5#include <dt-bindings/input/rk-input.h> 6#include <dt-bindings/display/drm_mipi_dsi.h> 7#include <dt-bindings/display/rockchip_vop.h> 8#include <dt-bindings/display/media-bus-format.h> 9#include "rk3568.dtsi" 10 11 12/ { 13 14 model = "Forlinx OK3568-C Board"; 15 compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; 16 17 forlinx_control { 18 status = "disabled"; 19 video-hdmi = "hdmi"; 20 video-mipi-edp = "mipi"; 21 video-lvds-rgb = "lvds"; 22 }; 23 24 edp-panel { 25 compatible = "simple-panel"; 26 prepare-delay-ms = <120>; 27 enable-delay-ms = <120>; 28 unprepare-delay-ms = <120>; 29 disable-delay-ms = <120>; 30 backlight = <&edp_backlight>; 31 enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 32 33 port { 34 panel_in_edp: endpoint { 35 remote-endpoint = <&edp_out_panel>; 36 }; 37 }; 38 }; 39 40 panel { 41 compatible = "simple-panel"; 42 backlight = <&lvds_backlight>; 43 power-supply = <&vcc3v3_lcd2_n>; 44 enable-delay-ms = <20>; 45 prepare-delay-ms = <20>; 46 unprepare-delay-ms = <20>; 47 disable-delay-ms = <20>; 48 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 49 width-mm = <152>; 50 height-mm = <91>; 51 52 display-timings { 53 native-mode = <&timing0>; 54 55 timing0: timing0 { 56 clock-frequency = <71000000>; 57 hactive = <1280>; 58 vactive = <800>; 59 hback-porch = <10>; 60 hfront-porch = <140>; 61 vback-porch = <1>; 62 vfront-porch = <2>; 63 hsync-len = <10>; 64 vsync-len = <20>; 65 hsync-active = <0>; 66 vsync-active = <1>; 67 de-active = <1>; 68 pixelclk-active = <0>; 69 }; 70 }; 71 72 ports { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 port@0 { 77 reg = <0>; 78 dual-lvds-even-pixels; 79 panel_in_lvds: endpoint { 80 remote-endpoint = <&lvds_out_panel>; 81 }; 82 }; 83 }; 84 }; 85 86 rgb-panel { 87 compatible = "simple-panel"; 88 backlight = <&lvds_backlight>; 89 power-supply = <&vcc3v3_lcd2_n>; 90 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 91 92 display-timings { 93 native-mode = <&timing1>; 94 95 timing1: timing1 { 96 clock-frequency = <51200000>; 97 hactive = <1024>; 98 vactive = <600>; 99 hfront-porch = <160>; 100 hback-porch = <320>; 101 hsync-len = <1>; 102 vback-porch = <35>; 103 vfront-porch = <12>; 104 vsync-len = <1>; 105 hsync-active = <0>; 106 vsync-active = <0>; 107 de-active = <1>; 108 pixelclk-active = <1>; 109 }; 110 }; 111 112 ports { 113 #address-cells = <1>; 114 #size-cells = <0>; 115 116 port@0 { 117 reg = <0>; 118 panel_in_rgb: endpoint { 119 remote-endpoint = <&rgb_out_panel>; 120 }; 121 }; 122 123 }; 124 }; 125 126 adc_keys: adc-keys { 127 compatible = "adc-keys"; 128 io-channels = <&saradc 0>; 129 io-channel-names = "buttons"; 130 keyup-threshold-microvolt = <1800000>; 131 poll-interval = <100>; 132 133 vol-up-key { 134 label = "volume up"; 135 linux,code = <KEY_VOLUMEUP>; 136 press-threshold-microvolt = <1750>; 137 }; 138 139 vol-down-key { 140 label = "volume down"; 141 linux,code = <KEY_VOLUMEDOWN>; 142 press-threshold-microvolt = <297500>; 143 }; 144 145 menu-key { 146 label = "menu"; 147 linux,code = <KEY_MENU>; 148 press-threshold-microvolt = <980000>; 149 }; 150 151 back-key { 152 label = "back"; 153 linux,code = <KEY_BACK>; 154 press-threshold-microvolt = <1305500>; 155 }; 156 }; 157 158 leds: leds { 159 compatible = "gpio-leds"; 160 work_led: work { 161 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 162 linux,default-trigger = "heartbeat"; 163 }; 164 }; 165 166 hdmi_sound: hdmi-sound { 167 status = "okay"; 168 compatible = "rockchip,hdmi"; 169 rockchip,mclk-fs = <128>; 170 rockchip,card-name = "rockchip,hdmi"; 171 rockchip,cpu = <&i2s0_8ch>; 172 rockchip,codec = <&hdmi>; 173 rockchip,jack-det; 174 }; 175 176 pdmics: dummy-codec { 177 status = "disabled"; 178 compatible = "rockchip,dummy-codec"; 179 #sound-dai-cells = <0>; 180 }; 181 182 pdm_mic_array: pdm-mic-array { 183 status = "disabled"; 184 compatible = "simple-audio-card"; 185 simple-audio-card,name = "rockchip,pdm-mic-array"; 186 simple-audio-card,cpu { 187 sound-dai = <&pdm>; 188 }; 189 simple-audio-card,codec { 190 sound-dai = <&pdmics>; 191 }; 192 }; 193 194 audiopwmout_diff: audiopwmout-diff { 195 status = "disabled"; 196 compatible = "simple-audio-card"; 197 simple-audio-card,format = "i2s"; 198 simple-audio-card,name = "rockchip,audiopwmout-diff"; 199 simple-audio-card,mclk-fs = <256>; 200 simple-audio-card,bitclock-master = <&master>; 201 simple-audio-card,frame-master = <&master>; 202 simple-audio-card,cpu { 203 sound-dai = <&i2s3_2ch>; 204 }; 205 master: simple-audio-card,codec { 206 sound-dai = <&dig_acodec>; 207 }; 208 }; 209 210 211 rk809_sound: rk809-sound { 212 status = "okay"; 213 compatible = "rockchip,multicodecs-card"; 214 rockchip,card-name = "rockchip-rk809"; 215 hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; 216 rockchip,format = "i2s"; 217 rockchip,mclk-fs = <256>; 218 rockchip,cpu = <&i2s1_8ch>; 219 rockchip,codec = <&rk809_codec>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&hp_det>; 222 223 }; 224 225 spdif-sound { 226 status = "disabled"; 227 compatible = "simple-audio-card"; 228 simple-audio-card,name = "ROCKCHIP,SPDIF"; 229 simple-audio-card,cpu { 230 sound-dai = <&spdif_8ch>; 231 }; 232 simple-audio-card,codec { 233 sound-dai = <&spdif_out>; 234 }; 235 }; 236 237 spdif_out: spdif-out { 238 status = "disabled"; 239 compatible = "linux,spdif-dit"; 240 #sound-dai-cells = <0>; 241 }; 242 243 vcc12v: vcc-12v { 244 compatible = "regulator-fixed"; 245 regulator-name = "vcc12v"; 246 regulator-always-on; 247 regulator-boot-on; 248 regulator-min-microvolt = <12000000>; 249 regulator-max-microvolt = <12000000>; 250 }; 251 252 vcc5v0_sys: vcc5v0-sys { 253 compatible = "regulator-fixed"; 254 regulator-name = "vcc5v0_sys"; 255 regulator-always-on; 256 regulator-boot-on; 257 regulator-min-microvolt = <5000000>; 258 regulator-max-microvolt = <5000000>; 259 vin-supply = <&vcc12v>; 260 }; 261 262 vcc3v3_sys: vcc3v3-sys { 263 compatible = "regulator-fixed"; 264 regulator-name = "vcc3v3_sys"; 265 regulator-always-on; 266 regulator-boot-on; 267 regulator-min-microvolt = <3300000>; 268 regulator-max-microvolt = <3300000>; 269 vin-supply = <&vcc5v0_sys>; 270 }; 271 vcc3v3_pcie: vcc3v3-pcie { 272 compatible = "regulator-gpio"; 273 regulator-name = "vcc3v3_pcie"; 274 regulator-min-microvolt = <100000>; 275 regulator-max-microvolt = <3300000>; 276 gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 277 gpios-states = <0x1>; 278 states = <100000 0x0 279 3300000 0x1>; 280 }; 281 282 //for main board 283 vcc3v3: vcc-3v3 { 284 compatible = "regulator-fixed"; 285 regulator-name = "vcc3v3"; 286 regulator-always-on; 287 regulator-boot-on; 288 regulator-min-microvolt = <3300000>; 289 regulator-max-microvolt = <3300000>; 290 vin-supply = <&vcc5v0_sys>; 291 }; 292 293 vcc1v8: vcc-1v8 { 294 compatible = "regulator-fixed"; 295 regulator-name = "vcc1v8"; 296 regulator-always-on; 297 regulator-boot-on; 298 regulator-min-microvolt = <1800000>; 299 regulator-max-microvolt = <1800000>; 300 vin-supply = <&vcc3v3>; 301 }; 302 303 vcc1v2: vcc-1v2 { 304 compatible = "regulator-fixed"; 305 regulator-name = "vcc1v2"; 306 regulator-always-on; 307 regulator-boot-on; 308 regulator-min-microvolt = <1200000>; 309 regulator-max-microvolt = <1200000>; 310 vin-supply = <&vcc3v3>; 311 }; 312 313 vcc2v8: vcc-2v8 { 314 compatible = "regulator-fixed"; 315 regulator-name = "vcc2v8"; 316 regulator-always-on; 317 regulator-boot-on; 318 regulator-min-microvolt = <2800000>; 319 regulator-max-microvolt = <2800000>; 320 vin-supply = <&vcc3v3>; 321 }; 322 323 vcc3v3_lcd2_n: vcc3v3-lcd2-n { 324 compatible = "regulator-fixed"; 325 regulator-name = "vcc3v3_lcd2_n"; 326 regulator-boot-on; 327 regulator-min-microvolt = <3300000>; 328 regulator-max-microvolt = <3300000>; 329 enable-active-high; 330 gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 331 vin-supply = <&vcc3v3_sys>; 332 333 regulator-state-mem { 334 regulator-off-in-suspend; 335 }; 336 }; 337 338 sdio_pwrseq: sdio-pwrseq { 339 compatible = "mmc-pwrseq-simple"; 340 clocks = <&rk809 1>; 341 clock-names = "ext_clock"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&wifi_enable_h>; 344 345 /* 346 * On the module itself this is one of these (depending 347 * on the actual card populated): 348 * - SDIO_RESET_L_WL_REG_ON 349 * - PDN (power down when low) 350 */ 351 post-power-on-delay-ms = <200>; 352 reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; 353 }; 354 355 vcc2v5_sys: vcc2v5-ddr { 356 compatible = "regulator-fixed"; 357 regulator-name = "vcc2v5-sys"; 358 regulator-always-on; 359 regulator-boot-on; 360 regulator-min-microvolt = <2500000>; 361 regulator-max-microvolt = <2500000>; 362 vin-supply = <&vcc3v3_sys>; 363 }; 364 365 5g-rst { 366 compatible = "regulator-fixed"; 367 regulator-name = "5g-rst"; 368 regulator-min-microvolt = <3300000>; 369 regulator-max-microvolt = <3300000>; 370 gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; 371 enable-active-low; 372 regulator-boot-on; 373 regulator-always-on; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&net_5g_rst_gpio>; 376 status = "okay"; 377 }; 378 379 5g-pwr { 380 compatible = "regulator-fixed"; 381 regulator-name = "5g-pwr"; 382 regulator-min-microvolt = <3300000>; 383 regulator-max-microvolt = <3300000>; 384 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 385 enable-active-high; 386 regulator-boot-on; 387 regulator-always-on; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&net_5g_pwr_gpio>; 390 status = "okay"; 391 }; 392 393 fiq-debugger { 394 compatible = "rockchip,fiq-debugger"; 395 rockchip,serial-id = <2>; 396 rockchip,wake-irq = <0>; 397 /* If enable uart uses irq instead of fiq */ 398 rockchip,irq-mode-enable = <1>; 399 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 400 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&uart2m0_xfer>; 403 status = "okay"; 404 }; 405 406 debug: debug@fd904000 { 407 compatible = "rockchip,debug"; 408 reg = <0x0 0xfd904000 0x0 0x1000>, 409 <0x0 0xfd905000 0x0 0x1000>, 410 <0x0 0xfd906000 0x0 0x1000>, 411 <0x0 0xfd907000 0x0 0x1000>; 412 }; 413 414 cspmu: cspmu@fd90c000 { 415 compatible = "rockchip,cspmu"; 416 reg = <0x0 0xfd90c000 0x0 0x1000>, 417 <0x0 0xfd90d000 0x0 0x1000>, 418 <0x0 0xfd90e000 0x0 0x1000>, 419 <0x0 0xfd90f000 0x0 0x1000>; 420 }; 421 422 test-power { 423 status = "okay"; 424 }; 425 dsi1_backlight: dsi1-backlight { 426 compatible = "pwm-backlight"; 427 pwms = <&pwm5 0 20000 0>; 428 brightness-levels = < 429 0 20 20 21 21 22 22 23 430 23 24 24 25 25 26 26 27 431 27 28 28 29 29 30 30 31 432 31 32 32 33 33 34 34 35 433 35 36 36 37 37 38 38 39 434 40 41 42 43 44 45 46 47 435 48 49 50 51 52 53 54 55 436 56 57 58 59 60 61 62 63 437 64 65 66 67 68 69 70 71 438 72 73 74 75 76 77 78 79 439 80 81 82 83 84 85 86 87 440 88 89 90 91 92 93 94 95 441 96 97 98 99 100 101 102 103 442 104 105 106 107 108 109 110 111 443 112 113 114 115 116 117 118 119 444 120 121 122 123 124 125 126 127 445 128 129 130 131 132 133 134 135 446 136 137 138 139 140 141 142 143 447 144 145 146 147 148 149 150 151 448 152 153 154 155 156 157 158 159 449 160 161 162 163 164 165 166 167 450 168 169 170 171 172 173 174 175 451 176 177 178 179 180 181 182 183 452 184 185 186 187 188 189 190 191 453 192 193 194 195 196 197 198 199 454 200 201 202 203 204 205 206 207 455 208 209 210 211 212 213 214 215 456 216 217 218 219 220 221 222 223 457 224 225 226 227 228 229 230 231 458 232 233 234 235 236 237 238 239 459 240 241 242 243 244 245 246 247 460 248 249 250 251 252 253 254 255 461 >; 462 default-brightness-level = <200>; 463 is-forlinx; 464 }; 465 466 lvds_backlight: lvds-backlight { 467 compatible = "pwm-backlight"; 468 pwms = <&pwm14 0 20000 0>; 469 brightness-levels = < 470 0 20 20 21 21 22 22 23 471 23 24 24 25 25 26 26 27 472 27 28 28 29 29 30 30 31 473 31 32 32 33 33 34 34 35 474 35 36 36 37 37 38 38 39 475 40 41 42 43 44 45 46 47 476 48 49 50 51 52 53 54 55 477 56 57 58 59 60 61 62 63 478 64 65 66 67 68 69 70 71 479 72 73 74 75 76 77 78 79 480 80 81 82 83 84 85 86 87 481 88 89 90 91 92 93 94 95 482 96 97 98 99 100 101 102 103 483 104 105 106 107 108 109 110 111 484 112 113 114 115 116 117 118 119 485 120 121 122 123 124 125 126 127 486 128 129 130 131 132 133 134 135 487 136 137 138 139 140 141 142 143 488 144 145 146 147 148 149 150 151 489 152 153 154 155 156 157 158 159 490 160 161 162 163 164 165 166 167 491 168 169 170 171 172 173 174 175 492 176 177 178 179 180 181 182 183 493 184 185 186 187 188 189 190 191 494 192 193 194 195 196 197 198 199 495 200 201 202 203 204 205 206 207 496 208 209 210 211 212 213 214 215 497 216 217 218 219 220 221 222 223 498 224 225 226 227 228 229 230 231 499 232 233 234 235 236 237 238 239 500 240 241 242 243 244 245 246 247 501 248 249 250 251 252 253 254 255 502 >; 503 default-brightness-level = <200>; 504 is-forlinx; 505 }; 506 507 edp_backlight: edp-backlight { 508 compatible = "pwm-backlight"; 509 pwms = <&pwm3 0 20000 0>; 510 brightness-levels = < 511 0 20 20 21 21 22 22 23 512 23 24 24 25 25 26 26 27 513 27 28 28 29 29 30 30 31 514 31 32 32 33 33 34 34 35 515 35 36 36 37 37 38 38 39 516 40 41 42 43 44 45 46 47 517 48 49 50 51 52 53 54 55 518 56 57 58 59 60 61 62 63 519 64 65 66 67 68 69 70 71 520 72 73 74 75 76 77 78 79 521 80 81 82 83 84 85 86 87 522 88 89 90 91 92 93 94 95 523 96 97 98 99 100 101 102 103 524 104 105 106 107 108 109 110 111 525 112 113 114 115 116 117 118 119 526 120 121 122 123 124 125 126 127 527 128 129 130 131 132 133 134 135 528 136 137 138 139 140 141 142 143 529 144 145 146 147 148 149 150 151 530 152 153 154 155 156 157 158 159 531 160 161 162 163 164 165 166 167 532 168 169 170 171 172 173 174 175 533 176 177 178 179 180 181 182 183 534 184 185 186 187 188 189 190 191 535 192 193 194 195 196 197 198 199 536 200 201 202 203 204 205 206 207 537 208 209 210 211 212 213 214 215 538 216 217 218 219 220 221 222 223 539 224 225 226 227 228 229 230 231 540 232 233 234 235 236 237 238 239 541 240 241 242 243 244 245 246 247 542 248 249 250 251 252 253 254 255 543 >; 544 default-brightness-level = <200>; 545 }; 546}; 547 548&reserved_memory { 549 ramoops: ramoops@110000 { 550 compatible = "ramoops"; 551 reg = <0x0 0x110000 0x0 0xf0000>; 552 record-size = <0x20000>; 553 console-size = <0x80000>; 554 ftrace-size = <0x00000>; 555 pmsg-size = <0x50000>; 556 }; 557}; 558 559&rng { 560 status = "okay"; 561}; 562 563&rockchip_suspend { 564 status = "okay"; 565}; 566 567&combphy0_us { 568 status = "okay"; 569}; 570 571&combphy1_usq { 572 status = "okay"; 573}; 574 575&combphy2_psq { 576 status = "okay"; 577}; 578 579&csi2_dphy_hw { 580 status = "okay"; 581}; 582 583&csi2_dphy0 { 584 status = "okay"; 585 586 ports { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 port@0 { 590 reg = <0>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 mipi_in_ov13850: endpoint@1 { 595 reg = <1>; 596 remote-endpoint = <&ov13850_out>; 597 data-lanes = <1 2>; 598 }; 599 }; 600 port@1 { 601 reg = <1>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 605 csidphy_out: endpoint@0 { 606 reg = <0>; 607 remote-endpoint = <&isp0_in>; 608 }; 609 }; 610 }; 611}; 612 613&gmac0 { 614 phy-mode = "rgmii-rxid"; 615 clock_in_out = "output"; 616 617 snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 618 snps,reset-active-low; 619 /* Reset time is 20ms, 100ms for rtl8211f */ 620 snps,reset-delays-us = <0 20000 100000>; 621 622 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; 623 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 624 assigned-clock-rates = <0>, <125000000>, <25000000>; 625 626 pinctrl-names = "default"; 627 pinctrl-0 = <&gmac0_miim 628 &gmac0_tx_bus2 629 &gmac0_rx_bus2 630 &gmac0_rgmii_clk 631 &gmac0_rgmii_bus 632 ð0_pins>; 633 634 tx_delay = <0x36>; 635/* rx_delay = <0x00>; */ 636 637 phy-handle = <&rgmii_phy0>; 638 status = "okay"; 639}; 640 641&gmac1 { 642 phy-mode = "rgmii-rxid"; 643 clock_in_out = "output"; 644 645 snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; 646 snps,reset-active-low; 647 /* Reset time is 20ms, 100ms for rtl8211f */ 648 snps,reset-delays-us = <0 20000 100000>; 649 650 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; 651 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 652 assigned-clock-rates = <0>, <125000000>, <25000000>; 653 654 pinctrl-names = "default"; 655 pinctrl-0 = <&gmac1m1_miim 656 &gmac1m1_tx_bus2 657 &gmac1m1_rx_bus2 658 &gmac1m1_rgmii_clk 659 &gmac1m1_rgmii_bus 660 ð1m1_pins>; 661 662 tx_delay = <0x47>; 663/* rx_delay = <0x00>; */ 664 665 phy-handle = <&rgmii_phy1>; 666 status = "okay"; 667}; 668 669&mdio0 { 670 rgmii_phy0: phy@0 { 671 compatible = "ethernet-phy-ieee802.3-c22"; 672 reg = <0x0>; 673 clocks = <&cru CLK_MAC0_OUT>; 674 }; 675}; 676 677&mdio1 { 678 rgmii_phy1: phy@0 { 679 compatible = "ethernet-phy-ieee802.3-c22"; 680 reg = <0x0>; 681 clocks = <&cru CLK_MAC1_OUT>; 682 }; 683}; 684 685&video_phy0 { 686 status = "okay"; 687}; 688 689&video_phy1 { 690 status = "okay"; 691}; 692 693&pcie30phy { 694 status = "okay"; 695}; 696 697&pcie3x2 { 698 reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 699/* enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; */ 700 vpcie3v3-supply = <&vcc3v3_pcie>; 701 status = "okay"; 702}; 703 704&pcie2x1 { 705 reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 706 status = "okay"; 707}; 708 709&pinctrl { 710 touch { 711 touch_gpio: touch-gpio { 712 rockchip,pins = 713 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, 714 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 715 }; 716 717 rgb_touch_gpio: rgb-touch-gpio { 718 rockchip,pins = 719 <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, 720 <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 721 }; 722 723 ft5x06_int: ft5x06-int { 724 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, 725 <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 726 }; 727 728 dsi_gt911_int: dsi-gt911-int { 729 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, 730 <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 731 }; 732 }; 733 734 cam { 735 camera_pwr: camera-pwr { 736 rockchip,pins = 737 /* camera power en */ 738 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 739 }; 740 741 ov13850_default_pin: ov13850-default-pin { 742 rockchip,pins = 743 <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, 744 <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 745 }; 746 ov13850_sleep_pin: ov13850-sleep-pin { 747 rockchip,pins = 748 <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, 749 <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 750 }; 751 }; 752 headphone { 753 hp_det: hp-det { 754 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 755 }; 756 }; 757 758 pmic { 759 pmic_int: pmic_int { 760 rockchip,pins = 761 <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 762 }; 763 764 soc_slppin_gpio: soc_slppin_gpio { 765 rockchip,pins = 766 <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; 767 }; 768 769 soc_slppin_slp: soc_slppin_slp { 770 rockchip,pins = 771 <0 RK_PA2 1 &pcfg_pull_up>; 772 }; 773 774 soc_slppin_rst: soc_slppin_rst { 775 rockchip,pins = 776 <0 RK_PA2 2 &pcfg_pull_none>; 777 }; 778 }; 779 780 sdio-pwrseq { 781 wifi_enable_h: wifi-enable-h { 782 rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 783 }; 784 }; 785 786 5g { 787 net_5g_rst_gpio: net_5g_rst_gpio { 788 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 789 }; 790 791 net_5g_pwr_gpio: net_5g_pwr_gpio { 792 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 793 }; 794 }; 795}; 796 797&rkisp { 798 status = "okay"; 799}; 800 801&rkisp_mmu { 802 status = "okay"; 803}; 804 805&rkisp_vir0 { 806 status = "okay"; 807 808 port { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 812 isp0_in: endpoint@0 { 813 reg = <0>; 814 remote-endpoint = <&csidphy_out>; 815 }; 816 }; 817}; 818 819&sdmmc2 { 820 max-frequency = <150000000>; 821 supports-sdio; 822 bus-width = <4>; 823 disable-wp; 824 cap-sd-highspeed; 825 cap-sdio-irq; 826 keep-power-in-suspend; 827 mmc-pwrseq = <&sdio_pwrseq>; 828 non-removable; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 831 sd-uhs-sdr104; 832 status = "okay"; 833}; 834 835&uart8 { 836 status = "okay"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; 839}; 840 841&bus_npu { 842 bus-supply = <&vdd_logic>; 843 pvtm-supply = <&vdd_cpu>; 844 status = "okay"; 845}; 846 847&can0 { 848 assigned-clocks = <&cru CLK_CAN0>; 849 assigned-clock-rates = <200000000>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&can0m0_pins>; 852 status = "okay"; 853}; 854 855&can1 { 856 assigned-clocks = <&cru CLK_CAN1>; 857 assigned-clock-rates = <200000000>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&can1m1_pins>; 860 status = "okay"; 861}; 862 863&can2 { 864 assigned-clocks = <&cru CLK_CAN2>; 865 assigned-clock-rates = <150000000>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&can2m1_pins>; 868 status = "disabled"; 869}; 870 871&cpu0 { 872 cpu-supply = <&vdd_cpu>; 873}; 874 875&dfi { 876 status = "okay"; 877}; 878 879&dmc { 880 center-supply = <&vdd_logic>; 881 status = "okay"; 882}; 883 884&gpu { 885 mali-supply = <&vdd_gpu>; 886 status = "okay"; 887}; 888 889&i2c0 { 890 status = "okay"; 891 892 vdd_cpu: tcs4525@1c { 893 compatible = "tcs,tcs452x"; 894 status = "okay"; 895 reg = <0x1c>; 896 vin-supply = <&vcc5v0_sys>; 897 regulator-compatible = "fan53555-reg"; 898 regulator-name = "vdd_cpu"; 899 regulator-min-microvolt = <712500>; 900 regulator-max-microvolt = <1390000>; 901 regulator-init-microvolt = <900000>; 902 regulator-ramp-delay = <2300>; 903 fcs,suspend-voltage-selector = <1>; 904 regulator-boot-on; 905 regulator-always-on; 906 regulator-state-mem { 907 regulator-off-in-suspend; 908 }; 909 }; 910 911 rk809: pmic@20 { 912 compatible = "rockchip,rk809"; 913 reg = <0x20>; 914 interrupt-parent = <&gpio0>; 915 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 916 917 pinctrl-names = "default", "pmic-sleep", 918 "pmic-power-off", "pmic-reset"; 919 pinctrl-0 = <&pmic_int>; 920 pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 921 pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 922 pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; 923 924 rockchip,system-power-controller; 925 wakeup-source; 926 #clock-cells = <1>; 927 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 928 //fb-inner-reg-idxs = <2>; 929 /* 1: rst regs (default in codes), 0: rst the pmic */ 930 pmic-reset-func = <0>; 931 /* not save the PMIC_POWER_EN register in uboot */ 932 not-save-power-en = <1>; 933 934 vcc1-supply = <&vcc3v3_sys>; 935 vcc2-supply = <&vcc3v3_sys>; 936 vcc3-supply = <&vcc3v3_sys>; 937 vcc4-supply = <&vcc3v3_sys>; 938 vcc5-supply = <&vcc3v3_sys>; 939 vcc6-supply = <&vcc3v3_sys>; 940 vcc7-supply = <&vcc3v3_sys>; 941 vcc8-supply = <&vcc3v3_sys>; 942 vcc9-supply = <&vcc3v3_sys>; 943 944 pwrkey { 945 status = "okay"; 946 }; 947 948 pinctrl_rk8xx: pinctrl_rk8xx { 949 gpio-controller; 950 #gpio-cells = <2>; 951 952 rk817_slppin_null: rk817_slppin_null { 953 pins = "gpio_slp"; 954 function = "pin_fun0"; 955 }; 956 957 rk817_slppin_slp: rk817_slppin_slp { 958 pins = "gpio_slp"; 959 function = "pin_fun1"; 960 }; 961 962 rk817_slppin_pwrdn: rk817_slppin_pwrdn { 963 pins = "gpio_slp"; 964 function = "pin_fun2"; 965 }; 966 967 rk817_slppin_rst: rk817_slppin_rst { 968 pins = "gpio_slp"; 969 function = "pin_fun3"; 970 }; 971 }; 972 973 regulators { 974 vdd_logic: DCDC_REG1 { 975 regulator-always-on; 976 regulator-boot-on; 977 regulator-min-microvolt = <500000>; 978 regulator-max-microvolt = <1350000>; 979 regulator-init-microvolt = <900000>; 980 regulator-ramp-delay = <6001>; 981 regulator-initial-mode = <0x2>; 982 regulator-name = "vdd_logic"; 983 regulator-state-mem { 984 regulator-off-in-suspend; 985 }; 986 }; 987 988 vdd_gpu: DCDC_REG2 { 989 regulator-always-on; 990 regulator-boot-on; 991 regulator-min-microvolt = <500000>; 992 regulator-max-microvolt = <1350000>; 993 regulator-init-microvolt = <900000>; 994 regulator-ramp-delay = <6001>; 995 regulator-initial-mode = <0x2>; 996 regulator-name = "vdd_gpu"; 997 regulator-state-mem { 998 regulator-off-in-suspend; 999 }; 1000 }; 1001 1002 vcc_ddr: DCDC_REG3 { 1003 regulator-always-on; 1004 regulator-boot-on; 1005 regulator-initial-mode = <0x2>; 1006 regulator-name = "vcc_ddr"; 1007 regulator-state-mem { 1008 regulator-on-in-suspend; 1009 }; 1010 }; 1011 1012 vdd_npu: DCDC_REG4 { 1013 regulator-always-on; 1014 regulator-boot-on; 1015 regulator-min-microvolt = <500000>; 1016 regulator-max-microvolt = <1350000>; 1017 regulator-init-microvolt = <900000>; 1018 regulator-ramp-delay = <6001>; 1019 regulator-initial-mode = <0x2>; 1020 regulator-name = "vdd_npu"; 1021 regulator-state-mem { 1022 regulator-off-in-suspend; 1023 }; 1024 }; 1025 1026 vdda0v9_image: LDO_REG1 { 1027 regulator-boot-on; 1028 regulator-always-on; 1029 regulator-min-microvolt = <900000>; 1030 regulator-max-microvolt = <900000>; 1031 regulator-name = "vdda0v9_image"; 1032 regulator-state-mem { 1033 regulator-off-in-suspend; 1034 }; 1035 }; 1036 1037 vdda_0v9: LDO_REG2 { 1038 regulator-always-on; 1039 regulator-boot-on; 1040 regulator-min-microvolt = <900000>; 1041 regulator-max-microvolt = <900000>; 1042 regulator-name = "vdda_0v9"; 1043 regulator-state-mem { 1044 regulator-off-in-suspend; 1045 }; 1046 }; 1047 1048 vdda0v9_pmu: LDO_REG3 { 1049 regulator-always-on; 1050 regulator-boot-on; 1051 regulator-min-microvolt = <900000>; 1052 regulator-max-microvolt = <900000>; 1053 regulator-name = "vdda0v9_pmu"; 1054 regulator-state-mem { 1055 regulator-on-in-suspend; 1056 regulator-suspend-microvolt = <900000>; 1057 }; 1058 }; 1059 1060 vccio_acodec: LDO_REG4 { 1061 regulator-always-on; 1062 regulator-boot-on; 1063 regulator-min-microvolt = <3300000>; 1064 regulator-max-microvolt = <3300000>; 1065 regulator-name = "vccio_acodec"; 1066 regulator-state-mem { 1067 regulator-off-in-suspend; 1068 }; 1069 }; 1070 1071 vccio_sd: LDO_REG5 { 1072 regulator-always-on; 1073 regulator-boot-on; 1074 regulator-min-microvolt = <1800000>; 1075 regulator-max-microvolt = <3300000>; 1076 regulator-name = "vccio_sd"; 1077 regulator-state-mem { 1078 regulator-off-in-suspend; 1079 }; 1080 }; 1081 1082 vcc3v3_pmu: LDO_REG6 { 1083 regulator-always-on; 1084 regulator-boot-on; 1085 regulator-min-microvolt = <3300000>; 1086 regulator-max-microvolt = <3300000>; 1087 regulator-name = "vcc3v3_pmu"; 1088 regulator-state-mem { 1089 regulator-on-in-suspend; 1090 regulator-suspend-microvolt = <3300000>; 1091 }; 1092 }; 1093 1094 vcca_1v8: LDO_REG7 { 1095 regulator-always-on; 1096 regulator-boot-on; 1097 regulator-min-microvolt = <1800000>; 1098 regulator-max-microvolt = <1800000>; 1099 regulator-name = "vcca_1v8"; 1100 regulator-state-mem { 1101 regulator-off-in-suspend; 1102 }; 1103 }; 1104 1105 vcca1v8_pmu: LDO_REG8 { 1106 regulator-always-on; 1107 regulator-boot-on; 1108 regulator-min-microvolt = <1800000>; 1109 regulator-max-microvolt = <1800000>; 1110 regulator-name = "vcca1v8_pmu"; 1111 regulator-state-mem { 1112 regulator-on-in-suspend; 1113 regulator-suspend-microvolt = <1800000>; 1114 }; 1115 }; 1116 1117 vcca1v8_image: LDO_REG9 { 1118 regulator-always-on; 1119 regulator-boot-on; 1120 regulator-min-microvolt = <1800000>; 1121 regulator-max-microvolt = <1800000>; 1122 regulator-name = "vcca1v8_image"; 1123 regulator-state-mem { 1124 regulator-off-in-suspend; 1125 }; 1126 }; 1127 1128 vcc_1v8: DCDC_REG5 { 1129 regulator-always-on; 1130 regulator-boot-on; 1131 regulator-min-microvolt = <1800000>; 1132 regulator-max-microvolt = <1800000>; 1133 regulator-name = "vcc_1v8"; 1134 regulator-state-mem { 1135 regulator-off-in-suspend; 1136 }; 1137 }; 1138 1139 vcc_3v3: SWITCH_REG1 { 1140 regulator-always-on; 1141 regulator-boot-on; 1142 regulator-name = "vcc_3v3"; 1143 regulator-state-mem { 1144 regulator-off-in-suspend; 1145 }; 1146 }; 1147 1148 vcc3v3_sd: SWITCH_REG2 { 1149 regulator-always-on; 1150 regulator-boot-on; 1151 regulator-name = "vcc3v3_sd"; 1152 regulator-state-mem { 1153 regulator-off-in-suspend; 1154 }; 1155 }; 1156 }; 1157 1158 rk809_codec: codec { 1159 #sound-dai-cells = <0>; 1160 compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 1161 clocks = <&cru I2S1_MCLKOUT>; 1162 clock-names = "mclk"; 1163 assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; 1164 assigned-clock-rates = <12288000>; 1165 assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&i2s1m0_mclk>; 1168 hp-volume = <20>; 1169 spk-volume = <3>; 1170 mic-in-differential; 1171 status = "okay"; 1172 }; 1173 }; 1174}; 1175 1176&i2c2 { 1177 status = "okay"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&i2c2m1_xfer>; 1180 1181 vm149c_0: vm149c@0c { 1182 compatible = "silicon touch,vm149c"; 1183 status = "okay"; 1184 reg = <0x0c>; 1185 rockchip,camera-module-index = <0>; 1186 rockchip,camera-module-facing = "back"; 1187 }; 1188 1189 ov13850: ov13850@10 { 1190 compatible = "ovti,ov13850"; 1191 status = "okay"; 1192 reg = <0x10>; 1193 clocks = <&cru CLK_CIF_OUT>; 1194 clock-names = "xvclk"; 1195 power-domains = <&power RK3568_PD_VI>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&cif_clk>, <&ov13850_default_pin>; 1198 pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 1199 reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; 1200 rockchip,camera-module-index = <0>; 1201 rockchip,camera-module-facing = "back"; 1202 rockchip,camera-module-name = "ov13850-csi"; 1203 rockchip,camera-module-lens-name = "ov13850-2mp"; 1204 lens-focus = <&vm149c_0>; 1205 1206 port { 1207 ov13850_out: endpoint { 1208 remote-endpoint = <&mipi_in_ov13850>; 1209 data-lanes = <1 2>; 1210 }; 1211 }; 1212 }; 1213 1214 gt9xx_lvds: gt9xx@5d { 1215 compatible = "goodix,gt928"; 1216 reg = <0x5d>; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&touch_gpio>; 1219 interrupt-parent = <&gpio1>; 1220 interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>; 1221 irq-gpio = <&gpio1 RK_PA4 IRQ_TYPE_LEVEL_LOW>; 1222 reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 1223 touchscreen-size-x = <1280>; 1224 touchscreen-size-y = <800>; 1225 touchscreen-swapped-x-y; 1226 uniq = "lvds"; 1227 status = "okay"; 1228 }; 1229 1230 gt9xx_rgb: gt9xx-rgb@5d { 1231 compatible = "goodix,gt928"; 1232 reg = <0x5d>; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&rgb_touch_gpio>; 1235 interrupt-parent = <&gpio4>; 1236 interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>; 1237 irq-gpio = <&gpio4 RK_PC6 IRQ_TYPE_LEVEL_LOW>; 1238 reset-gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; 1239 touchscreen-size-x = <800>; 1240 touchscreen-size-y = <480>; 1241 touchscreen-inverted-x; 1242 touchscreen-inverted-y; 1243 uniq = "rgb"; 1244 status = "disabled"; 1245 }; 1246 1247 gt9xx_dsi: gt9xx@14 { 1248 compatible = "goodix,gt928"; 1249 reg = <0x14>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&dsi_gt911_int>; 1252 interrupt-parent = <&gpio0>; 1253 interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>; 1254 irq-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 1255 reset-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 1256 touchscreen-size-x = <1024>; 1257 touchscreen-size-y = <600>; 1258 uniq = "dsi"; 1259 status = "okay"; 1260 }; 1261 1262 polytouch: edt-ft5x06@38{ 1263 compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; 1264 reg = <0x38>; 1265 pinctrl-names = "defaults"; 1266 pinctrl-0 = <&ft5x06_int>; 1267 interrupt-parent = <&gpio0>; 1268 interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>; 1269 touchscreen-size-x = <1024>; 1270 touchscreen-size-y = <600>; 1271 status = "okay"; 1272 }; 1273}; 1274 1275&i2c3 { 1276 status = "okay"; 1277 1278 rx8010: rx8010@32 { 1279 compatible = "epson,rx8010"; 1280 reg = <0x32>; 1281 }; 1282 1283 pcf8563: pcf8563@51 { 1284 compatible = "nxp,pcf8563"; 1285 reg = <0x51>; 1286 #clock-cells = <0>; 1287 }; 1288}; 1289 1290&i2s0_8ch { 1291 status = "okay"; 1292}; 1293 1294&i2s1_8ch { 1295 status = "okay"; 1296 rockchip,clk-trcm = <1>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&i2s1m0_sclktx 1299 &i2s1m0_lrcktx 1300 &i2s1m0_sdi0 1301 &i2s1m0_sdo0>; 1302}; 1303 1304&iep { 1305 status = "okay"; 1306}; 1307 1308&iep_mmu { 1309 status = "okay"; 1310}; 1311 1312&jpegd { 1313 status = "okay"; 1314}; 1315 1316&jpegd_mmu { 1317 status = "okay"; 1318}; 1319 1320&mpp_srv { 1321 status = "okay"; 1322}; 1323 1324&nandc0 { 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "okay"; 1328 1329 nand@0 { 1330 reg = <0>; 1331 nand-bus-width = <8>; 1332 nand-ecc-mode = "hw"; 1333 nand-ecc-strength = <16>; 1334 nand-ecc-step-size = <1024>; 1335 }; 1336}; 1337 1338 /* 1339 * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. 1340 * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; 1341 * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages 1342 * must be consistent with the software configuration correspondingly 1343 * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration 1344 * should also be configured to 1.8V accordingly; 1345 * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration 1346 * should also be configured to 3.3V accordingly; 1347 * 3/ VCCIO2 voltage control selection (0xFDC20140) 1348 * BIT[0]: 0x0: from GPIO_0A7 (default) 1349 * BIT[0]: 0x1: from GRF 1350 * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: 1351 * L:VCCIO2 must supply 3.3V 1352 * H:VCCIO2 must supply 1.8V 1353 */ 1354&pmu_io_domains { 1355 status = "okay"; 1356 pmuio1-supply = <&vcc3v3_pmu>; 1357 pmuio2-supply = <&vcc3v3_pmu>; 1358 vccio1-supply = <&vccio_acodec>; 1359 vccio3-supply = <&vccio_sd>; 1360 vccio4-supply = <&vcc_1v8>; 1361 vccio5-supply = <&vcc_3v3>; 1362 vccio6-supply = <&vcc_1v8>; 1363 vccio7-supply = <&vcc_3v3>; 1364}; 1365 1366&pwm3 { 1367 status = "okay"; 1368}; 1369 1370&pwm5 { 1371 status = "okay"; 1372}; 1373 1374&pwm14 { 1375 status = "okay"; 1376}; 1377 1378&rk_rga { 1379 status = "okay"; 1380}; 1381 1382&rkvdec { 1383 status = "okay"; 1384}; 1385 1386&rkvdec_mmu { 1387 status = "okay"; 1388}; 1389 1390&rkvenc { 1391 venc-supply = <&vdd_logic>; 1392 status = "okay"; 1393}; 1394 1395&rkvenc_mmu { 1396 status = "okay"; 1397}; 1398 1399&rknpu { 1400 rknpu-supply = <&vdd_npu>; 1401 status = "okay"; 1402}; 1403 1404&rknpu_mmu { 1405 status = "okay"; 1406}; 1407 1408&saradc { 1409 status = "okay"; 1410 vref-supply = <&vcca_1v8>; 1411}; 1412 1413&sdhci { 1414 bus-width = <8>; 1415 supports-emmc; 1416 non-removable; 1417 max-frequency = <200000000>; 1418 status = "okay"; 1419}; 1420 1421&sdmmc0 { 1422 max-frequency = <150000000>; 1423 supports-sd; 1424 bus-width = <4>; 1425 cap-mmc-highspeed; 1426 cap-sd-highspeed; 1427 disable-wp; 1428 sd-uhs-sdr104; 1429 vmmc-supply = <&vcc3v3_sd>; 1430 vqmmc-supply = <&vccio_sd>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 1433 status = "okay"; 1434}; 1435 1436&sfc { 1437 status = "okay"; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&fspi_pins>; 1440 flash: m25p80@0 { 1441 #address-cells = <1>; 1442 #size-cells = <1>; 1443 compatible = "spansion,m25p80", "jedec,spi-nor"; 1444 reg = <0>; 1445 spi-max-frequency = <40000000>; 1446 m25p,fast-read; 1447 }; 1448}; 1449 1450&spdif_8ch { 1451 status = "disabled"; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&spdifm1_tx>; 1454}; 1455 1456&tsadc { 1457 status = "okay"; 1458}; 1459 1460&u2phy0_host { 1461 status = "okay"; 1462}; 1463 1464&u2phy0_otg { 1465 status = "okay"; 1466}; 1467 1468&u2phy1_host { 1469 status = "okay"; 1470}; 1471 1472&u2phy1_otg { 1473 status = "okay"; 1474}; 1475 1476&usb2phy0 { 1477 status = "okay"; 1478}; 1479 1480&usb2phy1 { 1481 status = "okay"; 1482}; 1483 1484&usb_host0_ehci { 1485 status = "okay"; 1486}; 1487 1488&usb_host0_ohci { 1489 status = "okay"; 1490}; 1491 1492&usb_host1_ehci { 1493 status = "okay"; 1494}; 1495 1496&usb_host1_ohci { 1497 status = "okay"; 1498}; 1499 1500&usbdrd_dwc3 { 1501 dr_mode = "otg"; 1502 extcon = <&usb2phy0>; 1503 status = "okay"; 1504}; 1505 1506&usbdrd30 { 1507 status = "okay"; 1508}; 1509 1510&usbhost_dwc3 { 1511 status = "okay"; 1512}; 1513 1514&usbhost30 { 1515 status = "okay"; 1516}; 1517 1518&vad { 1519 rockchip,audio-src = <&i2s1_8ch>; 1520 rockchip,buffer-time-ms = <128>; 1521 rockchip,det-channel = <0>; 1522 rockchip,mode = <0>; 1523}; 1524 1525&vdpu { 1526 status = "okay"; 1527}; 1528 1529&vdpu_mmu { 1530 status = "okay"; 1531}; 1532 1533&vepu { 1534 status = "okay"; 1535}; 1536 1537&vepu_mmu { 1538 status = "okay"; 1539}; 1540 1541&vop { 1542 status = "okay"; 1543 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 1544 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; 1545 disable-win-move; 1546}; 1547 1548&vop_mmu { 1549 status = "okay"; 1550}; 1551 1552&vp0 { 1553 cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>; 1554}; 1555 1556&vp1 { 1557 cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>; 1558}; 1559 1560&edp { 1561 status = "disabled"; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&edpdpm0_pins>; 1564 1565 ports { 1566 port@1 { 1567 reg = <1>; 1568 1569 edp_out_panel: endpoint { 1570 remote-endpoint = <&panel_in_edp>; 1571 }; 1572 }; 1573 }; 1574}; 1575 1576&edp_phy { 1577 status = "disabled"; 1578}; 1579 1580&edp_in_vp0 { 1581 status = "disabled"; 1582}; 1583 1584&edp_in_vp1 { 1585 status = "disabled"; 1586}; 1587 1588&route_edp { 1589 status = "disabled"; 1590 connect = <&vp1_out_edp>; 1591}; 1592&route_dsi1 { 1593 status = "disabled"; 1594 connect = <&vp1_out_dsi1>; 1595}; 1596 1597&dsi1_in_vp0 { 1598 status = "disabled"; 1599}; 1600 1601&dsi1_in_vp1 { 1602 status = "disabled"; 1603}; 1604 1605&dsi1 { 1606 status = "disabled"; 1607 //rockchip,lane-rate = <1000>; 1608 dsi1_panel: panel@0 { 1609 status = "okay"; 1610 compatible = "simple-panel-dsi"; 1611 reg = <0>; 1612 reset-delay-ms = <60>; 1613 enable-delay-ms = <60>; 1614 prepare-delay-ms = <60>; 1615 unprepare-delay-ms = <60>; 1616 disable-delay-ms = <60>; 1617 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 1618 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 1619 dsi,format = <MIPI_DSI_FMT_RGB888>; 1620 dsi,lanes = <4>; 1621 panel-init-sequence = [ 1622 ]; 1623 1624 panel-exit-sequence = [ 1625 ]; 1626 1627 panel-width-mm = <68>; 1628 panel-height-mm = <121>; 1629 backlight = <&dsi1_backlight>; 1630 enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 1631 1632 display-timings { 1633 native-mode = <&panel7_1024x600>; 1634 panel7_1024x600: timings { 1635 hback-porch = <48>; 1636 hfront-porch = <40>; 1637 hactive = <1024>; 1638 hsync-len = <48>; 1639 vback-porch = <48>; 1640 vfront-porch = <40>; 1641 vactive = <600>; 1642 vsync-len = <4>; 1643 clock-frequency = <45000000>; 1644 vsync-active = <0>; 1645 hsync-active = <0>; 1646 de-active = <0>; 1647 pixelclk-active = <0>; 1648 }; 1649 }; 1650 1651 ports { 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 1655 port@0 { 1656 reg = <0>; 1657 panel_in_dsi: endpoint { 1658 remote-endpoint = <&dsi_out_panel>; 1659 }; 1660 }; 1661 }; 1662 }; 1663 1664 ports { 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 1668 port@1 { 1669 reg = <1>; 1670 dsi_out_panel: endpoint { 1671 remote-endpoint = <&panel_in_dsi>; 1672 }; 1673 }; 1674 }; 1675 1676}; 1677 1678&hdmi { 1679 status = "disabled"; 1680 rockchip,phy-table = 1681 <92812500 0x8009 0x0000 0x0270>, 1682 <165000000 0x800b 0x0000 0x026d>, 1683 <185625000 0x800b 0x0000 0x01ed>, 1684 <297000000 0x800b 0x0000 0x01ad>, 1685 <594000000 0x8029 0x0000 0x0088>, 1686 <000000000 0x0000 0x0000 0x0000>; 1687}; 1688 1689&hdmi_in_vp0 { 1690 status = "disabled"; 1691}; 1692 1693&hdmi_in_vp1 { 1694 status = "disabled"; 1695}; 1696 1697&route_hdmi { 1698 status = "disabled"; 1699 connect = <&vp0_out_hdmi>; 1700}; 1701 1702&lvds { 1703 status = "disabled"; 1704 phys = <&video_phy0>; 1705 phy-names = "phy"; 1706 1707 ports { 1708 port@1 { 1709 reg = <1>; 1710 1711 lvds_out_panel: endpoint { 1712 remote-endpoint = <&panel_in_lvds>; 1713 }; 1714 }; 1715 }; 1716}; 1717 1718&lvds_in_vp1 { 1719 status = "disabled"; 1720}; 1721 1722&lvds_in_vp2 { 1723 status = "disabled"; 1724}; 1725 1726&route_lvds { 1727 status = "disabled"; 1728 connect = <&vp2_out_lvds>; 1729}; 1730 1731&rgb { 1732 status = "disabled"; 1733 phys = <&video_phy0>; 1734 phy-names = "phy"; 1735 1736 ports { 1737 port@1 { 1738 reg = <1>; 1739 rgb_out_panel: endpoint { 1740 remote-endpoint = <&panel_in_rgb>; 1741 }; 1742 }; 1743 }; 1744}; 1745 1746 1747&rgb_in_vp2 { 1748 status = "disabled"; 1749}; 1750 1751&route_rgb { 1752 status = "disabled"; 1753 connect = <&vp2_out_rgb>; 1754}; 1755 1756/* 1757&rgb { 1758 status = "okay"; 1759 1760 ports { 1761 port@1 { 1762 reg = <1>; 1763 rgb_out_panel: endpoint { 1764 remote-endpoint = <&panel_in_rgb>; 1765 }; 1766 }; 1767 }; 1768}; 1769 1770 1771&rgb_in_vp2 { 1772 status = "okay"; 1773}; 1774 1775&route_rgb { 1776 status = "okay"; 1777 connect = <&vp2_out_rgb>; 1778}; 1779*/ 1780&xin32k { 1781 status = "disabled"; 1782}; 1783 1784&uart3 { 1785 status = "okay"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&uart3m1_xfer>; 1788}; 1789 1790&uart4 { 1791 status = "okay"; 1792 pinctrl-names = "default"; 1793 pinctrl-0 = <&uart4m1_xfer>; 1794}; 1795 1796&uart5 { 1797 status = "okay"; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&uart5m1_xfer>; 1800}; 1801 1802&spi0 { 1803 pinctrl-names = "default", "high_speed"; 1804 pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>; 1805 pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>; 1806 status = "disabled"; 1807 1808 spi@0 { 1809 compatible = "rockchip,spidev"; 1810 reg = <0>; 1811 spi-max-frequency = <50000000>; 1812 }; 1813}; 1814 1815&spi2 { 1816 pinctrl-names = "default", "high_speed"; 1817 pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>; 1818 pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>; 1819 status = "okay"; 1820 1821 spi@0 { 1822 compatible = "rockchip,spidev"; 1823 reg = <0>; 1824 spi-max-frequency = <50000000>; 1825 }; 1826 1827 spi@1 { 1828 compatible = "rockchip,spidev"; 1829 reg = <1>; 1830 spi-max-frequency = <50000000>; 1831 }; 1832}; 1833