1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 29 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz, //0 87 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz, //1 88 89 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz, //2 90 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz, //3 91 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz, //4 92 93 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz, //5 94 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz, //6 95 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz, //7 96 97 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz, //8 98 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz, //9 99 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz, //10 100 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz, //11 101 102 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //12 103 E_PNL_SUPPORTED_LPLL_TTL_50to100MHz, //13 104 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //14 105 E_PNL_SUPPORTED_LPLL_TTL_25to25MHz, //15 106 107 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to340MHz, //16 108 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz, //17 109 110 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz, //18 111 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz, //19 112 113 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz, //20 114 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to38MHz, //21 115 116 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to340MHz, //22 117 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz, //23 118 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz, //24 119 120 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz, //25 121 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz, //26 122 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz, //27 123 124 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz, //28 125 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to55MHz, //29 126 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to38MHz, //30 127 128 E_PNL_SUPPORTED_LPLL_EPI_34_10BIT_12PAIR_4K_CASE2_V15_330to330MHz, //31 129 130 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_V15_330to330MHz, //32 131 132 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_V15_330to330MHz, //33 133 134 E_PNL_SUPPORTED_LPLL_MAX, //34 135 } E_PNL_SUPPORTED_LPLL_TYPE; 136 137 typedef struct 138 { 139 MS_U8 address; 140 MS_U16 value; 141 MS_U16 mask; 142 }TBLStruct,*pTBLStruct; 143 144 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 145 { 146 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.0 147 //Address,Value,Mask 148 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 149 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 150 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 151 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 152 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 153 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 154 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 155 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 156 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 157 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 158 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 159 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 160 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 161 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 162 {0x33,0x0020,0x0020},//reg_lpll2_pd 163 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 164 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 165 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 166 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 167 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 168 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 169 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 170 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 171 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 172 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 173 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 174 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 175 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 176 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 177 }, 178 179 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.1 180 //Address,Value,Mask 181 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 182 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 183 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 184 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 185 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 186 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 187 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 188 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 189 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 190 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 191 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 192 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 193 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 194 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 195 {0x33,0x0020,0x0020},//reg_lpll2_pd 196 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 197 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 198 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 199 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 200 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 201 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 202 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 203 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 204 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 205 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 206 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 207 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 208 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 209 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 210 }, 211 212 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz NO.2 213 //Address,Value,Mask 214 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 215 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 216 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 217 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 218 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 219 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 220 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 221 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 222 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 223 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 224 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 225 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 226 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 227 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 228 {0x33,0x0020,0x0020},//reg_lpll2_pd 229 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 230 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 231 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 232 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 233 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 234 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 235 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 236 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 237 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 238 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 239 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 240 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 241 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 242 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 243 }, 244 245 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.3 246 //Address,Value,Mask 247 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 248 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 249 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 250 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 251 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 252 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 253 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 254 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 255 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 256 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 257 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 258 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 259 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 260 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 261 {0x33,0x0020,0x0020},//reg_lpll2_pd 262 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 263 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 264 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 265 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 266 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 267 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 268 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 269 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 270 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 271 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 272 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 273 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 274 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 275 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 276 }, 277 278 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.4 279 //Address,Value,Mask 280 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 281 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 282 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 283 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 284 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 285 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 286 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 287 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 288 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 289 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 290 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 291 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 292 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 293 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 294 {0x33,0x0020,0x0020},//reg_lpll2_pd 295 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 296 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 297 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 298 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 299 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 300 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 301 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 302 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 303 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 304 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 305 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 306 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 307 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 308 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 309 }, 310 311 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.5 312 //Address,Value,Mask 313 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 314 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 315 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 316 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 317 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 318 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 319 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 320 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 321 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 322 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 323 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 324 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 325 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 326 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 327 {0x33,0x0020,0x0020},//reg_lpll2_pd 328 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 329 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 330 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 331 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 332 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 333 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 334 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 335 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 336 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 337 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 338 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 339 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 340 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 341 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 342 }, 343 344 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.6 345 //Address,Value,Mask 346 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 347 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 348 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 349 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 350 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 351 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 352 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 353 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 354 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 355 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 356 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 357 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 358 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 359 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 360 {0x33,0x0020,0x0020},//reg_lpll2_pd 361 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 362 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 363 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 364 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 365 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 366 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 367 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 368 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 369 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 370 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 371 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 372 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 373 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 374 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 375 }, 376 377 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.7 378 //Address,Value,Mask 379 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 380 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 381 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 382 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 383 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 384 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 385 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 386 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 387 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 388 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 389 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 390 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 391 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 392 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 393 {0x33,0x0020,0x0020},//reg_lpll2_pd 394 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 395 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 396 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 397 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 398 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 399 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 400 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 401 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 402 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 403 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 404 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 405 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 406 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 407 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 408 }, 409 410 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz NO.8 411 //Address,Value,Mask 412 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 413 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 414 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 415 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 416 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 417 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 418 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 419 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 420 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 421 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 422 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 423 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 424 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 425 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 426 {0x33,0x0020,0x0020},//reg_lpll2_pd 427 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 428 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 429 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 430 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 431 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 432 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 433 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 434 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 435 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 436 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 437 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 438 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 439 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 440 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 441 }, 442 443 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz NO.9 444 //Address,Value,Mask 445 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 446 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 447 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 448 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 449 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 450 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 451 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 452 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 453 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 454 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 455 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 456 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 457 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 458 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 459 {0x33,0x0020,0x0020},//reg_lpll2_pd 460 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 461 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 462 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 463 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 464 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 465 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 466 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 467 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 468 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 469 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 470 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 471 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 472 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 473 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 474 }, 475 476 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz NO.10 477 //Address,Value,Mask 478 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 479 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 480 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 481 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 482 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 483 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 484 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 485 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 486 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 487 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 488 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 489 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 490 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 491 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 492 {0x33,0x0020,0x0020},//reg_lpll2_pd 493 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 494 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 495 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 496 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 497 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 498 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 499 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 500 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 501 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 502 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 503 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 504 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 505 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 506 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 507 }, 508 509 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.11 510 //Address,Value,Mask 511 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 512 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 513 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 514 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 515 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 516 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 517 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 518 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 519 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 520 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 521 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 522 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 523 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 524 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 525 {0x33,0x0020,0x0020},//reg_lpll2_pd 526 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 527 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 528 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 529 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 530 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 531 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 532 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 533 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 534 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 535 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 536 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 537 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 538 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 539 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 540 }, 541 542 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.12 543 //Address,Value,Mask 544 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 545 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 546 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 547 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 548 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 549 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 550 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 551 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 552 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 553 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 554 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 555 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 556 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 557 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 558 {0x33,0x0020,0x0020},//reg_lpll2_pd 559 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 560 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 561 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 562 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 563 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 564 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 565 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 566 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 567 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 568 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 569 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 570 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 571 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 572 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 573 }, 574 575 { //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.13 576 //Address,Value,Mask 577 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 578 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 579 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 580 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 581 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 582 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 583 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 584 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 585 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 586 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 587 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 588 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 589 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 590 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 591 {0x33,0x0020,0x0020},//reg_lpll2_pd 592 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 593 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 594 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 595 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 596 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 597 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 598 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 599 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 600 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 601 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 602 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 603 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 604 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 605 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 606 }, 607 608 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.14 609 //Address,Value,Mask 610 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 611 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 612 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 613 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 614 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 615 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 616 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 617 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 618 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 619 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 620 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 621 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 622 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 623 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 624 {0x33,0x0020,0x0020},//reg_lpll2_pd 625 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 626 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 627 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 628 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 629 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 630 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 631 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 632 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 633 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 634 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 635 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 636 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 637 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 638 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 639 }, 640 641 { //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.15 642 //Address,Value,Mask 643 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 644 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 645 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 646 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 647 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 648 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 649 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 650 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 651 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 652 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 653 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 654 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 655 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 656 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 657 {0x33,0x0020,0x0020},//reg_lpll2_pd 658 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 659 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 660 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 661 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 662 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 663 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 664 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 665 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 666 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 667 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 668 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 669 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 670 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 671 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 672 }, 673 674 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to340MHz NO.16 675 //Address,Value,Mask 676 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 677 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 678 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 679 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 680 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 681 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 682 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 683 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 684 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 685 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 686 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 687 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 688 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 689 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 690 {0x33,0x0020,0x0020},//reg_lpll2_pd 691 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 692 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 693 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 694 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 695 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 696 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 697 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 698 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 699 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 700 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 701 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 702 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 703 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 704 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 705 }, 706 707 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz NO.17 708 //Address,Value,Mask 709 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 710 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 711 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 712 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 713 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 714 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 715 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 716 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 717 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 718 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 719 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 720 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 721 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 722 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 723 {0x33,0x0020,0x0020},//reg_lpll2_pd 724 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 725 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 726 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 727 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 728 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 729 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 730 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 731 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 732 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 733 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 734 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 735 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 736 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 737 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 738 }, 739 740 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.18 741 //Address,Value,Mask 742 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 743 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 744 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 745 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 746 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 747 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 748 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 749 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 750 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 751 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 752 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 753 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 754 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 755 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 756 {0x33,0x0020,0x0020},//reg_lpll2_pd 757 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 758 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 759 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 760 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 761 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 762 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 763 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 764 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 765 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 766 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 767 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 768 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 769 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 770 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 771 }, 772 773 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.19 774 //Address,Value,Mask 775 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 776 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 777 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 778 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 779 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 780 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 781 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 782 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 783 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 784 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 785 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 786 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 787 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 788 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 789 {0x33,0x0020,0x0020},//reg_lpll2_pd 790 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 791 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 792 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 793 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 794 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 795 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 796 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 797 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 798 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 799 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 800 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 801 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 802 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 803 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 804 }, 805 806 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz NO.20 807 //Address,Value,Mask 808 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 809 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 810 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 811 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 812 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 813 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 814 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 815 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 816 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 817 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 818 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 819 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 820 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 821 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 822 {0x33,0x0020,0x0020},//reg_lpll2_pd 823 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 824 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 825 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 826 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 827 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 828 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 829 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 830 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 831 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 832 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 833 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 834 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 835 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 836 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 837 }, 838 839 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to38MHz NO.21 840 //Address,Value,Mask 841 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 842 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 843 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 844 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 845 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 846 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 847 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 848 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 849 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 850 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 851 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 852 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 853 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 854 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 855 {0x33,0x0020,0x0020},//reg_lpll2_pd 856 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 857 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 858 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 859 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 860 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 861 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 862 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 863 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 864 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 865 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 866 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 867 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 868 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 869 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 870 }, 871 872 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to340MHz NO.22 873 //Address,Value,Mask 874 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 875 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 876 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 877 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 878 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 879 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 880 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 881 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 882 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 883 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 884 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 885 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 886 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 887 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 888 {0x33,0x0020,0x0020},//reg_lpll2_pd 889 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 890 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 891 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 892 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 893 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 894 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 895 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 896 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 897 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 898 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 899 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 900 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 901 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 902 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 903 }, 904 905 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz NO.23 906 //Address,Value,Mask 907 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 908 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 909 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 910 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 911 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 912 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 913 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 914 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 915 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 916 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 917 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 918 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 919 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 920 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 921 {0x33,0x0020,0x0020},//reg_lpll2_pd 922 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 923 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 924 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 925 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 926 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 927 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 928 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 929 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 930 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 931 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 932 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 933 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 934 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 935 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 936 }, 937 938 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz NO.24 939 //Address,Value,Mask 940 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 941 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 942 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 943 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 944 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 945 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 946 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 947 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 948 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 949 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 950 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 951 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 952 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 953 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 954 {0x33,0x0020,0x0020},//reg_lpll2_pd 955 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 956 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 957 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 958 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 959 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 960 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 961 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 962 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 963 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 964 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 965 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 966 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 967 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 968 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 969 }, 970 971 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz NO.25 972 //Address,Value,Mask 973 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 974 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 975 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 976 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 977 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 978 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 979 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 980 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 981 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 982 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 983 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 984 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 985 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 986 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 987 {0x33,0x0020,0x0020},//reg_lpll2_pd 988 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 989 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 990 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 991 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 992 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 993 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 994 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 995 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 996 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 997 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 998 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 999 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1000 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1001 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1002 }, 1003 1004 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz NO.26 1005 //Address,Value,Mask 1006 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1007 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1008 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1009 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1010 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1011 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1012 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1013 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1014 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1015 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1016 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1017 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1018 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1019 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1020 {0x33,0x0020,0x0020},//reg_lpll2_pd 1021 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1022 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1023 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1024 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1025 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1026 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1027 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1028 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1029 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1030 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1031 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1032 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1033 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1034 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1035 }, 1036 1037 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.27 1038 //Address,Value,Mask 1039 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1040 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1041 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1042 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1043 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1044 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1045 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1046 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1047 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1048 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1049 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1050 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1051 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1052 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1053 {0x33,0x0020,0x0020},//reg_lpll2_pd 1054 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1055 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1056 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1057 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1058 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1059 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1060 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1061 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1062 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1063 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1064 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1065 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1066 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1067 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1068 }, 1069 1070 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz NO.28 1071 //Address,Value,Mask 1072 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1073 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1074 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1075 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1076 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1077 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1078 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1079 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1080 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1081 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1082 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1083 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1084 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1085 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1086 {0x33,0x0020,0x0020},//reg_lpll2_pd 1087 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1088 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1089 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1090 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1091 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1092 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1093 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1094 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1095 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1096 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1097 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1098 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1099 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1100 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1101 }, 1102 1103 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to55MHz NO.29 1104 //Address,Value,Mask 1105 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1106 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1107 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1108 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1109 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1110 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1111 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1112 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1113 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1114 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1115 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1116 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1117 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1118 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1119 {0x33,0x0020,0x0020},//reg_lpll2_pd 1120 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1121 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1122 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1123 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1124 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1125 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1126 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1127 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1128 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1129 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1130 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1131 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1132 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1133 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1134 }, 1135 1136 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to38MHz NO.30 1137 //Address,Value,Mask 1138 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1139 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1140 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1141 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1142 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1143 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1144 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1145 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1146 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1147 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1148 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1149 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1150 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1151 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1152 {0x33,0x0020,0x0020},//reg_lpll2_pd 1153 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1154 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1155 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1156 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1157 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1158 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1159 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1160 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1161 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1162 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1163 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1164 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1165 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1166 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1167 }, 1168 1169 { //E_PNL_SUPPORTED_LPLL_EPI_34_10BIT_12PAIR_4K_CASE2_V15_330to330MHz NO.31 1170 //Address,Value,Mask 1171 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1172 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1173 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1174 {0x01,0x0100,0x0F00},//reg_lpll1_loop_div_second 1175 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1176 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1177 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1178 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1179 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1180 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1181 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1182 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1183 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1184 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1185 {0x33,0x0000,0x0020},//reg_lpll2_pd 1186 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1187 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1188 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1189 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1190 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1191 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1192 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1193 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1194 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1195 {0x37,0x0001,0x0001},//reg_lpll1_test[16] 1196 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1197 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1198 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1199 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1200 }, 1201 1202 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_V15_330to330MHz NO.32 1203 //Address,Value,Mask 1204 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1205 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1206 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1207 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1208 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1209 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1210 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1211 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1212 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1213 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1214 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1215 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1216 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1217 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1218 {0x33,0x0000,0x0020},//reg_lpll2_pd 1219 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1220 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1221 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1222 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1223 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1224 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1225 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1226 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1227 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1228 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1229 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1230 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1231 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1232 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1233 }, 1234 1235 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_V15_330to330MHz NO.33 1236 //Address,Value,Mask 1237 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1238 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1239 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1240 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1241 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1242 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1243 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1244 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1245 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1246 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1247 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1248 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1249 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1250 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1251 {0x33,0x0000,0x0020},//reg_lpll2_pd 1252 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1253 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1254 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1255 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1256 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1257 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1258 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1259 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1260 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1261 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1262 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1263 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1264 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1265 {0x37,0x0000,0x0004},//reg_lpll1_test[18] 1266 }, 1267 1268 }; 1269 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 1270 { 1271 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.0 1272 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.1 1273 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz NO.2 1274 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.3 1275 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.4 1276 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.5 1277 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.6 1278 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.7 1279 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz NO.8 1280 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz NO.9 1281 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz NO.10 1282 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.11 1283 12, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.12 1284 12, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.13 1285 12, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.14 1286 12, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.15 1287 20, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to340MHz NO.16 1288 20, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz NO.17 1289 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.18 1290 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.19 1291 20, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz NO.20 1292 20, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to38MHz NO.21 1293 40, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to340MHz NO.22 1294 20, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz NO.23 1295 20, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz NO.24 1296 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz NO.25 1297 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz NO.26 1298 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.27 1299 20, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz NO.28 1300 20, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to55MHz NO.29 1301 20, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to38MHz NO.30 1302 8, //E_PNL_SUPPORTED_LPLL_EPI_34_10BIT_12PAIR_4K_CASE2_V15_330to330MHz NO.31 1303 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_V15_330to330MHz NO.32 1304 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_V15_330to330MHz NO.33 1305 }; 1306 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 1307 { 1308 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.0 1309 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.1 1310 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz NO.2 1311 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.3 1312 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.4 1313 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.5 1314 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.6 1315 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.7 1316 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz NO.8 1317 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz NO.9 1318 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz NO.10 1319 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.11 1320 8, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.12 1321 16, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.13 1322 32, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.14 1323 32, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.15 1324 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to340MHz NO.16 1325 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz NO.17 1326 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.18 1327 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.19 1328 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz NO.20 1329 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to38MHz NO.21 1330 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to340MHz NO.22 1331 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz NO.23 1332 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz NO.24 1333 15, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz NO.25 1334 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz NO.26 1335 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.27 1336 30, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz NO.28 1337 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to55MHz NO.29 1338 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_38to38MHz NO.30 1339 4, //E_PNL_SUPPORTED_LPLL_EPI_34_10BIT_12PAIR_4K_CASE2_V15_330to330MHz NO.31 1340 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_V15_330to330MHz NO.32 1341 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_V15_330to330MHz NO.33 1342 }; 1343 1344 #endif //_LPLL_TBL_H_ 1345