1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_EXT_TBL_H_ 80 #define _LPLL_EXT_TBL_H_ 81 82 #define LPLL_EXT_REG_NUM 17 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz, //1 88 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz, //2 89 E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz, //3 90 91 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz, //4 92 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to150MHz, //5 93 94 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz, //6 95 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to75MHz, //7 96 97 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to75MHz, //8 98 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to38MHz, //9 99 100 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz, //10 101 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz, //11 102 E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to150MHz, //12 103 104 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz, //13 105 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz, //14 106 E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to75MHz, //15 107 108 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz, //16 109 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to55MHz, //17 110 E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to38MHz, //18 111 112 E_PNL_SUPPORTED_LPLL_EXT_MAX, //19 113 } E_PNL_SUPPORTED_LPLL_EXT_TYPE; 114 115 typedef struct 116 { 117 MS_U8 address; 118 MS_U16 value; 119 MS_U16 mask; 120 }TBLStruct_Ext,*pTBLStruct_Ext; 121 122 TBLStruct_Ext LPLLSettingTBL_Ext[E_PNL_SUPPORTED_LPLL_EXT_MAX][LPLL_EXT_REG_NUM]= 123 { 124 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 125 //Address,Value,Mask 126 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 127 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 128 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 129 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 130 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 131 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 132 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 133 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 134 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 135 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 136 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 137 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 138 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 139 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 140 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 141 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 142 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 143 }, 144 145 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 146 //Address,Value,Mask 147 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 148 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 149 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 150 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 151 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 152 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 153 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 154 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 155 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 156 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 157 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 158 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 159 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 160 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 161 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 162 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 163 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 164 }, 165 166 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 167 //Address,Value,Mask 168 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 169 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 170 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 171 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 172 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 173 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 174 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 175 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 176 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 177 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 178 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 179 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 180 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 181 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 182 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 183 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 184 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 185 }, 186 187 { //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.3 188 //Address,Value,Mask 189 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 190 {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl 191 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 192 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 193 {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec 194 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 195 {0x42,0x0070,0x00F0},//reg_lpll_ext_scalar_div_sec 196 {0x43,0x0002,0x0007},//reg_lpll_ext_skew_div 197 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 198 {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk 199 {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en 200 {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en 201 {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini 202 {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo 203 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 204 {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en 205 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 206 }, 207 208 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz NO.4 209 //Address,Value,Mask 210 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 211 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 212 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 213 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 214 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 215 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 216 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 217 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 218 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 219 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 220 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 221 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 222 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 223 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 224 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 225 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 226 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 227 }, 228 229 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to150MHz NO.5 230 //Address,Value,Mask 231 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 232 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 233 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 234 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 235 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 236 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 237 {0x42,0x0000,0x00F0},//reg_lpll_ext_scalar_div_sec 238 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 239 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 240 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 241 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 242 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 243 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 244 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 245 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 246 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 247 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 248 }, 249 250 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz NO.6 251 //Address,Value,Mask 252 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 253 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 254 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 255 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 256 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 257 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 258 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 259 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 260 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 261 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 262 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 263 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 264 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 265 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 266 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 267 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 268 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 269 }, 270 271 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to75MHz NO.7 272 //Address,Value,Mask 273 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 274 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 275 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 276 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 277 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 278 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 279 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 280 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 281 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 282 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 283 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 284 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 285 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 286 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 287 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 288 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 289 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 290 }, 291 292 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to75MHz NO.8 293 //Address,Value,Mask 294 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 295 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 296 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 297 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 298 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 299 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 300 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 301 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 302 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 303 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 304 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 305 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 306 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 307 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 308 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 309 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 310 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 311 }, 312 313 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to38MHz NO.9 314 //Address,Value,Mask 315 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 316 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 317 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 318 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 319 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 320 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 321 {0x42,0x0020,0x00F0},//reg_lpll_ext_scalar_div_sec 322 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 323 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 324 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 325 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 326 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 327 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 328 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 329 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 330 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 331 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 332 }, 333 334 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz NO.10 335 //Address,Value,Mask 336 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 337 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 338 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 339 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 340 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 341 {0x42,0x0000,0x0003},//reg_lpll_ext_scalar_div_fst 342 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 343 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 344 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 345 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 346 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 347 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 348 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 349 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 350 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 351 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 352 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 353 }, 354 355 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz NO.11 356 //Address,Value,Mask 357 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 358 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 359 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 360 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 361 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 362 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 363 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 364 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 365 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 366 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 367 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 368 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 369 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 370 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 371 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 372 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 373 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 374 }, 375 376 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to150MHz NO.12 377 //Address,Value,Mask 378 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 379 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 380 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 381 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 382 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 383 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 384 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 385 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 386 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 387 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 388 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 389 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 390 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 391 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 392 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 393 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 394 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 395 }, 396 397 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz NO.13 398 //Address,Value,Mask 399 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 400 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 401 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 402 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 403 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 404 {0x42,0x0001,0x0003},//reg_lpll_ext_scalar_div_fst 405 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 406 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 407 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 408 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 409 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 410 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 411 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 412 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 413 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 414 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 415 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 416 }, 417 418 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz NO.14 419 //Address,Value,Mask 420 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 421 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 422 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 423 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 424 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 425 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 426 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 427 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 428 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 429 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 430 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 431 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 432 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 433 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 434 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 435 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 436 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 437 }, 438 439 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to75MHz NO.15 440 //Address,Value,Mask 441 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 442 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 443 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 444 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 445 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 446 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 447 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 448 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 449 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 450 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 451 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 452 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 453 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 454 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 455 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 456 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 457 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 458 }, 459 460 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz NO.16 461 //Address,Value,Mask 462 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 463 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 464 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 465 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 466 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 467 {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst 468 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 469 {0x43,0x0000,0x0007},//reg_lpll_ext_skew_div 470 {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div 471 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 472 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 473 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 474 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 475 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 476 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 477 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 478 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 479 }, 480 481 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to55MHz NO.17 482 //Address,Value,Mask 483 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 484 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 485 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 486 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 487 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 488 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 489 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 490 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 491 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 492 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 493 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 494 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 495 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 496 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 497 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 498 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 499 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 500 }, 501 502 { //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to38MHz NO.18 503 //Address,Value,Mask 504 {0x40,0x0000,0x8000},//reg_lpll_ext_pd 505 {0x40,0x0002,0x0007},//reg_lpll_ext_ictrl 506 {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst 507 {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst 508 {0x41,0x0500,0x0F00},//reg_lpll_ext_loop_div_sec 509 {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst 510 {0x42,0x0030,0x00F0},//reg_lpll_ext_scalar_div_sec 511 {0x43,0x0001,0x0007},//reg_lpll_ext_skew_div 512 {0x42,0x0400,0x0700},//reg_lpll_ext_fifo_div 513 {0x43,0x0000,0x0010},//reg_lpll_ext_skew_en_fixclk 514 {0x40,0x0800,0x0800},//reg_lpll_ext_dual_lp_en 515 {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en 516 {0x40,0x0000,0x2000},//reg_lpll_ext_en_mini 517 {0x40,0x0400,0x0400},//reg_lpll_ext_en_fifo 518 {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar 519 {0x40,0x1000,0x1000},//reg_lpll_ext_fifo_div5_en 520 {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en 521 }, 522 523 }; 524 MS_U16 u16EXT_LoopGain[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 525 { 526 12, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 527 6, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 528 3, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 529 3, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.3 530 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz NO.4 531 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to150MHz NO.5 532 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz NO.6 533 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to75MHz NO.7 534 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to75MHz NO.8 535 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to38MHz NO.9 536 8, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz NO.10 537 4, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz NO.11 538 4, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to150MHz NO.12 539 4, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz NO.13 540 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz NO.14 541 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to75MHz NO.15 542 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz NO.16 543 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to55MHz NO.17 544 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to38MHz NO.18 545 }; 546 MS_U16 u16EXT_LoopDiv[E_PNL_SUPPORTED_LPLL_EXT_MAX]= 547 { 548 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_115to150MHz NO.0 549 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_57to115MHz NO.1 550 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to57MHz NO.2 551 7, //E_PNL_SUPPORTED_LPLL_EXT_HS_LVDS_1CH_25to25MHz NO.3 552 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to340MHz NO.4 553 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_10BIT_150to150MHz NO.5 554 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to150MHz NO.6 555 1, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_10BIT_75to75MHz NO.7 556 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to75MHz NO.8 557 2, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_10BIT_38to38MHz NO.9 558 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_220to340MHz NO.10 559 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to220MHz NO.11 560 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_4CH_8BIT_150to150MHz NO.12 561 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_110to150MHz NO.13 562 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to110MHz NO.14 563 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_2CH_8BIT_75to75MHz NO.15 564 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_55to75MHz NO.16 565 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to55MHz NO.17 566 3, //E_PNL_SUPPORTED_LPLL_EXT_VBY1_1CH_8BIT_38to38MHz NO.18 567 }; 568 569 #endif //_LPLL_TBL_H_ 570