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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #include "MsCommon.h"
105 #include "MsIRQ.h"
106 #include "MsOS.h"
107
108 #include "MsTypes.h"
109 #include "drvBDMA.h"
110 #include "drvIIC.h"
111 #include "msAPI_Tuner.h"
112 #include "msAPI_MIU.h"
113 #include "BinInfo.h"
114 #include "halVif.h"
115
116 #include "INTERN_DVBT.h"
117 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
118 #include "InfoBlock.h"
119 #endif
120
121 #include "apiPWS.h"
122
123 #include "drvMMIO.h"
124 #include "drvAVD.h"
125
126 #define TEST_EMBEDED_DEMOD 0
127 //U8 load_data_variable=1;
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
130
131 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
132
133 // #define INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
134
135 #define MBRegBase 0x110500//0x1033C0
136 #define VDMcuBase 0x103400
137 #define DMDMcuBase 0x103460
138
139 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
140
141 #define INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
142
143 #define MBRegBase 0x112600 //Demod MailBox //mick
144 #define VDMcuBase 0x103400 //DmdMCU51 (40-4F)
145 #define DMDMcuBase 0x103480
146
147 #endif
148
149 #define DBG_INTERN_DVBT(x) //x
150 #define DBG_GET_SIGNAL(x)
151 #define DBG_DUMP_LOAD_DSP_TIME 0
152
153 //-----------------------------------------------------------------------
154 /****************************************************************
155 *Local Variables *
156 ****************************************************************/
157 //static U8 *RIUBase=NULL;
158 //static U32 RIUSize=0;
159 static BOOL FECLock=0;
160
161 //Global Variables
162 S_CMDPKTREG gsCmdPacket;
163 //U8 gCalIdacCh0, gCalIdacCh1;
164
165 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
166 code U8 INTERN_DVBT_table[] = {
167
168 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
169 #include "INTERN_DVBT_demod.dat"
170 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
171 #include "INTERN_DVBT_demod_T4.dat"
172 #endif
173 };
174
175 #endif
176
177 #if 0
178 static void INTERN_DVBT_InitRegBase(void)
179 {
180 MDrv_MMIO_GetBASE((MS_U32*)(void *)RIUBase, &RIUSize, MS_MODULE_MIU);
181 printf("address:%lx %lx\n",(MS_U32)RIUBase, RIUSize);
182 }
183 #endif
184 /***********************************************************************************
185 Subject: Delay
186 Function: INTERN_DVBT_Delayms
187 Parmeter: delay_ms : millisecs for delay
188 Return: NONE
189 Remark:
190 ************************************************************************************/
INTERN_DVBT_Delayms(U32 delay_ms)191 static void INTERN_DVBT_Delayms(U32 delay_ms)
192 {
193 MsOS_DelayTask(delay_ms);
194 }
195 //-----------------------------------------------------------------------
INTERN_DVBT_ReadReg(U16 u16Addr,U8 * pu8Data)196 BOOLEAN INTERN_DVBT_ReadReg(U16 u16Addr, U8 *pu8Data)
197 {
198 U16 u8WaitCnt=0;
199
200 // UNUSED(pu8Data);
201 if (MDrv_ReadByte(MBRegBase + 0x00))
202 {
203 printf(">> MB Busy!\n");
204 return FALSE;
205 }
206
207 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H
208 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L
209 MDrv_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode
210
211 MDrv_WriteByte(DMDMcuBase + 0x03, 0x02); // assert interrupt to DMD MCU51 //mick
212 MDrv_WriteByte(DMDMcuBase + 0x03, 0x00); // de-assert interrupt to DMD MCU51
213
214 while(MDrv_ReadByte(MBRegBase + 0x00)!= 0xFF) // wait MB_CNTL set done
215 {
216 #if TEST_EMBEDED_DEMOD
217 INTERN_DVBT_Delayms(1); // << Ken 20090629
218 #endif
219 if (u8WaitCnt++ >= 0xFF)
220 {
221 printf(">> DVBT ReadReg Fail!\n");
222 return FALSE;
223 }
224 }
225
226 *pu8Data = MDrv_ReadByte(MBRegBase + 0x03); // REG_DATA get
227 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
228
229 return TRUE;
230 }
231
232 //-----------------------------------------------------------------------
INTERN_DVBT_WriteReg(U32 u16Addr,U8 u8Data)233 BOOLEAN INTERN_DVBT_WriteReg(U32 u16Addr, U8 u8Data)
234 {
235 U16 u8WaitCnt=0;
236
237 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H
238 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L
239 MDrv_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA
240 MDrv_WriteByte(MBRegBase + 0x00, 0x02); // MB_CNTL set write mode
241
242 MDrv_WriteByte(DMDMcuBase + 0x03, 0x02); // assert interrupt to VD MCU51 //mick
243 MDrv_WriteByte(DMDMcuBase + 0x03, 0x00); // de-assert interrupt to VD MCU51
244
245 while(MDrv_ReadByte(MBRegBase + 0x00) != 0xFF) // wait done flag
246 {
247 #if TEST_EMBEDED_DEMOD
248 INTERN_DVBT_Delayms(1); // <<< Ken 20090629
249 #endif
250 if (u8WaitCnt++ >= 0xFF)
251 {
252 printf(">> DVBT WriteReg Fail!\n");
253 return FALSE;
254 }
255 }
256
257 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
258
259 return TRUE;
260 }
261
262 /***********************************************************************************
263 Subject: Command Packet Interface
264 Function: INTERN_DVBT_Cmd_Packet_Send
265 Parmeter:
266 Return: BOOLEAN
267 Remark:
268 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,U8 param_cnt)269 BOOLEAN INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, U8 param_cnt)
270 {
271 U8 status = true, indx;
272 U8 reg_val, timeout = 0;
273
274 // ==== Command Phase ===================
275 DBG_INTERN_DVBT(printf("--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
276 pCmdPacket->param[0],pCmdPacket->param[1],
277 pCmdPacket->param[2],pCmdPacket->param[3],
278 pCmdPacket->param[4],pCmdPacket->param[5] ));
279
280 // wait _BIT_END clear
281 do
282 {
283 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
284 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, ®_val);
285 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
286 reg_val = MDrv_ReadByte(MBRegBase + 0x1C);
287 #endif
288 if((reg_val & _BIT_END) != _BIT_END)
289 {
290 break;
291 }
292 MsOS_DelayTask(10);
293 if (timeout++ > 200)
294 {
295 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
296 return false;
297 }
298 } while (1);
299
300 // set cmd_3:0 and _BIT_START
301 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
302 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, ®_val);
303 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
304 status &= INTERN_DVBT_WriteReg(REG_CMD_CTRL, reg_val);
305 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
306 reg_val = MDrv_ReadByte(MBRegBase + 0x1C);
307 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
308 MDrv_WriteByte(MBRegBase + 0x1C, reg_val);
309 #endif
310
311 //DBG_INTERN_DVBT(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
312 // wait _BIT_START clear
313 do
314 {
315 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
316 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, ®_val);
317 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
318 reg_val = MDrv_ReadByte(MBRegBase + 0x1C);
319 #endif
320 if((reg_val & _BIT_START) != _BIT_START)
321 {
322 break;
323 }
324 MsOS_DelayTask(1);
325 if (timeout++ > 200)
326 {
327 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
328 return false;
329 }
330 } while (1);
331
332 // ==== Data Phase ======================
333
334 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
335 status &= INTERN_DVBT_WriteReg(REG_CMD_ADDR, 0x00);
336 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
337 MDrv_WriteByte(MBRegBase + 0x1E, 0x00);
338 #endif
339
340 for (indx = 0; indx < param_cnt; indx++)
341 {
342 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
343 status &= INTERN_DVBT_ReadReg(REG_CMD_ADDR, ®_val);
344 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
345 reg_val = MDrv_ReadByte(MBRegBase + 0x1E);
346 #endif
347 //DBG_INTERN_DVBT(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
348
349 // set param[indx] and _BIT_DRQ
350 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
351 status &= INTERN_DVBT_WriteReg(REG_CMD_DATA, pCmdPacket->param[indx]);
352 status &= INTERN_DVBT_ReadReg(REG_DTA_CTRL, ®_val);
353 status &= INTERN_DVBT_WriteReg(REG_DTA_CTRL, reg_val|_BIT_DRQ);
354
355 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
356 MDrv_WriteByte(MBRegBase + 0x1F, pCmdPacket->param[indx]);
357 reg_val = MDrv_ReadByte(MBRegBase + 0x1D);
358 MDrv_WriteByte(MBRegBase + 0x1D, reg_val|_BIT_DRQ);
359 #endif
360 // wait _BIT_DRQ clear
361 do
362 {
363 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
364 status &= INTERN_DVBT_ReadReg(REG_DTA_CTRL, ®_val);
365 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
366 reg_val = MDrv_ReadByte(MBRegBase + 0x1D);
367 #endif
368 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
369 {
370 break;
371 }
372 MsOS_DelayTask(1);
373 if (timeout++ > 200)
374 {
375 printf("---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
376 return false;
377 }
378 } while (1);
379 }
380
381 // ==== End Phase =======================
382
383 // set _BIT_END to finish command
384 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
385 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, ®_val);
386 status &= INTERN_DVBT_WriteReg(REG_CMD_CTRL, reg_val|_BIT_END);
387
388 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
389 reg_val = MDrv_ReadByte(MBRegBase + 0x1C);
390 MDrv_WriteByte(MBRegBase + 0x1C, reg_val|_BIT_END);
391 #endif
392 return status;
393 }
394
395
396 /***********************************************************************************
397 Subject: Command Packet Interface
398 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
399 Parmeter:
400 Return: BOOLEAN
401 Remark:
402 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(BOOL * cmd_done)403 BOOLEAN INTERN_DVBT_Cmd_Packet_Exe_Check(BOOL* cmd_done)
404 {
405 U8 status = true;
406 U8 reg_val;
407 U16 timeout = 0;
408
409 // wait _BIT_END clear
410 do {
411 status &= INTERN_DVBT_ReadReg(REG_CMD_CTRL, ®_val);
412
413 if((reg_val & _BIT_END) != _BIT_END)
414 break;
415
416 if (timeout++ > 200)
417 {
418 *cmd_done = false;
419 return status;
420 }
421 INTERN_DVBT_Delayms(10);
422 } while (1);
423
424 DBG_INTERN_DVBT(printf("Exe duration: %d\n", (int)timeout));
425
426 *cmd_done = true;
427 return status;
428 }
429
430 /***********************************************************************************
431 Subject: SoftStop
432 Function: INTERN_DVBT_SoftStop
433 Parmeter:
434 Return: BOOLEAN
435 Remark:
436 ************************************************************************************/
437 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
438 #else
INTERN_DVBT_SoftStop(void)439 BOOLEAN INTERN_DVBT_SoftStop ( void )
440 {
441 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
442 U16 u8WaitCnt=0;
443
444 if (MDrv_ReadByte(MBRegBase + 0x00))
445 {
446 printf(">> MB Busy!\n");
447 return FALSE;
448 }
449
450 MDrv_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
451
452 MDrv_WriteByte(DMDMcuBase + 0x03, 0x02); // assert interrupt to VD MCU51
453 MDrv_WriteByte(DMDMcuBase + 0x03, 0x00); // de-assert interrupt to VD MCU51
454
455 while(MDrv_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
456 {
457 #if TEST_EMBEDED_DEMOD
458 INTERN_DVBT_Delayms(1); // << Ken 20090629
459 #endif
460 if (u8WaitCnt++ >= 0xFF)
461 {
462 printf(">> DVBT SoftStop Fail!\n");
463 return FALSE;
464 }
465 }
466
467 //MDrv_WriteByte(0x103460, 0x01); // reset VD_MCU
468 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
469
470 #endif
471 return TRUE;
472 }
473 #endif
474
475 /***********************************************************************************
476 Subject: Reset
477 Function: INTERN_DVBT_Reset
478 Parmeter:
479 Return: BOOLEAN
480 Remark:
481 ************************************************************************************/
INTERN_DVBT_Reset(void)482 BOOLEAN INTERN_DVBT_Reset ( void )
483 {
484 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_reset\n"));
485
486 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
487 #else
488 INTERN_DVBT_SoftStop();
489 #endif
490
491 MDrv_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
492 // INTERN_DVBT_WriteReg(0x2002, 0x72); // reset DVB-T
493 INTERN_DVBT_Delayms(5);
494 // INTERN_DVBT_WriteReg(0x2002, 0x52);
495 MDrv_WriteByte(DMDMcuBase + 0x00, 0x00);
496 INTERN_DVBT_Delayms(5);
497 FECLock = FALSE;
498 return TRUE;
499 }
500
501 /***********************************************************************************
502 Subject: Exit
503 Function: INTERN_DVBT_Exit
504 Parmeter:
505 Return: BOOLEAN
506 Remark:
507 ************************************************************************************/
INTERN_DVBT_Exit(void)508 BOOLEAN INTERN_DVBT_Exit ( void )
509 {
510 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
511 // Mapi_PWS_Stop_VDMCU();
512 #else
513 INTERN_DVBT_SoftStop();
514
515
516 //diable clk gen
517 //MDrv_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
518 //MDrv_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
519
520 MDrv_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
521 MDrv_WriteByte(0x10330b, 0x00);
522
523 MDrv_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
524 MDrv_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
525
526 MDrv_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
527 MDrv_WriteByte(0x10330f, 0x00);
528
529 MDrv_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
530 MDrv_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
531
532 MDrv_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
533 MDrv_WriteByte(0x103313, 0x00);
534
535 MDrv_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
536 MDrv_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
537
538 MDrv_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
539 MDrv_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
540
541 MDrv_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
542 MDrv_WriteByte(0x103319, 0x11);
543
544 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
545 MDrv_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
546
547 //#if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
548 // MDrv_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 -> 0x02
549 //#endif
550
551 if(MDrv_Read2Byte(0x001ECC) == 0x000F) // T3
552 {
553 MDrv_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
554 }
555
556 #endif
557
558 return TRUE;
559 }
560
561 /***********************************************************************************
562 Subject: Load DSP code to chip
563 Function: INTERN_DVBT_LoadDSPCode
564 Parmeter:
565 Return: BOOLEAN
566 Remark:
567 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)568 static BOOLEAN INTERN_DVBT_LoadDSPCode(void)
569 {
570 U8 udata = 0x00;
571 U16 i;
572 U16 fail_cnt=0;
573
574 #if (DBG_DUMP_LOAD_DSP_TIME==1)
575 U32 u32Time;
576 #endif
577
578 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
579 BININFO BinInfo;
580 BOOLEAN bResult;
581 U32 u32GEAddr;
582 U8 Data;
583 S8 op;
584 U32 srcaddr;
585 U32 len;
586 U32 SizeBy4K;
587 U16 u16Counter=0;
588 U8 *pU8Data;
589 #endif
590
591 #if 0
592 if(MDrv_ReadByte(0x101E3E))
593 {
594 printf("Warring! Reg[0x101E3E]=%d\n", MDrv_ReadByte(0x101E3E));
595 return FALSE;
596 }
597 #endif
598
599 MDrv_Sys_DisableWatchDog();
600
601 MDrv_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
602 MDrv_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
603 MDrv_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
604 MDrv_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
605 MDrv_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
606 MDrv_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
607
608 //// Load code thru VDMCU_IF ////
609 DBG_INTERN_DVBT(printf(">Load Code...\n"));
610 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
611 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
612 {
613 MDrv_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
614 }
615 #else
616 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
617 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
618 if ( bResult != PASS )
619 {
620 return FALSE;
621 }
622 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
623
624 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
625 InfoBlock_Flash_2_Checking_Start(&BinInfo);
626 #endif
627
628 #if OBA2
629 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
630 #else
631 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
632 #endif
633
634 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
635 InfoBlock_Flash_2_Checking_End(&BinInfo);
636 #endif
637
638 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
639 SizeBy4K=BinInfo.B_Len/0x1000;
640 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
641
642 #if (DBG_DUMP_LOAD_DSP_TIME==1)
643 u32Time = msAPI_Timer_GetTime0();
644 #endif
645
646 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
647
648 for (i=0;i<=SizeBy4K;i++)
649 {
650 if(i==SizeBy4K)
651 len=BinInfo.B_Len%0x1000;
652 else
653 len=0x1000;
654
655 srcaddr = u32GEAddr+(0x1000*i);
656 //printf("\t i = %08X\n", i);
657 //printf("\t len = %08X\n", len);
658 op = 1;
659 u16Counter = 0 ;
660 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
661 while(len--)
662 {
663 u16Counter ++ ;
664 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
665 //pU8Data = (U8 *)(srcaddr|0x80000000);
666 #if OBA2
667 pU8Data = (U8 *)(srcaddr);
668 #else
669 pU8Data = (U8 *)(srcaddr|0x80000000);
670 #endif
671 Data = *pU8Data;
672
673 #if 0
674 if(u16Counter < 0x100)
675 printf("0x%bx,", Data);
676 #endif
677 MDrv_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
678
679 srcaddr += op;
680 }
681 // printf("\n\n\n");
682 }
683
684 #if (DBG_DUMP_LOAD_DSP_TIME==1)
685 printf("------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
686 #endif
687
688 #endif
689
690 //// Content verification ////
691 DBG_INTERN_DVBT(printf(">Verify Code...\n"));
692
693 MDrv_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
694 MDrv_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
695
696 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
697 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
698 {
699 udata = MDrv_ReadByte(DMDMcuBase + 0x10); // read sram data
700 if (udata != INTERN_DVBT_table[i])
701 {
702 printf(">fail add = 0x%x\n", i);
703 printf(">code = 0x%x\n", INTERN_DVBT_table[i]);
704 printf(">data = 0x%x\n", udata);
705
706 if (fail_cnt++ > 10)
707 {
708 printf(">DVB-T DSP Loadcode fail!");
709 return false;
710 }
711 }
712 }
713 #else
714 for (i=0;i<=SizeBy4K;i++)
715 {
716 if(i==SizeBy4K)
717 len=BinInfo.B_Len%0x1000;
718 else
719 len=0x1000;
720
721 srcaddr = u32GEAddr+(0x1000*i);
722 //printf("\t i = %08LX\n", i);
723 //printf("\t len = %08LX\n", len);
724 op = 1;
725 u16Counter = 0 ;
726 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
727 while(len--)
728 {
729 u16Counter ++ ;
730 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
731 //pU8Data = (U8 *)(srcaddr|0x80000000);
732 #if OBA2
733 pU8Data = (U8 *)(srcaddr);
734 #else
735 pU8Data = (U8 *)(srcaddr|0x80000000);
736 #endif
737 Data = *pU8Data;
738
739 #if 0
740 if(u16Counter < 0x100)
741 printf("0x%bx,", Data);
742 #endif
743 udata = MDrv_ReadByte(DMDMcuBase + 0x10); // read sram data
744 if (udata != Data)
745 {
746 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
747 printf(">code = 0x%x\n", Data);
748 printf(">data = 0x%x\n", udata);
749
750 if (fail_cnt++ > 10)
751 {
752 printf(">DVB-T DSP Loadcode fail!");
753 return false;
754 }
755 }
756
757 srcaddr += op;
758 }
759 // printf("\n\n\n");
760 }
761 #endif
762
763 MDrv_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
764 MDrv_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
765 MDrv_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
766 MDrv_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
767
768 DBG_INTERN_DVBT(printf(">DSP Loadcode done."));
769 //while(load_data_variable);
770
771 if(MDrv_Read2Byte(0x001ECC) == 0x000F) // chip_id == T3
772 {
773 MDrv_WriteByte(0x101E3E, 0x02); // DVBT = BIT1 -> 0x02
774 }
775
776 return TRUE;
777 }
778
779 /***********************************************************************************
780 Subject: DVB-T CLKGEN initialized function
781 Function: INTERN_DVBT_Power_On_Initialization
782 Parmeter:
783 Return: BOOLEAN
784 Remark:
785 ************************************************************************************/
INTERN_DVBT_InitClkgen(void)786 void INTERN_DVBT_InitClkgen(void)
787 {
788 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
789 //<<CLK_GEN1_DVB_t >>
790 if ( MDrv_ReadByte( 0x001ecf) == 0x00 )
791 MDrv_WriteByte(0x100b42, 0x10); // reg_ckg_vdmcu@0x21[4:0] (bank_CLKGEN0) //108MHz
792 else //after t3_u02
793 MDrv_WriteByte(0x100b42, 0x0D); // reg_ckg_vdmcu@0x21[4:0] (bank_CLKGEN0) //108MHz
794
795 MDrv_WriteByte(0x100b43, 0x01); // reg_ckg_vd200@0x21[11:8]
796
797 MDrv_WriteByte(0x100b44, 0x00); // enable mail-box clock (bank_CLKGEN0)
798 MDrv_WriteByte(0x100b45, 0x00); // enable mail-box clock
799
800 MDrv_WriteByte(0x103314, 0x00); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
801 MDrv_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
802
803 MDrv_WriteByte(0x10330a, 0x00); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
804 MDrv_WriteByte(0x10330b, 0x00);
805
806 MDrv_WriteByte(0x10330c, 0x00); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
807 MDrv_WriteByte(0x10330d, 0x00); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
808
809 MDrv_WriteByte(0x10330e, 0x00); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
810 MDrv_WriteByte(0x10330f, 0x00);
811
812 MDrv_WriteByte(0x103310, 0x00); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
813 MDrv_WriteByte(0x103311, 0x00); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
814
815 MDrv_WriteByte(0x103312, 0x00); // dvbt_t:0x0000, dvb_c: 0x0004
816 MDrv_WriteByte(0x103313, 0x00);
817
818 MDrv_WriteByte(0x103314, 0x00); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
819 MDrv_WriteByte(0x103315, 0x00); // reg_ckg_dvbtc_innc@0x0a[11:8]
820
821 MDrv_WriteByte(0x103316, 0x00); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
822 MDrv_WriteByte(0x103317, 0x00); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
823
824 MDrv_WriteByte(0x103318, 0x00); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
825 MDrv_WriteByte(0x103319, 0x00);
826
827 #if 0 //parallel
828 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
829 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
830
831 MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 /serial mode 0x0400
832
833 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
834 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
835 #else
836 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
837 #endif
838
839 #else // serial
840 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
841 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
842
843 MDrv_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
844 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
845 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
846 #else
847 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
848 #endif
849 #endif
850 //MDrv_WriteByte(0x101e22, 0x02); // internal TS connect to TS0:0x0002; to TS1:0x0200
851 //MDrv_WriteByte(0x101e23, 0x00); // reg_ts0~1_mux@0x11 (bank_CHIP)
852
853 //MDrv_WriteByte(0x100b50, 0x08); // internal TS0:0x0108; internal TS1:0x0801
854 //MDrv_WriteByte(0x100b51, 0x08); // reg_ckg_ts0~1@0x28 (bank_CLKGEN0) << Ken 20090629
855
856 MDrv_WriteByte(0x101e04, 0x00); // reg_if_agc_pad_oen@0x02 (bank_CHIP)
857 MDrv_WriteByte(0x101e05, 0x00);
858
859 //----------------------------------------------------------------------------------------
860 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
861 //<<CLK_GEN1_DVB_t >>
862
863 MDrv_WriteByte(0x10331e, 0x10); // reg_ckg_dmdmcu@0x21[4:0] (bank_CLKGEN0) //108MHz
864
865 MDrv_WriteByte(0x103480, 0x00); // release dmdmcu_rst
866
867 MDrv_WriteByte(0x103314, 0x00); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
868 MDrv_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
869
870 MDrv_WriteByte(0x10330a, 0x00); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
871 MDrv_WriteByte(0x10330b, 0x00);
872
873 MDrv_WriteByte(0x10330c, 0x00); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
874 MDrv_WriteByte(0x10330d, 0x00); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
875
876 MDrv_WriteByte(0x10330e, 0x00); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
877 MDrv_WriteByte(0x10330f, 0x00);
878
879 MDrv_WriteByte(0x103310, 0x00); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
880 MDrv_WriteByte(0x103311, 0x00); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
881
882 MDrv_WriteByte(0x103312, 0x00); // dvbt_t:0x0000, dvb_c: 0x0004
883 MDrv_WriteByte(0x103313, 0x00);
884
885 MDrv_WriteByte(0x103314, 0x00); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
886 MDrv_WriteByte(0x103315, 0x00); // reg_ckg_dvbtc_innc@0x0a[11:8]
887
888 MDrv_WriteByte(0x103316, 0x00); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
889 MDrv_WriteByte(0x103317, 0x00); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
890
891 MDrv_WriteByte(0x103318, 0x00); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
892 MDrv_WriteByte(0x103319, 0x00);
893
894 #if 0 //parallel
895 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
896 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
897
898 MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 /serial mode 0x0400
899
900 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
901 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
902 #else
903 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
904 #endif
905 #else // serial
906 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
907 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
908
909 MDrv_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
910 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
911 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
912 #else
913 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
914 #endif
915 #endif
916 // !!!
917 //MDrv_WriteByte(0x101e22, 0x02); // internal TS connect to TS0:0x0002; to TS1:0x0200
918 //MDrv_WriteByte(0x101e23, 0x00); // reg_ts0~1_mux@0x11 (bank_CHIP)
919
920 //MDrv_WriteByte(0x100b50, 0x08); // internal TS0:0x0108; internal TS1:0x0801
921 //MDrv_WriteByte(0x100b51, 0x01); // reg_ckg_ts0~1@0x28 (bank_CLKGEN0) << Ken 20090629
922 // !!!
923 MDrv_WriteByte(0x101e04, 0x00); // reg_if_agc_pad_oen@0x02 (bank_CHIP)
924 MDrv_WriteByte(0x101e05, 0x00);
925
926 //----------------------------------------
927 //For T4 Add
928 //At Chip Top
929 MDrv_WriteByte(0x101e9e, MDrv_ReadByte(0x101e9e) & 0x3F); // Bit6,7 Clean=0
930 // MDrv_WriteByte(0x101e9e, 0x00); // reg_agcgctrl
931 // MDrv_WriteByte(0x101e9f, 0x00);
932
933 MDrv_WriteByte(0x101e05, MDrv_ReadByte(0x101e05) & 0xEF); // Bit12 Clean=0
934 // MDrv_WriteByte(0x101e04, 0x00); // reg_if_agc_pad_oen
935 // MDrv_WriteByte(0x101e05, 0x00);
936
937 MDrv_WriteByte(0x101eA1, MDrv_ReadByte(0x101eA1) & 0x7F); // Bit15 Clean=0
938 // MDrv_WriteByte(0x101eA0, 0x00); // reg_allpad_in
939 // MDrv_WriteByte(0x101eA1, 0x00);
940 // ---------------------------------------
941 MDrv_WriteByte(0x112002, 0x52); // wreg vdbank_DEMOD_0+0x01 0052
942 MDrv_WriteByte(0x112003, 0x00); // Release Ana misc resest
943
944 MDrv_WriteByte(0x112060, 0x00); // ADC sign bit
945 MDrv_WriteByte(0x112061, 0x00);
946
947 MDrv_WriteByte(0x112064, 0x00); // ADC I channel offset // wreg vdbank_DEMOD_0+0x32 0c00
948 MDrv_WriteByte(0x112065, 0x0c);
949
950 MDrv_WriteByte(0x112066, 0x00); // ADC Q channel offset
951 MDrv_WriteByte(0x112067, 0x0c);
952 // ---------------------------------------
953 // Enable DVBT demod (MailBox=0x1020)
954 MDrv_WriteByte(0x112818, 0x03); // Set enable ADC clock [ANA_PWDN_ADCI]
955 MDrv_WriteByte(0x112819, 0x00); // wreg vdbank_DMD_ANA_MISC+0x0c 0x0000
956 INTERN_DVBT_Delayms(2);
957
958 MDrv_WriteByte(0x11286a, 0x86); // wreg vdbank_DMD_ANA_MISC+0x35 0x1e04
959 MDrv_WriteByte(0x11286b, 0x1e); // [ANA_MPLL_ICTRL]
960 INTERN_DVBT_Delayms(2);
961
962 // ---------------------------------------------------------------------
963 // DVBT , DVBC Clock Setting
964 // ---------------------------------------------------------------------
965 MDrv_WriteByte(0x11286a, 0x06); // Reset MPLL
966 MDrv_WriteByte(0x11286b, 0x1e); // wreg vdbank_DMD_ANA_MISC+0x35 0x1e04
967 INTERN_DVBT_Delayms(2);
968
969 MDrv_WriteByte(0x11286a, 0x06); // Disable MPLL reset
970 MDrv_WriteByte(0x11286b, 0x06); // wreg vdbank_DMD_ANA_MISC+0x35 0x0604
971 INTERN_DVBT_Delayms(2);
972
973 MDrv_WriteByte(0x112866, 0x02); // Set MPLL_LOOP_DIV_FIRST and SECOND
974 MDrv_WriteByte(0x112867, 0x09); // [ANA_MPLL_LOOP_DIV_FIRST]
975
976 MDrv_WriteByte(0x112860, 0x00); // Set MPLL_ADC_DIV_SEL [ANA_MPLL_CLK_DP_PD]
977 MDrv_WriteByte(0x112861, 0x13); // wreg vdbank_DMD_ANA_MISC+0x30 0x1300
978
979 MDrv_WriteByte(0x112802, 0x40); // Set IMUXS QMUXS [ANA_ADC_PWDNI]
980 MDrv_WriteByte(0x112803, 0x04); // wreg vdbank_DMD_ANA_MISC+0x01 0x0440
981
982 MDrv_WriteByte(0x112818, 0x00); // Set enable ADC clock [ANA_PWDN_ADCI]
983 MDrv_WriteByte(0x112819, 0x00); // wreg vdbank_DMD_ANA_MISC+0x0c 0x0000
984
985 MDrv_WriteByte(0x112840, 0x86); // Disable PWDN_REF [ANA_VCLP]
986 MDrv_WriteByte(0x112841, 0x1e); // wreg vdbank_DMD_ANA_MISC+0x20 0x0000
987 #endif
988 }
989
990 /***********************************************************************************
991 Subject: Power on initialized function
992 Function: INTERN_DVBT_Power_On_Initialization
993 Parmeter:
994 Return: BOOLEAN
995 Remark:
996 ************************************************************************************/
997
INTERN_DVBT_Power_On_Initialization(void)998 BOOLEAN INTERN_DVBT_Power_On_Initialization ( void )
999 {
1000 U8 status = true;
1001 //U8 cal_done;
1002
1003 //INTERN_DVBT_InitRegBase();
1004 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
1005 printf("INTERN_DVBT_Power_On_Initialization call stop vdmcu\n");
1006 #if ENABLE_PWS
1007 Mapi_PWS_Stop_VDMCU();
1008 #endif
1009 #endif
1010
1011 INTERN_DVBT_InitClkgen();
1012
1013 //// Firmware download //////////
1014 DBG_INTERN_DVBT(printf("INTERN_DVBT Load DSP...\n"));
1015 //MsOS_DelayTask(100);
1016
1017 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
1018 if (MDrv_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1019 {
1020 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1021 {
1022 printf("DVB-T Load DSP Code Fail\n");
1023 return FALSE;
1024 }
1025 else
1026 {
1027 printf("DVB-T Load DSP Code OK\n");
1028 }
1029 }
1030 #elif ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD ) //T4
1031
1032 extern BOOLEAN devCOFDM_WriteReg(U16 RegAddr, U16 RegData);
1033
1034 //reset VIF setting to avoid affect demod
1035 devCOFDM_WriteReg(0x2200, 0xFF);
1036 devCOFDM_WriteReg(0x2204, 0x00);
1037
1038 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1039 {
1040 printf("DVB-T Load DSP Code Fail\n");
1041 return FALSE;
1042 }
1043 else
1044 {
1045 printf("DVB-T Load DSP Code OK\n");
1046 }
1047 #endif
1048
1049 #if 0
1050 //// MCU Reset //////////
1051 DBG_INTERN_DVBT(printf("INTERN_DVBT Reset...\n"));
1052 if (INTERN_DVBT_Reset() == FALSE)
1053 {
1054 DBG_INTERN_DVBT(printf("Fail\n"));
1055 return FALSE;
1056 }
1057 else
1058 {
1059 DBG_INTERN_DVBT(printf("OK\n"));
1060 }
1061 #endif
1062
1063 // INTERN_DVBT_ReadReg(0x8000, &gu8ChipRevId);
1064 // DBG_INTERN_DVBT(printf("DVB-T RevID:%bx\n", gu8ChipRevId));
1065
1066 //// DAC calibration //////////
1067 // DBG_INTERN_DVBT(printf("INTERN_DVBT Cal DAC...\n"));
1068 //
1069 // gsCmdPacket.cmd_code = CMD_DAC_CALI;
1070 // gsCmdPacket.param[dac_op_code] = DAC_RUN_CALI;
1071 // status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1072 // status &= INTERN_DVBT_Cmd_Packet_Exe_Check(&cal_done);
1073 // if (cal_done == true)
1074 // {
1075 // DBG_INTERN_DVBT(printf("OK\n"));
1076 // status &= INTERN_DVBT_ReadReg(0x81A8, &gCalIdacCh0);
1077 // status &= INTERN_DVBT_ReadReg(0x81A9, &gCalIdacCh1);
1078 // }
1079 // else
1080 // {
1081 // gCalIdacCh0 = gCalIdacCh1 = 0;
1082 // DBG_INTERN_DVBT(printf("FAIL\n"));
1083 // }
1084
1085 return status;
1086 }
1087
1088 /************************************************************************************************
1089 Subject: Driving control
1090 Function: INTERN_DVBT_Driving_Control
1091 Parmeter: bInversionEnable : TRUE For High
1092 Return: void
1093 Remark:
1094 *************************************************************************************************/
INTERN_DVBT_Driving_Control(BOOLEAN bEnable)1095 void INTERN_DVBT_Driving_Control(BOOLEAN bEnable)
1096 {
1097 U8 u8Temp;
1098
1099 u8Temp = MDrv_ReadByte(0x101E10);
1100
1101 if (bEnable)
1102 {
1103 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1104 }
1105 else
1106 {
1107 u8Temp = u8Temp & (~0x01);
1108 }
1109
1110 DBG_INTERN_DVBT(printf("---> INTERN_DVBT_Driving_Control(Bit0) = 0x%bx \n",u8Temp));
1111 MDrv_WriteByte(0x101E10, u8Temp);
1112 }
1113 /************************************************************************************************
1114 Subject: Clk Inversion control
1115 Function: INTERN_DVBT_Clk_Inversion_Control
1116 Parmeter: bInversionEnable : TRUE For Inversion Action
1117 Return: void
1118 Remark:
1119 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(BOOLEAN bInversionEnable)1120 void INTERN_DVBT_Clk_Inversion_Control(BOOLEAN bInversionEnable)
1121 {
1122 U8 u8Temp;
1123
1124 u8Temp = MDrv_ReadByte(0x103301);
1125
1126 if (bInversionEnable)
1127 {
1128 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1129 }
1130 else
1131 {
1132 u8Temp = u8Temp & (~0x02);
1133 }
1134
1135 DBG_INTERN_DVBT(printf("---> Inversion(Bit9) = 0x%bx \n",u8Temp));
1136 MDrv_WriteByte(0x103301, u8Temp);
1137 }
1138 /************************************************************************************************
1139 Subject: Transport stream serial/parallel control
1140 Function: INTERN_DVBT_Serial_Control
1141 Parmeter: bEnable : TRUE For serial
1142 Return: BOOLEAN :
1143 Remark:
1144 *************************************************************************************************/
INTERN_DVBT_Serial_Control(BOOLEAN bEnable)1145 BOOLEAN INTERN_DVBT_Serial_Control(BOOLEAN bEnable)
1146 {
1147 U8 status = true;
1148
1149 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_ts... \n"));
1150
1151 if (bEnable) //Serial mode for TS pad
1152 {
1153 // serial
1154 MDrv_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1155 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1156
1157 MDrv_WriteByte(0x103300, 0x00); // serial mode 0x0400
1158 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1159 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1160 #else
1161 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
1162 #endif
1163 MDrv_WriteByte(0x101EA5, MDrv_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1164
1165 //// INTERN_DVBT TS Control: Serial //////////
1166 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1167
1168 gsCmdPacket.param[0] = TS_SERIAL;
1169 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1170 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1171 #else
1172 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1173 #endif
1174 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1175 }
1176 else
1177 {
1178 //parallel
1179 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1180 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1181
1182 //MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1183 MDrv_WriteByte(0x103300, 0x13); // parallel mode: 0x0513 => ts_clk=288/(2*(0x13+1))=7.2MHz
1184 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1185 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1186 #else
1187 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1188 #endif
1189 MDrv_WriteByte(0x101EA5, MDrv_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1190
1191 //// INTERN_DVBT TS Control: Parallel //////////
1192 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1193
1194 gsCmdPacket.param[0] = TS_PARALLEL;
1195 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1196 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1197 #else
1198 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1199 #endif
1200 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1201 }
1202
1203 DBG_INTERN_DVBT(printf("---> Inversion(Bit5) = 0x%bx \n",gsCmdPacket.param[1] ));
1204
1205 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1206 return status;
1207 }
1208
1209
1210 /************************************************************************************************
1211 Subject: channel change config
1212 Function: INTERN_DVBT_Config
1213 Parmeter: BW: bandwidth
1214 Return: BOOLEAN :
1215 Remark:
1216 *************************************************************************************************/
INTERN_DVBT_Config(RF_CHANNEL_BANDWIDTH BW,BOOLEAN bSerialTS,BOOLEAN bPalBG)1217 BOOLEAN INTERN_DVBT_Config ( RF_CHANNEL_BANDWIDTH BW, BOOLEAN bSerialTS, BOOLEAN bPalBG)
1218 {
1219 U16 fs, fc;
1220 U8 bandwidth;
1221 U8 status = true;
1222
1223 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_config\n"));
1224
1225 fs = 45473;
1226 fc = fs - 36167;
1227
1228 switch(BW)
1229 {
1230 /* no provided
1231 case E_RF_CH_BAND_5MHz:
1232 bandwidth = 0;
1233 break;
1234 */
1235 case E_RF_CH_BAND_6MHz:
1236 bandwidth = 1;
1237 break;
1238 case E_RF_CH_BAND_7MHz:
1239 bandwidth = 2;
1240 break;
1241 case E_RF_CH_BAND_8MHz:
1242 default:
1243 bandwidth = 3;
1244 break;
1245 }
1246
1247 status &= INTERN_DVBT_Reset();
1248
1249 //// INTERN_DVBT system init: DVB-T //////////
1250 gsCmdPacket.cmd_code = CMD_SYSTEM_INIT;
1251
1252 gsCmdPacket.param[0] = E_SYS_DVBT;
1253 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1254
1255 //// DVB-T configurate ///////////////////
1256 gsCmdPacket.cmd_code = CMD_DVBT_CONFIG;
1257
1258 gsCmdPacket.param[p_opmode_rfagc_en] = 0;
1259 gsCmdPacket.param[p_opmode_humdet_en] = 0;
1260 gsCmdPacket.param[p_opmode_dcr_en] = 1;
1261 gsCmdPacket.param[p_opmode_iqb_en] = 0;
1262 gsCmdPacket.param[p_opmode_auto_iq_swap] = 1;
1263 gsCmdPacket.param[p_opmode_auto_fsa_left] = 1;
1264 gsCmdPacket.param[p_opmode_auto_rfmax] = 0;
1265 gsCmdPacket.param[p_opmode_mode_forced] = 0;
1266 gsCmdPacket.param[p_opmode_cp_forced] = 0;
1267 gsCmdPacket.param[pc_config_rssi] = 0;
1268 gsCmdPacket.param[pc_config_zif] = 0;
1269 gsCmdPacket.param[pc_config_fc_l] = (U8)(fc%256); //0x5a;
1270 gsCmdPacket.param[pc_config_fc_h] = (U8)(fc/256); //0x24;
1271 gsCmdPacket.param[pc_config_fs_l] = (U8)(fs%256); //0xa1;
1272 gsCmdPacket.param[pc_config_fs_h] = (U8)(fs/256); //0xb1;
1273 gsCmdPacket.param[pc_config_bw] = bandwidth;
1274 gsCmdPacket.param[pc_config_fsa_left] = 0;
1275 gsCmdPacket.param[pc_config_rfmax] = 1;
1276 gsCmdPacket.param[pc_config_lp_sel] = 0;
1277 gsCmdPacket.param[pc_config_cp] = 3;
1278 gsCmdPacket.param[pc_config_mode] = 1;
1279 gsCmdPacket.param[pc_config_iq_swap] = 0; //mick iq swap
1280 gsCmdPacket.param[pc_config_atv_system] = bPalBG? 0:1;
1281 gsCmdPacket.param[pc_config_serial_ts] = bSerialTS;
1282 gsCmdPacket.param[pc_config_data_swap] = 0;
1283 gsCmdPacket.param[pc_config_icfo_range] = 1;
1284
1285 if (bSerialTS)
1286 {
1287 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1288 gsCmdPacket.param[pc_config_ts_out_inv] = false;
1289 #else
1290 gsCmdPacket.param[pc_config_ts_out_inv] = true;
1291 #endif
1292 }
1293 else
1294 {
1295 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1296 gsCmdPacket.param[pc_config_ts_out_inv] = false;
1297 #else
1298 gsCmdPacket.param[pc_config_ts_out_inv] = true;
1299 #endif
1300 }
1301 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, DVBT_PARAM_LEN);
1302
1303 #if (FRONTEND_TUNER_TYPE == LG_TDTC_G311D_TUNER)
1304 gsCmdPacket.cmd_code = CMD_TUNED_VALUE;
1305 gsCmdPacket.param[agc_ref_small] = 168;
1306 gsCmdPacket.param[agc_ref_large] = 248;
1307 gsCmdPacket.param[agc_ref_aci] = 150;
1308 gsCmdPacket.param[ripple_switch_th_l] = 0xCD; //461 (0.90)
1309 gsCmdPacket.param[ripple_switch_th_h] = 0x01;
1310 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, TUNED_PARAM_MAX_NUM);
1311 #endif
1312
1313 if(bSerialTS)
1314 {
1315 // serial
1316 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1317 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1318
1319 MDrv_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1320 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1321 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1322 #else
1323 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
1324 #endif
1325 }
1326 else
1327 {
1328 //parallel
1329 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1330 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1331
1332 //MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1333 MDrv_WriteByte(0x103300, 0x13); // parallel mode: 0x0513 => ts_clk=288/(2*(0x13+1))=7.2MHz
1334 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1335 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1336 #else
1337 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1338 #endif
1339 }
1340 return status;
1341 }
1342 /************************************************************************************************
1343 Subject: enable hw to lock channel
1344 Function: INTERN_DVBT_Active
1345 Parmeter: bEnable
1346 Return: BOOLEAN
1347 Remark:
1348 *************************************************************************************************/
INTERN_DVBT_Active(BOOLEAN bEnable)1349 BOOLEAN INTERN_DVBT_Active(BOOLEAN bEnable)
1350 {
1351 U8 status = true;
1352
1353 DBG_INTERN_DVBT(printf(" @INTERN_DVBT_active\n"));
1354
1355 //// INTERN_DVBT Finite State Machine on/off //////////
1356 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1357
1358 gsCmdPacket.param[0] = (U8)bEnable;
1359 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1360
1361 return status;
1362 }
1363 /************************************************************************************************
1364 Subject: Return lock status
1365 Function: INTERN_DVBT_Lock
1366 Parmeter: eStatus :
1367 Return: BOOLEAN
1368 Remark:
1369 *************************************************************************************************/
INTERN_DVBT_Lock(COFDM_LOCK_STATUS eStatus)1370 BOOLEAN INTERN_DVBT_Lock( COFDM_LOCK_STATUS eStatus )
1371 {
1372 U16 u16Address;
1373 BYTE cData;
1374 BYTE cBitMask;
1375
1376 static U32 u32FecLockTime;
1377
1378 switch( eStatus )
1379 {
1380 case COFDM_FEC_LOCK:
1381 INTERN_DVBT_ReadReg(0x23E0, &cData);
1382 if (cData == 0x0B)
1383 {
1384 u32FecLockTime = MsOS_GetSystemTime();
1385 FECLock = TRUE;
1386 //printf("dmd_lock\n");
1387
1388 return TRUE;
1389 }
1390 else
1391 {
1392 if (FECLock == TRUE)
1393 {
1394 if ( ( MsOS_GetSystemTime() - u32FecLockTime ) < 3000 )
1395 return TRUE;
1396 }
1397 FECLock = FALSE;
1398 //printf("dmd_unlock\n");
1399 return FALSE; // continuously un-lock
1400 }
1401 break;
1402
1403 case COFDM_PSYNC_LOCK:
1404 u16Address = 0x232C; //FEC: P-sync Lock,
1405 cBitMask = BIT1;
1406 break;
1407
1408 case COFDM_TPS_LOCK:
1409 u16Address = 0x2222; //TPS Lock,
1410 cBitMask = BIT1;
1411 break;
1412
1413 case COFDM_DCR_LOCK:
1414 u16Address = 0x2145; //DCR Lock,
1415 cBitMask = BIT0;
1416 break;
1417
1418 case COFDM_AGC_LOCK:
1419 u16Address = 0x212F; //AGC Lock,
1420 cBitMask = BIT0;
1421 break;
1422
1423 case COFDM_MODE_DET:
1424 u16Address = 0x24CF; //Mode CP Detect,
1425 cBitMask = BIT4;
1426 break;
1427
1428 default:
1429 return FALSE;
1430 }
1431
1432 if (INTERN_DVBT_ReadReg(u16Address, &cData) == FALSE)
1433 return FALSE;
1434
1435 if ((cData & cBitMask) == cBitMask)
1436 {
1437 return TRUE;
1438 }
1439
1440 return FALSE;
1441
1442 }
1443
1444 /****************************************************************************
1445 Subject: To get the Post viterbi BER
1446 Function: INTERN_DVBT_GetPostViterbiBer
1447 Parmeter: Quility
1448 Return: E_RESULT_SUCCESS
1449 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1450 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1451 We will not read the Period, and have the "/256/8"
1452 *****************************************************************************/
INTERN_DVBT_GetPostViterbiBer(float * ber)1453 BOOLEAN INTERN_DVBT_GetPostViterbiBer(float *ber)
1454 {
1455 U8 status = true;
1456 U8 reg, reg_frz;
1457 U16 BitErrPeriod;
1458 U32 BitErr;
1459 U16 PktErr;
1460
1461 /////////// Post-Viterbi BER /////////////
1462
1463 // bank 7 0x32 [7] reg_bit_err_num_freeze
1464 status &= INTERN_DVBT_ReadReg(0x2332, ®_frz);
1465 status &= INTERN_DVBT_WriteReg(0x2332, reg_frz|0x80);
1466
1467 // bank 7 0x30 [7:0] reg_bit_err_sblprd_7_0
1468 // [15:8] reg_bit_err_sblprd_15_8
1469 status &= INTERN_DVBT_ReadReg(0x2331, ®);
1470 BitErrPeriod = reg;
1471
1472 status &= INTERN_DVBT_ReadReg(0x2330, ®);
1473 BitErrPeriod = (BitErrPeriod << 8)|reg;
1474
1475 // bank 7 0x3a [7:0] reg_bit_err_num_7_0
1476 // [15:8] reg_bit_err_num_15_8
1477 // bank 7 0x3c [7:0] reg_bit_err_num_23_16
1478 // [15:8] reg_bit_err_num_31_24
1479
1480 status &= INTERN_DVBT_ReadReg(0x233D, ®);
1481 BitErr = reg;
1482
1483 status &= INTERN_DVBT_ReadReg(0x233C, ®);
1484 BitErr = (BitErr << 8)|reg;
1485
1486 status &= INTERN_DVBT_ReadReg(0x233B, ®);
1487 BitErr = (BitErr << 8)|reg;
1488
1489 status &= INTERN_DVBT_ReadReg(0x233A, ®);
1490 BitErr = (BitErr << 8)|reg;
1491
1492 // bank 7 0x3e [7:0] reg_uncrt_pkt_num_7_0
1493 // [15:8] reg_uncrt_pkt_num_15_8
1494 status &= INTERN_DVBT_ReadReg(0x233F, ®);
1495 PktErr = reg;
1496
1497 status &= INTERN_DVBT_ReadReg(0x233E, ®);
1498 PktErr = (PktErr << 8)|reg;
1499
1500 // bank 7 0x32 [7] reg_bit_err_num_freeze
1501 status &= INTERN_DVBT_WriteReg(0x2332, reg_frz);
1502
1503 if (BitErrPeriod == 0 ) //protect 0
1504 BitErrPeriod = 1;
1505
1506 if (BitErr <=0 )
1507 *ber = 0.5 / ((float)BitErrPeriod*128*188*8);
1508 else
1509 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1510
1511
1512 DBG_GET_SIGNAL(printf("INTERN_DVBT PostVitBER = %8.3e \n ", *ber));
1513 DBG_GET_SIGNAL(printf("INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1514
1515
1516 return status;
1517 }
1518
1519 /****************************************************************************
1520 Subject: Function providing approx. result of Log10(X)
1521 Function: Log10Approx
1522 Parmeter: Operand X in float
1523 Return: Approx. value of Log10(X) in float
1524 Remark: Ouput range from 0.0, 0.3 to 9.6 (input 1 to 2^32)
1525 *****************************************************************************/
Log10Approx(float flt_x)1526 float Log10Approx(float flt_x)
1527 {
1528 U32 u32_temp = 1;
1529 U8 indx = 0;
1530
1531 do {
1532 u32_temp = u32_temp << 1;
1533 if (flt_x < (float)u32_temp)
1534 break;
1535 }while (++indx < 32);
1536
1537 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
1538 return (float)0.3 * indx;
1539 }
1540
1541 /****************************************************************************
1542 Subject: Read the signal to noise ratio (SNR)
1543 Function: INTERN_DVBT_GetSNR
1544 Parmeter: None
1545 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1546 Remark:
1547 *****************************************************************************/
INTERN_DVBT_GetSNR(void)1548 float INTERN_DVBT_GetSNR (void)
1549 {
1550 U8 status = true;
1551 U8 reg, reg_frz;
1552 U32 noise_power;
1553 float snr;
1554
1555 // bank 6 0xfe [0] reg_fdp_freeze
1556 status &= INTERN_DVBT_ReadReg(0x22fe, ®_frz);
1557 status &= INTERN_DVBT_WriteReg(0x22fe, reg_frz|0x01);
1558
1559 // bank 6 0xff [0] reg_fdp_load
1560 status &= INTERN_DVBT_ReadReg(0x22ff, ®);
1561
1562 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1563 status &= INTERN_DVBT_ReadReg(0x224d, ®);
1564 noise_power = reg & 0x07;
1565
1566 status &= INTERN_DVBT_ReadReg(0x224c, ®);
1567 noise_power = (noise_power << 8)|reg;
1568
1569 status &= INTERN_DVBT_ReadReg(0x224b, ®);
1570 noise_power = (noise_power << 8)|reg;
1571
1572 status &= INTERN_DVBT_ReadReg(0x224a, ®);
1573 noise_power = (noise_power << 8)|reg;
1574
1575 noise_power = noise_power/2;
1576
1577 // bank 6 0x26 [5:4] reg_transmission_mode
1578 status &= INTERN_DVBT_ReadReg(0x2226, ®);
1579
1580 // bank 6 0xfe [0] reg_fdp_freeze
1581 status &= INTERN_DVBT_WriteReg(0x22fe, reg_frz);
1582
1583 if ((reg&0x03)==0x00) //2K
1584 {
1585 if (noise_power<1512)
1586 snr = 0;
1587 else
1588 snr = 10*Log10Approx((float)noise_power/1512);
1589 }
1590 //else if ((reg&0x03)==0x01)//8K
1591 else
1592 {
1593 if (noise_power<6048)
1594 snr = 0;
1595 else
1596 snr = 10*Log10Approx((float)noise_power/6048);
1597 }
1598 /* ignore 4K
1599 else //4K
1600 {
1601 if (noise_power<3024)
1602 snr = 0;
1603 else
1604 snr = 10*Log10Approx(noise_power/3024);
1605 }
1606 */
1607
1608 if (status == true)
1609 return snr;
1610 else
1611 return -1;
1612
1613 }
1614
INTERN_DVBT_GetSignalStrength(WORD * strength)1615 FUNCTION_RESULT INTERN_DVBT_GetSignalStrength(WORD *strength)
1616 {
1617 *strength = 80;
1618 return E_RESULT_SUCCESS;
1619 }
1620
1621 /****************************************************************************
1622 Subject: To get the DVT Signal quility
1623 Function: INTERN_DVBT_GetSignalQuality
1624 Parmeter: Quility
1625 Return: E_RESULT_SUCCESS
1626 E_RESULT_FAILURE
1627 Remark: Here we have 4 level range
1628 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1629 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1630 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1631 <4>.4th Range => Quality <10
1632 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(WORD * quality)1633 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality(WORD *quality)
1634 {
1635 float fber;
1636 float log_ber;
1637
1638 if (TRUE == INTERN_DVBT_Lock(COFDM_PSYNC_LOCK) )
1639 {
1640 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
1641 {
1642 DBG_INTERN_DVBT(printf("GetPostViterbiBer Fail!\n"));
1643 return E_RESULT_FAILURE;
1644 }
1645
1646 log_ber = (-1)*Log10Approx(1/fber); // Log10Approx() provide 1~2^32 input range only
1647
1648 DBG_GET_SIGNAL(printf("Log(BER) = %f\n",log_ber));
1649
1650 if ( log_ber <= (-7.0) ) // PostVit BER < 1e-7
1651 {
1652 *quality = 100;
1653 }
1654 else if ( log_ber < (-3.7) ) // PostVit BER < 2e-4
1655 {
1656 *quality = 60 + (((-3.7) - log_ber) / ((-3.7)-(-7.0)) * (100-60));
1657 }
1658 else if ( log_ber < (-2.7) ) // PostVit BER < 2e-3
1659 {
1660 *quality = 10 + (((-2.7) - log_ber) / ((-2.7)-(-3.7)) * (60-10));
1661 }
1662 else
1663 {
1664 *quality = 10;
1665 }
1666
1667 }
1668 else
1669 {
1670 *quality = 0;
1671 }
1672
1673 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", (int)*quality));
1674
1675 return E_RESULT_SUCCESS;
1676
1677 }
1678
1679
1680 /****************************************************************************
1681 Subject: To get the DVBT Carrier Freq Offset
1682 Function: INTERN_DVBT_Get_FreqOffset
1683 Parmeter: Frequency offset (in KHz), bandwidth
1684 Return: E_RESULT_SUCCESS
1685 E_RESULT_FAILURE
1686 Remark:
1687 *****************************************************************************/
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,U8 u8BW)1688 FUNCTION_RESULT INTERN_DVBT_Get_FreqOffset(float *pFreqOff, U8 u8BW)
1689 {
1690 float N, FreqB;
1691 float FreqCfoTd, FreqCfoFd, FreqIcfo;
1692 U32 RegCfoTd, RegCfoFd, RegIcfo;
1693 U8 reg_frz, reg;
1694 U8 status;
1695
1696 FreqB = (float)u8BW * 8 / 7;
1697
1698 status = INTERN_DVBT_ReadReg(0x2104+1, ®_frz);
1699
1700 status &= INTERN_DVBT_WriteReg(0x2104+1, reg_frz|0x80);
1701
1702 status &= INTERN_DVBT_ReadReg(0x24c6+2, ®);
1703 RegCfoTd = reg;
1704
1705 status &= INTERN_DVBT_ReadReg(0x24c6+1, ®);
1706 RegCfoTd = (RegCfoTd << 8)|reg;
1707
1708 status &= INTERN_DVBT_ReadReg(0x24c6, ®);
1709 RegCfoTd = (RegCfoTd << 8)|reg;
1710
1711 FreqCfoTd = (float)RegCfoTd;
1712
1713 if (RegCfoTd & 0x800000)
1714 FreqCfoTd = FreqCfoTd - (float)0x1000000;
1715
1716 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
1717
1718 status &= INTERN_DVBT_WriteReg(0x2104+1, reg_frz&(~0x80));
1719
1720 status &= INTERN_DVBT_ReadReg(0x22fe, ®_frz);
1721 status &= INTERN_DVBT_WriteReg(0x22fe, reg_frz|0x01);
1722
1723 //status &= INTERN_DVBT_WriteReg(0x22fe+1, 0x01);
1724 status &= INTERN_DVBT_WriteReg(0x22ff, 0x01);
1725
1726 status &= INTERN_DVBT_ReadReg(0x2230+3, ®);
1727 RegCfoFd = reg;
1728
1729 status &= INTERN_DVBT_ReadReg(0x2230+2, ®);
1730 RegCfoFd = (RegCfoFd << 8)|reg;
1731
1732 status &= INTERN_DVBT_ReadReg(0x2230+1, ®);
1733 RegCfoFd = (RegCfoFd << 8)|reg;
1734
1735 FreqCfoFd = (float)RegCfoFd;
1736
1737 if (RegCfoFd & 0x800000)
1738 FreqCfoFd = FreqCfoFd - (float)0x1000000;
1739
1740 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
1741
1742 status &= INTERN_DVBT_ReadReg(0x2218+1, ®);
1743 RegIcfo = reg & 0x07;
1744
1745 status &= INTERN_DVBT_ReadReg(0x2218, ®);
1746 RegIcfo = (RegIcfo << 8)|reg;
1747
1748 FreqIcfo = (float)RegIcfo;
1749
1750 if (RegIcfo & 0x400)
1751 FreqIcfo = FreqIcfo - (float)0x800;
1752
1753 status &= INTERN_DVBT_ReadReg(0x2226, ®);
1754 reg = reg & 0x30;
1755
1756 switch (reg)
1757 {
1758 case 0x00: N = 2048; break;
1759 case 0x20: N = 4096; break;
1760 case 0x10:
1761 default: N = 8192; break;
1762 }
1763
1764 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
1765 status &= INTERN_DVBT_WriteReg(0x22fe, reg_frz&(~0x01));
1766 //status &= INTERN_DVBT_WriteReg(0x22fe+1, 0x01);
1767 status &= INTERN_DVBT_WriteReg(0x22ff, 0x01);
1768 *pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
1769
1770 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
1771 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
1772 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
1773 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
1774
1775 if (status == TRUE)
1776 return E_RESULT_SUCCESS;
1777 else
1778 return E_RESULT_FAILURE;
1779 }
1780
1781
INTERN_DVBT_Power_ON_OFF(U8 bPowerOn)1782 void INTERN_DVBT_Power_ON_OFF(U8 bPowerOn)
1783 {
1784
1785 bPowerOn = bPowerOn;
1786 }
1787
INTERN_DVBT_Power_Save(void)1788 BOOLEAN INTERN_DVBT_Power_Save(void)
1789 {
1790
1791 return TRUE;
1792 }
1793
1794 /****************************************************************************
1795 Subject: To get the DVBT constellation parameter
1796 Function: INTERN_DVBT_Get_TPS_Parameter_Const
1797 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
1798 Return: TRUE
1799 FALSE
1800 Remark: The TPS parameters will be available after TPS lock
1801 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(WORD * TPS_parameter)1802 BOOLEAN INTERN_DVBT_Get_TPS_Parameter_Const( WORD * TPS_parameter)
1803 {
1804 U8 tps_param;
1805
1806 if ( INTERN_DVBT_ReadReg(0x2224, &tps_param) == FALSE )
1807 return FALSE;
1808
1809 *TPS_parameter = tps_param & (BIT0|BIT1) ;
1810 return TRUE;
1811 }
1812
1813 /***********************************************************************************
1814 Subject: read register
1815 Function: MDrv_1210_IIC_Bypass_Mode
1816 Parmeter:
1817 Return:
1818 Remark:
1819 ************************************************************************************/
1820 //void MDrv_1210_IIC_Bypass_Mode(BOOLEAN enable)
1821 //{
1822 // UNUSED(enable);
1823 // if (enable)
1824 // INTERN_DVBT_WriteReg(0x8010, 0x10); // IIC by-pass mode on
1825 // else
1826 // INTERN_DVBT_WriteReg(0x8010, 0x00); // IIC by-pass mode off
1827 //}
1828