xref: /utopia/UTPA2-700.0.x/modules/demodulator/drv/dmd/t3/Int_DVBC/INTERN_DVBC_Private.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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94 
95 #ifndef _INTERN_DVBC_PRIVATE_H_
96 #define _INTERN_DVBC_PRIVATE_H_
97 
98 
99 
100 
101 //--------------------------------------------------------------------
102 
103 // #define     DEMOD_DYNAMIC_SLAVE_ID_1          0x32
104 // #define     DEMOD_DYNAMIC_SLAVE_ID_2          0x72
105 // #define     DEMOD_DYNAMIC_SLAVE_ID_3          0xB2
106 // #define     DEMOD_DYNAMIC_SLAVE_ID_4          0xF2
107 
108 #define     DEMOD_ADDR_H            0x00
109 #define     DEMOD_ADDR_L            0x01
110 #define     DEMOD_WRITE_REG         0x02
111 #define     DEMOD_WRITE_REG_EX      0x03
112 #define     DEMOD_READ_REG          0x04
113 #define     DEMOD_RAM_CONTROL       0x05
114 
115 // #define INTERN_DVBC_IIC_CONTROL                 0x8400
116 // #define INTERN_DVBC_IIC_SCL_CLK                 0x8401
117 // #define INTERN_DVBC_IIC_READ_DATA               0x8402
118 // #define INTERN_DVBC_IIC_STATUS                  0x8403
119 // #define INTERN_DVBC_IIC_WRITE_DATA              0x8404
120 
121 // #define     COFDM_DEM_I2C_ID            DEMOD_DYNAMIC_SLAVE_ID_1
122 // #define     COFDM_DEM_I2C_ID_2          DEMOD_DYNAMIC_SLAVE_ID_2
123 // #define     COFDM_DEM_I2C_ID_3          DEMOD_DYNAMIC_SLAVE_ID_3
124 // #define     COFDM_DEM_I2C_ID_4          DEMOD_DYNAMIC_SLAVE_ID_4
125 
126 // #define INTERN_DVBC_REG_INVERSION              0x8024
127 #define BOOL    BOOLEAN
128 
129 #if  DTV_SCAN_AUTO_FINE_TUNE_ENABLE
130     //INTERN_DVBC_ Capture Range fix to 500K
131     #define DEMOD_CAPTURE_RANGE_500_K            500
132         #define DEMOD_CAPTURE_RANGE_SIZE                                      DEMOD_CAPTURE_RANGE_500_K
133 #endif
134 
135 
136 
137 
138 //--------------------------------------------------------------------
139 typedef enum
140 {
141     E_SYS_UNKOWN = -1,
142     E_SYS_DVBT,
143     E_SYS_DVBC,
144     E_SYS_ATSC,
145     E_SYS_VIF,
146 
147     E_SYS_NUM
148 }E_SYSTEM;
149 
150 typedef enum
151 {
152     CMD_SYSTEM_INIT = 0,
153     CMD_DAC_CALI,
154     CMD_DVBT_CONFIG,
155     CMD_DVBC_CONFIG,
156     CMD_VIF_CTRL,
157     CMD_FSM_CTRL,
158     CMD_INDIR_RREG,
159     CMD_INDIR_WREG,
160     CMD_GET_INFO,
161     CMD_TS_CTRL,
162     CMD_TUNED_VALUE,
163 
164     CMD_MAX_NUM
165 }E_CMD_CODE;
166 
167 typedef enum
168 {
169     pc_op_code = 0,
170     pc_if_freq,
171     pc_sound_sys,
172     pc_vif_vga_maximum_l,
173     pc_vif_vga_maximum_h,
174     pc_scan_mode,
175     pc_vif_top,
176     pc_gain_distribution_thr_l,
177     pc_gain_distribution_thr_h,
178 
179     VIF_PARAM_MAX_NUM
180 }E_VIF_PARAM;
181 
182 typedef enum
183 {
184     pc_system = 0,
185 
186     SYS_PARAM_MAX_NUM
187 }E_SYS_PARAM;
188 
189 typedef enum
190 {
191     SET_IF_FREQ = 0,
192     SET_SOUND_SYS,
193     VIF_INIT,
194     SET_VIF_HANDLER,
195     VIF_TOP_ADJUST,
196 
197     VIF_CMD_MAX_NUM
198 }E_VIF_CMD;
199 
200 typedef enum
201 {
202     TS_PARALLEL = 0,
203     TS_SERIAL = 1,
204 
205     TS_MODE_MAX_NUM
206 }E_TS_MODE;
207 
208 typedef enum
209 {
210     dac_op_code = 0,
211     dac_idac_ch0,
212     dac_idac_ch1,
213 
214     DAC_PARAM_MAX_NUM
215 }
216 E_DAC_PARAM;
217 
218 typedef enum
219 {
220     DAC_RUN_CALI = 0,
221     DAC_IDAC_ASSIGN,
222 
223     DAC_CMD_MAX_NUM
224 }
225 E_DAC_CMD;
226 
227 typedef enum
228 {
229     agc_ref_small,
230     agc_ref_large,
231     agc_ref_aci,
232     ripple_switch_th_l,
233     ripple_switch_th_h,
234 
235     TUNED_PARAM_MAX_NUM
236 }E_TUNED_PARAM;
237 
238 
239 typedef struct
240 {
241     U8        cmd_code;
242     U8        param[64];
243 } S_CMDPKTREG;
244 
245 #define REG_CMD_CTRL    0x20CC
246 #define REG_DTA_CTRL    0x20CD
247 #define REG_CMD_ADDR    0x20CE
248 #define REG_CMD_DATA    0x20CF
249 
250 #define _REG_START      REG_CMD_CTRL
251 #define _REG_END        REG_CMD_CTRL
252 #define _REG_DRQ        REG_DTA_CTRL
253 #define _REG_FSM        REG_CMD_CTRL
254 #define _REG_ERR        REG_DTA_CTRL
255 
256 #define _BIT_START      BIT1
257 #define _BIT_END        BIT0
258 #define _BIT_DRQ        BIT0
259 #define _BIT_FSM        BIT3
260 #define _BIT_ERR        BIT7
261 
262 //--------------------------------------------------------------------
263 typedef enum
264 {
265     // OP Mode Settings
266     p_opmode_rfagc_en = 0,
267     p_opmode_humdet_en,
268     p_opmode_dcr_en,
269     p_opmode_iqb_en,
270     p_opmode_auto_iq_swap,
271     p_opmode_auto_fsa_left,
272     p_opmode_auto_rfmax,
273     p_opmode_mode_forced,
274     p_opmode_cp_forced,
275 
276     // Config Params
277     pc_config_rssi,
278     pc_config_zif,
279     pc_config_fc_l,
280     pc_config_fc_h,
281     pc_config_fs_l,
282     pc_config_fs_h,
283     pc_config_bw,
284     pc_config_fsa_left,
285     pc_config_rfmax,
286     pc_config_lp_sel,
287     pc_config_cp,
288     pc_config_mode,
289     pc_config_iq_swap,
290     pc_config_atv_system,
291     pc_config_serial_ts,
292     pc_config_ts_out_inv,
293     pc_config_ts_data_swap,
294     pc_config_icfo_range,
295 
296     DVBT_PARAM_LEN,
297 } DVBT_Param;
298 
299 //--------------------------------------------------------------------
300 BOOLEAN INTERN_DVBC_Reset ( void );
301 BOOLEAN INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, U8 param_cnt);
302 BOOLEAN INTERN_DVBC_Get_TPS_Parameter_Const( WORD * TSP_parameter);
303 //--------------------------------------------------------------------
304 
305 #endif
306 
307