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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBC.c
98 /// @brief INTERN_DVBC DVBC
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBC_C_
104 #include "MsCommon.h"
105 #include "MsIRQ.h"
106 #include "MsOS.h"
107
108 #include "MsTypes.h"
109 #include "drvBDMA.h"
110 #include "drvIIC.h"
111 #include "msAPI_Tuner.h"
112 #include "msAPI_MIU.h"
113 #include "BinInfo.h"
114 #include "halVif.h"
115
116 #include "INTERN_DVBC.h"
117 #include "INTERN_DVBC_Private.h"
118 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
119 #include "InfoBlock.h"
120 #endif
121 #include "apiPWS.h"
122
123 #include "drvMMIO.h"
124 #include "drvAVD.h"
125
126 #define TEST_EMBEDED_DEMOD 0
127 //U8 load_data_variable=1;
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBC_DEMOD BIN_ID_INTERN_DVBC
130 //#define INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
131
132 #define MBRegBase 0x110500//0x1033C0
133 #define VDMcuBase 0x103400
134
135 #define DBG_INTERN_DVBC(x) //x
136 #define DBG_GET_SIGNAL(x)
137 #define DBG_DUMP_LOAD_DSP_TIME 0
138
139 //-----------------------------------------------------------------------
140 /****************************************************************
141 *Local Variables *
142 ****************************************************************/
143 //static U8 *RIUBase=NULL;
144 //static U32 RIUSize=0;
145 //static BOOL FECLock=0;
146 static U8 FECUnlockCnt;
147
148
149 //Global Variables
150 static S_CMDPKTREG gsCmdPacket;
151 //U8 gCalIdacCh0, gCalIdacCh1;
152
153 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
154 code U8 INTERN_DVBC_table[] = {
155 #include "INTERN_DVBC_demod.dat"
156 };
157 #endif
158
159 #if 0
160 static void INTERN_DVBC_InitRegBase(void)
161 {
162 MDrv_MMIO_GetBASE((MS_U32*)(void *)RIUBase, &RIUSize, MS_MODULE_MIU);
163 printf("address:%lx %lx\n",(MS_U32)RIUBase, RIUSize);
164 }
165 #endif
166 /***********************************************************************************
167 Subject: Delay
168 Function: INTERN_DVBC_Delayms
169 Parmeter: delay_ms : millisecs for delay
170 Return: NONE
171 Remark:
172 ************************************************************************************/
INTERN_DVBC_Delayms(U32 delay_ms)173 static void INTERN_DVBC_Delayms(U32 delay_ms)
174 {
175 MsOS_DelayTask(delay_ms);
176 }
177
INTERN_DVBC_ReadReg(U16 u16Addr,U8 * pu8Data)178 BOOLEAN INTERN_DVBC_ReadReg(U16 u16Addr, U8 *pu8Data)
179 {
180 U16 u8WaitCnt=0;
181
182 // UNUSED(pu8Data);
183 if (MDrv_ReadByte(MBRegBase + 0x00))
184 {
185 printf(">> MB Busy!\n");
186 return FALSE;
187 }
188
189 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H
190 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L
191 MDrv_WriteByte(MBRegBase + 0x00, 0x01); // MB_CNTL set read mode
192
193 MDrv_WriteByte(0x103463, 0x02); // assert interrupt to VD MCU51
194 MDrv_WriteByte(0x103463, 0x00); // de-assert interrupt to VD MCU51
195
196 while(MDrv_ReadByte(MBRegBase + 0x00)!= 0xFF) // wait MB_CNTL set done
197 {
198 #if TEST_EMBEDED_DEMOD
199 INTERN_DVBC_Delayms(1); // << Ken 20090629
200 #endif
201 if (u8WaitCnt++ >= 0xFF)
202 {
203 printf(">> DVBC ReadReg Fail!\n");
204 return FALSE;
205 }
206 }
207
208 *pu8Data = MDrv_ReadByte(MBRegBase + 0x03); // REG_DATA get
209 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
210
211 return TRUE;
212 }
213
214
INTERN_DVBC_WriteReg(U32 u16Addr,U8 u8Data)215 BOOLEAN INTERN_DVBC_WriteReg(U32 u16Addr, U8 u8Data)
216 {
217 U16 u8WaitCnt=0;
218
219 MDrv_WriteByte(MBRegBase + 0x02, (U8)(u16Addr >> 8)); // ADDR_H
220 MDrv_WriteByte(MBRegBase + 0x01, (U8)u16Addr); // ADDR_L
221 MDrv_WriteByte(MBRegBase + 0x03, u8Data); // REG_DATA
222 MDrv_WriteByte(MBRegBase + 0x00, 0x02); // MB_CNTL set write mode
223
224 MDrv_WriteByte(0x103463, 0x02); // assert interrupt to VD MCU51
225 MDrv_WriteByte(0x103463, 0x00); // de-assert interrupt to VD MCU51
226
227 while(MDrv_ReadByte(MBRegBase + 0x00) != 0xFF) // wait done flag
228 {
229 #if TEST_EMBEDED_DEMOD
230 INTERN_DVBC_Delayms(1); // <<< Ken 20090629
231 #endif
232 if (u8WaitCnt++ >= 0xFF)
233 {
234 printf(">> DVBC WriteReg Fail!\n");
235 return FALSE;
236 }
237 }
238
239 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
240
241 return TRUE;
242 }
243
244 /***********************************************************************************
245 Subject: Command Packet Interface
246 Function: INTERN_DVBC_Cmd_Packet_Send
247 Parmeter:
248 Return: BOOLEAN
249 Remark:
250 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,U8 param_cnt)251 BOOLEAN INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, U8 param_cnt)
252 {
253 U8 status = true, indx;
254 U8 reg_val, timeout = 0;
255
256 // ==== Command Phase ===================
257 DBG_INTERN_DVBC(printf("--->INTERN_DVBC (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
258 pCmdPacket->param[0],pCmdPacket->param[1],
259 pCmdPacket->param[2],pCmdPacket->param[3],
260 pCmdPacket->param[4],pCmdPacket->param[5] ));
261
262 // wait _BIT_END clear
263 do
264 {
265 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, ®_val);
266 if((reg_val & _BIT_END) != _BIT_END)
267 {
268 break;
269 }
270 MsOS_DelayTask(1);
271 if (timeout++ > 200)
272 {
273 printf("---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
274 return false;
275 }
276 } while (1);
277
278 // set cmd_3:0 and _BIT_START
279 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, ®_val);
280 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
281 status &= INTERN_DVBC_WriteReg(REG_CMD_CTRL, reg_val);
282
283 //DBG_INTERN_DVBC(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
284 // wait _BIT_START clear
285 do
286 {
287 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, ®_val);
288 if((reg_val & _BIT_START) != _BIT_START)
289 {
290 break;
291 }
292 MsOS_DelayTask(1);
293 if (timeout++ > 200)
294 {
295 printf("---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
296 return false;
297 }
298 } while (1);
299
300 // ==== Data Phase ======================
301
302 status &= INTERN_DVBC_WriteReg(REG_CMD_ADDR, 0x00);
303
304 for (indx = 0; indx < param_cnt; indx++)
305 {
306 status &= INTERN_DVBC_ReadReg(REG_CMD_ADDR, ®_val);
307 //DBG_INTERN_DVBC(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
308
309 // set param[indx] and _BIT_DRQ
310 status &= INTERN_DVBC_WriteReg(REG_CMD_DATA, pCmdPacket->param[indx]);
311 status &= INTERN_DVBC_ReadReg(REG_DTA_CTRL, ®_val);
312 status &= INTERN_DVBC_WriteReg(REG_DTA_CTRL, reg_val|_BIT_DRQ);
313
314 // wait _BIT_DRQ clear
315 do
316 {
317 status &= INTERN_DVBC_ReadReg(REG_DTA_CTRL, ®_val);
318 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
319 {
320 break;
321 }
322 MsOS_DelayTask(1);
323 if (timeout++ > 200)
324 {
325 printf("---> INTERN_DVBC_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
326 return false;
327 }
328 } while (1);
329 }
330
331 // ==== End Phase =======================
332
333 // set _BIT_END to finish command
334 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, ®_val);
335 status &= INTERN_DVBC_WriteReg(REG_CMD_CTRL, reg_val|_BIT_END);
336
337 return status;
338 }
339
340
341 /***********************************************************************************
342 Subject: Command Packet Interface
343 Function: INTERN_DVBC_Cmd_Packet_Exe_Check
344 Parmeter:
345 Return: BOOLEAN
346 Remark:
347 ************************************************************************************/
INTERN_DVBC_Cmd_Packet_Exe_Check(BOOL * cmd_done)348 BOOLEAN INTERN_DVBC_Cmd_Packet_Exe_Check(BOOL* cmd_done)
349 {
350 U8 status = true;
351 U8 reg_val;
352 U16 timeout = 0;
353
354 // wait _BIT_END clear
355 do {
356 status &= INTERN_DVBC_ReadReg(REG_CMD_CTRL, ®_val);
357
358 if((reg_val & _BIT_END) != _BIT_END)
359 break;
360
361 if (timeout++ > 200)
362 {
363 *cmd_done = false;
364 return status;
365 }
366 INTERN_DVBC_Delayms(10);
367 } while (1);
368
369 DBG_INTERN_DVBC(printf("Exe duration: %d\n", (int)timeout));
370
371 *cmd_done = true;
372 return status;
373 }
374
375 /***********************************************************************************
376 Subject: SoftStop
377 Function: INTERN_DVBC_SoftStop
378 Parmeter:
379 Return: BOOLEAN
380 Remark:
381 ************************************************************************************/
382 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
383 #else
INTERN_DVBC_SoftStop(void)384 BOOLEAN INTERN_DVBC_SoftStop ( void )
385 {
386 U16 u8WaitCnt=0;
387
388 if (MDrv_ReadByte(MBRegBase + 0x00))
389 {
390 printf(">> MB Busy!\n");
391 return FALSE;
392 }
393
394 MDrv_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
395
396 MDrv_WriteByte(0x103463, 0x02); // assert interrupt to VD MCU51
397 MDrv_WriteByte(0x103463, 0x00); // de-assert interrupt to VD MCU51
398
399 while(MDrv_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
400 {
401 #if TEST_EMBEDED_DEMOD
402 INTERN_DVBC_Delayms(1); // << Ken 20090629
403 #endif
404 if (u8WaitCnt++ >= 0xFF)
405 {
406 printf(">> DVBC SoftStop Fail!\n");
407 return FALSE;
408 }
409 }
410
411 //MDrv_WriteByte(0x103460, 0x01); // reset VD_MCU
412 MDrv_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
413
414 return TRUE;
415 }
416 #endif
417
418 /***********************************************************************************
419 Subject: Reset
420 Function: INTERN_DVBC_Reset
421 Parmeter:
422 Return: BOOLEAN
423 Remark:
424 ************************************************************************************/
INTERN_DVBC_Reset(void)425 BOOLEAN INTERN_DVBC_Reset ( void )
426 {
427 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_reset\n"));
428
429 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
430 #else
431 INTERN_DVBC_SoftStop();
432 #endif
433
434 MDrv_WriteByte(0x103460, 0x01); // reset VD_MCU
435 // INTERN_DVBC_WriteReg(0x2002, 0x72); // reset DVB-C
436 INTERN_DVBC_Delayms(5);
437 // INTERN_DVBC_WriteReg(0x2002, 0x52);
438 MDrv_WriteByte(0x103460, 0x00);
439 INTERN_DVBC_Delayms(5);
440 //FECLock = FALSE;
441 FECUnlockCnt = 0;
442 return TRUE;
443 }
444
445 /***********************************************************************************
446 Subject: Exit
447 Function: INTERN_DVBC_Exit
448 Parmeter:
449 Return: BOOLEAN
450 Remark:
451 ************************************************************************************/
INTERN_DVBC_Exit(void)452 BOOLEAN INTERN_DVBC_Exit ( void )
453 {
454 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
455 //Mapi_PWS_Stop_VDMCU(); // ken.chang
456 #else
457 INTERN_DVBC_SoftStop();
458
459 //diable clk gen
460 MDrv_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
461 MDrv_WriteByte(0x10330b, 0x00);
462
463 MDrv_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
464 MDrv_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
465
466 MDrv_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
467 MDrv_WriteByte(0x10330f, 0x00);
468
469 MDrv_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
470 MDrv_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
471
472 MDrv_WriteByte(0x103312, 0x05); // dvbt_t:0x0000, dvb_c: 0x0004
473 MDrv_WriteByte(0x103313, 0x00);
474
475 MDrv_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
476 MDrv_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
477
478 MDrv_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
479 MDrv_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
480
481 MDrv_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
482 MDrv_WriteByte(0x103319, 0x11);
483
484 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
485 MDrv_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
486
487 if(MDrv_Read2Byte(0x001ECC) == 0x000F) // T3
488 {
489 MDrv_WriteByte(0x101E3E, 0x00); // DVBC = BIT2 clear
490 }
491 #endif
492 return TRUE;
493 }
494
495 /***********************************************************************************
496 Subject: Load DSP code to chip
497 Function: INTERN_DVBC_LoadDSPCode
498 Parmeter:
499 Return: BOOLEAN
500 Remark:
501 ************************************************************************************/
INTERN_DVBC_LoadDSPCode(void)502 static BOOLEAN INTERN_DVBC_LoadDSPCode(void)
503 {
504 U8 udata = 0x00;
505 U16 i;
506 U16 fail_cnt=0;
507
508 #if (DBG_DUMP_LOAD_DSP_TIME==1)
509 U32 u32Time;
510 #endif
511
512 #ifndef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
513 BININFO BinInfo;
514 BOOLEAN bResult;
515 U32 u32GEAddr;
516 U8 Data;
517 S8 op;
518 U32 srcaddr;
519 U32 len;
520 U32 SizeBy4K;
521 U16 u16Counter=0;
522 U8 *pU8Data;
523 #endif
524
525 #if 0
526 if(MDrv_ReadByte(0x101E3E))
527 {
528 printf("Warring! Reg[0x101E3E]=%d\n", MDrv_ReadByte(0x101E3E));
529 return FALSE;
530 }
531 #endif
532
533 MDrv_Sys_DisableWatchDog();
534
535 MDrv_WriteByte(0x103460, 0x01); // reset VD_MCU
536 MDrv_WriteByte(0x103461, 0x00); // disable SRAM
537 MDrv_WriteByte(0x103463, 0x50); // enable "vdmcu51_if"
538 MDrv_WriteByte(0x103463, 0x51); // enable auto-increase
539 MDrv_WriteByte(0x103464, 0x00); // sram address low byte
540 MDrv_WriteByte(0x103465, 0x00); // sram address high byte
541
542 //// Load code thru VDMCU_IF ////
543 DBG_INTERN_DVBC(printf(">Load Code...\n"));
544 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
545 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
546 {
547 MDrv_WriteByte(0x10346C, INTERN_DVBC_table[i]); // write data to VD MCU 51 code sram
548 }
549 #else
550 BinInfo.B_ID = BIN_ID_INTERN_DVBC_DEMOD;
551 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
552 if ( bResult != PASS )
553 {
554 return FALSE;
555 }
556 //printf("\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
557
558 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
559 InfoBlock_Flash_2_Checking_Start(&BinInfo);
560 #endif
561
562 #if OBA2
563 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
564 #else
565 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
566 #endif
567
568 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
569 InfoBlock_Flash_2_Checking_End(&BinInfo);
570 #endif
571
572 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
573 SizeBy4K=BinInfo.B_Len/0x1000;
574 //printf("\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
575
576 #if (DBG_DUMP_LOAD_DSP_TIME==1)
577 u32Time = msAPI_Timer_GetTime0();
578 #endif
579
580 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
581
582 for (i=0;i<=SizeBy4K;i++)
583 {
584 if(i==SizeBy4K)
585 len=BinInfo.B_Len%0x1000;
586 else
587 len=0x1000;
588
589 srcaddr = u32GEAddr+(0x1000*i);
590 //printf("\t i = %08X\n", i);
591 //printf("\t len = %08X\n", len);
592 op = 1;
593 u16Counter = 0 ;
594 //printf("\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
595 while(len--)
596 {
597 u16Counter ++ ;
598 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
599 //pU8Data = (U8 *)(srcaddr|0x80000000);
600 #if OBA2
601 pU8Data = (U8 *)(srcaddr);
602 #else
603 pU8Data = (U8 *)(srcaddr|0x80000000);
604 #endif
605 Data = *pU8Data;
606
607 #if 0
608 if(u16Counter < 0x100)
609 printf("0x%bx,", Data);
610 #endif
611 MDrv_WriteByte(0x10346C, Data); // write data to VD MCU 51 code sram
612
613 srcaddr += op;
614 }
615 // printf("\n\n\n");
616 }
617
618 #if (DBG_DUMP_LOAD_DSP_TIME==1)
619 printf("------> INTERN_DVBC Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
620 #endif
621
622 #endif
623
624 //// Content verification ////
625 DBG_INTERN_DVBC(printf(">Verify Code...\n"));
626
627 MDrv_WriteByte(0x103464, 0x00); // sram address low byte
628 MDrv_WriteByte(0x103465, 0x00); // sram address high byte
629
630 #ifdef INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY
631 for ( i = 0; i < sizeof(INTERN_DVBC_table); i++)
632 {
633 udata = MDrv_ReadByte(0x103470); // read sram data
634 if (udata != INTERN_DVBC_table[i])
635 {
636 printf(">fail add = 0x%x\n", i);
637 printf(">code = 0x%x\n", INTERN_DVBC_table[i]);
638 printf(">data = 0x%x\n", udata);
639
640 if (fail_cnt++ > 10)
641 {
642 printf(">DVB-C DSP Loadcode fail!");
643 return false;
644 }
645 }
646 }
647 #else
648 for (i=0;i<=SizeBy4K;i++)
649 {
650 if(i==SizeBy4K)
651 len=BinInfo.B_Len%0x1000;
652 else
653 len=0x1000;
654
655 srcaddr = u32GEAddr+(0x1000*i);
656 //printf("\t i = %08LX\n", i);
657 //printf("\t len = %08LX\n", len);
658 op = 1;
659 u16Counter = 0 ;
660 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
661 while(len--)
662 {
663 u16Counter ++ ;
664 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
665 //pU8Data = (U8 *)(srcaddr|0x80000000);
666 #if OBA2
667 pU8Data = (U8 *)(srcaddr);
668 #else
669 pU8Data = (U8 *)(srcaddr|0x80000000);
670 #endif
671 Data = *pU8Data;
672
673 #if 0
674 if(u16Counter < 0x100)
675 printf("0x%bx,", Data);
676 #endif
677 udata = MDrv_ReadByte(0x103470); // read sram data
678 if (udata != Data)
679 {
680 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
681 printf(">code = 0x%x\n", Data);
682 printf(">data = 0x%x\n", udata);
683
684 if (fail_cnt++ > 10)
685 {
686 printf(">DVB-C DSP Loadcode fail!");
687 return false;
688 }
689 }
690
691 srcaddr += op;
692 }
693 // printf("\n\n\n");
694 }
695 #endif
696
697 MDrv_WriteByte(0x103463, 0x50); // diable auto-increase
698 MDrv_WriteByte(0x103463, 0x00); // disable "vdmcu51_if"
699 MDrv_WriteByte(0x103461, 0x01); // enable SRAM
700 MDrv_WriteByte(0x103460, 0x00); // release VD_MCU
701
702 DBG_INTERN_DVBC(printf(">DSP Loadcode done."));
703 //while(load_data_variable);
704
705 if(MDrv_Read2Byte(0x001ECC) == 0x000F) // chip_id == T3
706 {
707 MDrv_WriteByte(0x101E3E, 0x04); // DVBC = BIT2 -> 0x04
708 }
709
710 return TRUE;
711 }
712
713 /***********************************************************************************
714 Subject: DVB-C CLKGEN initialized function
715 Function: INTERN_DVBC_Power_On_Initialization
716 Parmeter:
717 Return: BOOLEAN
718 Remark:
719 ************************************************************************************/
INTERN_DVBC_InitClkgen(void)720 void INTERN_DVBC_InitClkgen(void)
721 {
722 //<<CLK_GEN1_DVB_t >>
723 if ( MDrv_ReadByte( 0x001ecf) == 0x00 )
724 MDrv_WriteByte(0x100b42, 0x10); // reg_ckg_vdmcu@0x21[4:0] (bank_CLKGEN0) //108MHz
725 else //after t3_u02
726 MDrv_WriteByte(0x100b42, 0x0D); // reg_ckg_vdmcu@0x21[4:0] (bank_CLKGEN0) //108MHz
727 MDrv_WriteByte(0x100b43, 0x01); // reg_ckg_vd200@0x21[11:8]
728
729 MDrv_WriteByte(0x100b44, 0x00); // enable mail-box clock (bank_CLKGEN0)
730 MDrv_WriteByte(0x100b45, 0x00); // enable mail-box clock
731
732 MDrv_WriteByte(0x103314, 0x00); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
733 MDrv_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
734
735 MDrv_WriteByte(0x10330a, 0x00); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
736 MDrv_WriteByte(0x10330b, 0x00);
737
738 MDrv_WriteByte(0x10330c, 0x00); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
739 MDrv_WriteByte(0x10330d, 0x00); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
740
741 MDrv_WriteByte(0x10330e, 0x00); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
742 MDrv_WriteByte(0x10330f, 0x00);
743
744 MDrv_WriteByte(0x103310, 0x00); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
745 MDrv_WriteByte(0x103311, 0x00); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
746
747 MDrv_WriteByte(0x103312, 0x04); // dvbt_t:0x0000, dvb_c: 0x0004
748 MDrv_WriteByte(0x103313, 0x00);
749
750 MDrv_WriteByte(0x103314, 0x00); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
751 MDrv_WriteByte(0x103315, 0x00); // reg_ckg_dvbtc_innc@0x0a[11:8]
752
753 MDrv_WriteByte(0x103316, 0x00); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
754 MDrv_WriteByte(0x103317, 0x00); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
755
756 MDrv_WriteByte(0x103318, 0x00); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
757 MDrv_WriteByte(0x103319, 0x00);
758 #if 0 //parallel
759 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
760 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
761
762 MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 /serial mode 0x0400
763 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
764 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
765 #else
766 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
767 #endif
768 #else // serial
769 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
770 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
771
772 MDrv_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
773 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
774 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
775 #else
776 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
777 #endif
778 #endif
779 //MDrv_WriteByte(0x101e22, 0x02); // internal TS connect to TS0:0x0002; to TS1:0x0200
780 //MDrv_WriteByte(0x101e23, 0x00); // reg_ts0~1_mux@0x11 (bank_CHIP)
781
782 //MDrv_WriteByte(0x100b50, 0x08); // internal TS0:0x0108; internal TS1:0x0801
783 //MDrv_WriteByte(0x100b51, 0x08); // reg_ckg_ts0~1@0x28 (bank_CLKGEN0) << Ken 20090629
784
785 MDrv_WriteByte(0x101e04, 0x00); // reg_if_agc_pad_oen@0x02 (bank_CHIP)
786 MDrv_WriteByte(0x101e05, 0x00);
787 }
788
789 /***********************************************************************************
790 Subject: Power on initialized function
791 Function: INTERN_DVBC_Power_On_Initialization
792 Parmeter:
793 Return: BOOLEAN
794 Remark:
795 ************************************************************************************/
796
INTERN_DVBC_Power_On_Initialization(void)797 BOOLEAN INTERN_DVBC_Power_On_Initialization ( void )
798 {
799 U8 status = true;
800 U8 cal_done;
801
802 UNUSED(cal_done);
803 //INTERN_DVBC_InitRegBase();
804 #if ( CHIP_FAMILY_TYPE == CHIP_FAMILY_S7 ) //T3
805 printf("INTERN_DVBC_Power_On_Initialization call stop vdmcu\n");
806 #if ENABLE_PWS
807 Mapi_PWS_Stop_VDMCU();
808 #endif
809 #endif
810
811 INTERN_DVBC_InitClkgen();
812
813 //// Firmware download //////////
814 DBG_INTERN_DVBC(printf("INTERN_DVBC Load DSP...\n"));
815 // MsOS_DelayTask(100);
816 if (MDrv_ReadByte(0x101E3E) != 0x04) // DVBC = BIT2 -> 0x04
817 {
818 if (INTERN_DVBC_LoadDSPCode() == FALSE)
819 {
820 printf("DVB-C Load DSP Code Fail\n");
821 return FALSE;
822 }
823 else
824 {
825 printf("DVB-C Load DSP Code OK\n");
826 }
827 }
828
829 #if 0
830 //// MCU Reset //////////
831 DBG_INTERN_DVBC(printf("INTERN_DVBC Reset...\n"));
832 if (INTERN_DVBC_Reset() == FALSE)
833 {
834 DBG_INTERN_DVBC(printf("Fail\n"));
835 return FALSE;
836 }
837 else
838 {
839 DBG_INTERN_DVBC(printf("OK\n"));
840 }
841 #endif
842
843 // INTERN_DVBC_ReadReg(0x8000, &gu8ChipRevId);
844 // DBG_INTERN_DVBC(printf("DVB-C RevID:%bx\n", gu8ChipRevId));
845
846 //// DAC calibration //////////
847 // DBG_INTERN_DVBC(printf("INTERN_DVBC Cal DAC...\n"));
848 //
849 // gsCmdPacket.cmd_code = CMD_DAC_CALI;
850 // gsCmdPacket.param[dac_op_code] = DAC_RUN_CALI;
851 // status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacket, 1);
852 // status &= INTERN_DVBC_Cmd_Packet_Exe_Check(&cal_done);
853 // if (cal_done == true)
854 // {
855 // DBG_INTERN_DVBC(printf("OK\n"));
856 // status &= INTERN_DVBC_ReadReg(0x81A8, &gCalIdacCh0);
857 // status &= INTERN_DVBC_ReadReg(0x81A9, &gCalIdacCh1);
858 // }
859 // else
860 // {
861 // gCalIdacCh0 = gCalIdacCh1 = 0;
862 // DBG_INTERN_DVBC(printf("FAIL\n"));
863 // }
864
865 return status;
866 }
867
868 /************************************************************************************************
869 Subject: Driving control
870 Function: INTERN_DVBC_Driving_Control
871 Parmeter: bInversionEnable : TRUE For High
872 Return: void
873 Remark:
874 *************************************************************************************************/
INTERN_DVBC_Driving_Control(BOOLEAN bEnable)875 void INTERN_DVBC_Driving_Control(BOOLEAN bEnable)
876 {
877 U8 u8Temp;
878
879 u8Temp = MDrv_ReadByte(0x101E10);
880
881 if (bEnable)
882 {
883 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
884 }
885 else
886 {
887 u8Temp = u8Temp & (~0x01);
888 }
889
890 DBG_INTERN_DVBC(printf("---> INTERN_DVBC_Driving_Control(Bit0) = 0x%bx \n",u8Temp));
891 MDrv_WriteByte(0x101E10, u8Temp);
892 }
893 /************************************************************************************************
894 Subject: Clk Inversion control
895 Function: INTERN_DVBC_Clk_Inversion_Control
896 Parmeter: bInversionEnable : TRUE For Inversion Action
897 Return: void
898 Remark:
899 *************************************************************************************************/
INTERN_DVBC_Clk_Inversion_Control(BOOLEAN bInversionEnable)900 void INTERN_DVBC_Clk_Inversion_Control(BOOLEAN bInversionEnable)
901 {
902 U8 u8Temp;
903
904 u8Temp = MDrv_ReadByte(0x103301);
905
906 if (bInversionEnable)
907 {
908 u8Temp = u8Temp | 0x02; //bit 9: clk inv
909 }
910 else
911 {
912 u8Temp = u8Temp & (~0x02);
913 }
914
915 DBG_INTERN_DVBC(printf("---> Inversion(Bit9) = 0x%bx \n",u8Temp));
916 MDrv_WriteByte(0x103301, u8Temp);
917 }
918 /************************************************************************************************
919 Subject: Transport stream serial/parallel control
920 Function: INTERN_DVBC_Serial_Control
921 Parmeter: bEnable : TRUE For serial
922 Return: BOOLEAN :
923 Remark:
924 *************************************************************************************************/
INTERN_DVBC_Serial_Control(BOOLEAN bEnable)925 BOOLEAN INTERN_DVBC_Serial_Control(BOOLEAN bEnable)
926 {
927 U8 status = true;
928
929 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_ts... \n"));
930
931 if (bEnable) //Serial mode for TS pad
932 {
933 // serial
934 MDrv_WriteByte(0x103308, 0x01); // serial mode: 0x0401
935 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
936
937 MDrv_WriteByte(0x103300, 0x00); // serial mode 0x0400
938 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
939 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
940 #else
941 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
942 #endif
943 MDrv_WriteByte(0x101EA5, MDrv_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
944
945 //// INTERN_DVBC TS Control: Serial //////////
946 gsCmdPacket.cmd_code = CMD_TS_CTRL;
947
948 gsCmdPacket.param[0] = TS_SERIAL;
949 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
950 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
951 #else
952 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
953 #endif
954 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacket, 2);
955 }
956 else
957 {
958 //parallel
959 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001
960 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
961
962 //MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
963 MDrv_WriteByte(0x103300, 0x13); // parallel mode: 0x0513 => ts_clk=288/(2*(0x13+1))=7.2MHz
964 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
965 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
966 #else
967 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
968 #endif
969 MDrv_WriteByte(0x101EA5, MDrv_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
970
971 //// INTERN_DVBT TS Control: Parallel //////////
972 gsCmdPacket.cmd_code = CMD_TS_CTRL;
973
974 gsCmdPacket.param[0] = TS_PARALLEL;
975 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
976 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
977 #else
978 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
979 #endif
980 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacket, 2);
981 }
982
983 DBG_INTERN_DVBC(printf("---> Inversion(Bit5) = 0x%bx \n",gsCmdPacket.param[1] ));
984
985 INTERN_DVBC_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
986
987 return status;
988 }
989
990
991 /************************************************************************************************
992 Subject: channel change config
993 Function: INTERN_DVBC_Config
994 Parmeter: u8QamMode: 0:16, 1:32, 2:64, 3:128, 4:256
995 Return: BOOLEAN :
996 Remark:
997 *************************************************************************************************/
INTERN_DVBC_Config(U16 u16SymbolRate,U8 u8QamMode,U32 u32IFFreq,BOOLEAN bSpecInv,BOOLEAN bSerialTS)998 BOOLEAN INTERN_DVBC_Config (U16 u16SymbolRate, U8 u8QamMode, U32 u32IFFreq, BOOLEAN bSpecInv, BOOLEAN bSerialTS)
999 {
1000 U8 status = TRUE;
1001 U8 reg_symrate_l;
1002 U8 reg_symrate_h;
1003 U16 u16Fs = 45470;
1004 U16 u16Fc = 0;
1005
1006 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_config\n"));
1007
1008 reg_symrate_l = (U8) (u16SymbolRate & 0xff);
1009 reg_symrate_h = (U8) (u16SymbolRate >> 8);
1010
1011 DBG_INTERN_DVBC(printf("u8QamMode = %d\n", (int)u8QamMode));
1012
1013 switch(u32IFFreq)
1014 {
1015 case 36125:
1016 case 36167:
1017 case 36000:
1018 case 6000:
1019 case 4560:
1020 u16Fc = u16Fs - (U16)u32IFFreq;
1021 DBG_INTERN_DVBC(printf("Fc freq = %d\n", (int)u16Fc));
1022 break;
1023 case 44000:
1024 default:
1025 printf("IF frequency not supported\n");
1026 break;
1027 }
1028
1029 status &= INTERN_DVBC_Reset();
1030
1031 //// INTERN_DVBC system init: DVB-C //////////
1032 gsCmdPacket.cmd_code = CMD_SYSTEM_INIT;
1033
1034 gsCmdPacket.param[0] = E_SYS_DVBC;
1035 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacket, 1);
1036
1037 //// DVB-T configurate ///////////////////
1038 gsCmdPacket.cmd_code = CMD_DVBT_CONFIG;
1039
1040 gsCmdPacket.param[p_opmode_rfagc_en] = 0;
1041 gsCmdPacket.param[p_opmode_humdet_en] = 0;
1042 gsCmdPacket.param[p_opmode_dcr_en] = 0;
1043 gsCmdPacket.param[p_opmode_iqb_en] = 0;
1044 gsCmdPacket.param[p_opmode_auto_iq_swap] = 1;
1045 gsCmdPacket.param[p_opmode_auto_fsa_left] = 1;
1046 gsCmdPacket.param[p_opmode_auto_rfmax] = 0;
1047 gsCmdPacket.param[p_opmode_mode_forced] = 0;
1048 gsCmdPacket.param[p_opmode_cp_forced] = 0;
1049 gsCmdPacket.param[pc_config_rssi] = 0;
1050 gsCmdPacket.param[pc_config_zif] = 0;
1051 gsCmdPacket.param[pc_config_fc_l] = (U8)(u16Fc & 0xff);
1052 gsCmdPacket.param[pc_config_fc_h] = (U8)(u16Fc >> 8);
1053 gsCmdPacket.param[pc_config_fs_l] = (U8)(u16Fs & 0xff);
1054 gsCmdPacket.param[pc_config_fs_h] = (U8)(u16Fs >> 8);
1055 gsCmdPacket.param[pc_config_bw] = reg_symrate_l; //0xdb; // Bandwidth-L
1056 gsCmdPacket.param[pc_config_fsa_left] = reg_symrate_h; //0x1A; // Bandwidth-H
1057 gsCmdPacket.param[pc_config_rfmax] = 1;
1058 gsCmdPacket.param[pc_config_lp_sel] = u8QamMode; // QAM- 0:16, 1:32, 2:64, 3:128, 4:256
1059 gsCmdPacket.param[pc_config_cp] = 3;
1060 gsCmdPacket.param[pc_config_mode] = 1;
1061 gsCmdPacket.param[pc_config_iq_swap] = bSpecInv;
1062 gsCmdPacket.param[pc_config_atv_system] = 1; //bPalBG? 0:1;
1063 gsCmdPacket.param[pc_config_serial_ts] = bSerialTS;
1064
1065 if (bSerialTS)
1066 {
1067 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1068 gsCmdPacket.param[pc_config_ts_out_inv] = false;
1069 #else
1070 gsCmdPacket.param[pc_config_ts_out_inv] = true;
1071 #endif
1072 }
1073 else
1074 {
1075 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1076 gsCmdPacket.param[pc_config_ts_out_inv] = false;
1077 #else
1078 gsCmdPacket.param[pc_config_ts_out_inv] = true;
1079 #endif
1080 }
1081 gsCmdPacket.param[pc_config_ts_data_swap] = FALSE;
1082
1083 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacket, DVBT_PARAM_LEN);
1084
1085 if(bSerialTS)
1086 {
1087 // serial
1088 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1089 MDrv_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1090
1091 MDrv_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1092 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1093 MDrv_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1094 #else
1095 MDrv_WriteByte(0x103301, 0x06); // reg_ckg_dvbtmk_ts_out_mode@0x00
1096 #endif
1097 }
1098 else
1099 {
1100 //parallel
1101 MDrv_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1102 MDrv_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1103
1104 //MDrv_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1105 MDrv_WriteByte(0x103300, 0x13); // parallel mode: 0x0513 => ts_clk=288/(2*(0x13+1))=7.2MHz
1106 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1107 MDrv_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1108 #else
1109 MDrv_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1110 #endif
1111 }
1112
1113 return status;
1114 }
1115 /************************************************************************************************
1116 Subject: enable hw to lock channel
1117 Function: INTERN_DVBC_Active
1118 Parmeter: bEnable
1119 Return: BOOLEAN
1120 Remark:
1121 *************************************************************************************************/
INTERN_DVBC_Active(BOOLEAN bEnable)1122 BOOLEAN INTERN_DVBC_Active(BOOLEAN bEnable)
1123 {
1124 U8 status = true;
1125
1126 DBG_INTERN_DVBC(printf(" @INTERN_DVBC_active\n"));
1127
1128 //// INTERN_DVBC Finite State Machine on/off //////////
1129 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1130
1131 gsCmdPacket.param[0] = (U8)bEnable;
1132 status &= INTERN_DVBC_Cmd_Packet_Send(&gsCmdPacket, 1);
1133
1134 return status;
1135 }
1136 /************************************************************************************************
1137 Subject: Return lock status
1138 Function: INTERN_DVBC_Lock
1139 Parmeter: eStatus :
1140 Return: BOOLEAN
1141 Remark:
1142 *************************************************************************************************/
INTERN_DVBC_Lock(QAM_LOCK_STATUS eStatus)1143 BOOLEAN INTERN_DVBC_Lock( QAM_LOCK_STATUS eStatus )
1144 {
1145 U16 u16Address;
1146 BYTE cData;
1147 BYTE cBitMask;
1148
1149 //static U32 u32FecLockTime;
1150
1151 switch( eStatus )
1152 {
1153 case QAM_FEC_LOCK:
1154 #if 1
1155 INTERN_DVBC_ReadReg(0x23E0, &cData);
1156 if (cData == 0x0C)
1157 {
1158 FECUnlockCnt = 64;
1159 return TRUE;
1160 }
1161 else if (FECUnlockCnt)
1162 {
1163 FECUnlockCnt--;
1164 return TRUE;
1165 }
1166 else
1167 {
1168 return FALSE;
1169 }
1170
1171 break;
1172 #else
1173 INTERN_DVBC_ReadReg(0x23E0, &cData);
1174 if (cData == 0x0B)
1175 {
1176 u32FecLockTime = MsOS_GetSystemTime();
1177 FECLock = TRUE;
1178 //printf("dmd_lock\n");
1179
1180 return TRUE;
1181 }
1182 else
1183 {
1184 if (FECLock == TRUE)
1185 {
1186 if ( ( MsOS_GetSystemTime() - u32FecLockTime ) < 3000 )
1187 return TRUE;
1188 }
1189 FECLock = FALSE;
1190 //printf("dmd_unlock\n");
1191 return FALSE; // continuously un-lock
1192 }
1193 break;
1194 #endif
1195
1196 case QAM_PSYNC_LOCK:
1197 u16Address = 0x232C; //FEC: P-sync Lock,
1198 cBitMask = BIT1;
1199 break;
1200
1201 case QAM_TPS_LOCK:
1202 u16Address = 0x2222; //TPS Lock,
1203 cBitMask = BIT1;
1204 break;
1205
1206 case QAM_DCR_LOCK:
1207 u16Address = 0x2145; //DCR Lock,
1208 cBitMask = BIT0;
1209 break;
1210
1211 case QAM_AGC_LOCK:
1212 u16Address = 0x212F; //AGC Lock,
1213 cBitMask = BIT0;
1214 break;
1215
1216 case QAM_MODE_DET:
1217 u16Address = 0x24CF; //Mode CP Detect,
1218 cBitMask = BIT4;
1219 break;
1220
1221 default:
1222 return FALSE;
1223 }
1224
1225 if (INTERN_DVBC_ReadReg(u16Address, &cData) == FALSE)
1226 return FALSE;
1227
1228 if ((cData & cBitMask) == cBitMask)
1229 {
1230 return TRUE;
1231 }
1232
1233 return FALSE;
1234
1235 }
1236
1237 /****************************************************************************
1238 Subject: To get the Post viterbi BER
1239 Function: INTERN_DVBC_GetPostViterbiBer
1240 Parmeter: Quility
1241 Return: E_RESULT_SUCCESS
1242 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
1243 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1244 We will not read the Period, and have the "/256/8"
1245 *****************************************************************************/
INTERN_DVBC_GetPostViterbiBer(float * ber)1246 BOOLEAN INTERN_DVBC_GetPostViterbiBer(float *ber)
1247 {
1248 U8 status = true;
1249 U8 reg, reg_frz;
1250 U16 BitErrPeriod;
1251 U32 BitErr;
1252 U16 PktErr;
1253
1254 /////////// Post-Viterbi BER /////////////
1255
1256 // bank 7 0x32 [7] reg_bit_err_num_freeze
1257 status &= INTERN_DVBC_ReadReg(0x2332, ®_frz);
1258 status &= INTERN_DVBC_WriteReg(0x2332, reg_frz|0x80);
1259
1260 // bank 7 0x30 [7:0] reg_bit_err_sblprd_7_0
1261 // [15:8] reg_bit_err_sblprd_15_8
1262 status &= INTERN_DVBC_ReadReg(0x2331, ®);
1263 BitErrPeriod = reg;
1264
1265 status &= INTERN_DVBC_ReadReg(0x2330, ®);
1266 BitErrPeriod = (BitErrPeriod << 8)|reg;
1267
1268 // bank 7 0x3a [7:0] reg_bit_err_num_7_0
1269 // [15:8] reg_bit_err_num_15_8
1270 // bank 7 0x3c [7:0] reg_bit_err_num_23_16
1271 // [15:8] reg_bit_err_num_31_24
1272
1273 status &= INTERN_DVBC_ReadReg(0x233D, ®);
1274 BitErr = reg;
1275
1276 status &= INTERN_DVBC_ReadReg(0x233C, ®);
1277 BitErr = (BitErr << 8)|reg;
1278
1279 status &= INTERN_DVBC_ReadReg(0x233B, ®);
1280 BitErr = (BitErr << 8)|reg;
1281
1282 status &= INTERN_DVBC_ReadReg(0x233A, ®);
1283 BitErr = (BitErr << 8)|reg;
1284
1285 // bank 7 0x3e [7:0] reg_uncrt_pkt_num_7_0
1286 // [15:8] reg_uncrt_pkt_num_15_8
1287 status &= INTERN_DVBC_ReadReg(0x233F, ®);
1288 PktErr = reg;
1289
1290 status &= INTERN_DVBC_ReadReg(0x233E, ®);
1291 PktErr = (PktErr << 8)|reg;
1292
1293 // bank 7 0x32 [7] reg_bit_err_num_freeze
1294 status &= INTERN_DVBC_WriteReg(0x2332, reg_frz);
1295
1296 if (BitErrPeriod == 0 ) //protect 0
1297 BitErrPeriod = 1;
1298
1299 if (BitErr <=0 )
1300 *ber = 0.5 / ((float)BitErrPeriod*128*188*8);
1301 else
1302 *ber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
1303
1304
1305 DBG_GET_SIGNAL(printf("INTERN_DVBC PostVitBER = %8.3e \n ", *ber));
1306 DBG_GET_SIGNAL(printf("INTERN_DVBC PktErr = %d \n ", (int)PktErr));
1307
1308
1309 return status;
1310 }
1311
1312 /****************************************************************************
1313 Subject: Function providing approx. result of Log10(X)
1314 Function: Log10Approx
1315 Parmeter: Operand X in float
1316 Return: Approx. value of Log10(X) in float
1317 Remark: Ouput range from 0.0, 0.3 to 9.6 (input 1 to 2^32)
1318 *****************************************************************************/
Log10Approx(float flt_x)1319 static float Log10Approx(float flt_x)
1320 {
1321 U32 u32_temp = 1;
1322 U8 indx = 0;
1323
1324 do {
1325 u32_temp = u32_temp << 1;
1326 if (flt_x < (float)u32_temp)
1327 break;
1328 }while (++indx < 32);
1329
1330 // 10*log10(X) ~= 0.3*N, when X ~= 2^N
1331 return (float)0.3 * indx;
1332 }
1333
1334 /****************************************************************************
1335 Subject: Read the signal to noise ratio (SNR)
1336 Function: INTERN_DVBC_GetSNR
1337 Parmeter: None
1338 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1339 Remark:
1340 *****************************************************************************/
INTERN_DVBC_GetSNR(void)1341 float INTERN_DVBC_GetSNR (void)
1342 {
1343 U8 status = true;
1344 U8 reg, reg_frz;
1345 U32 noise_power;
1346 float snr;
1347
1348 // bank 6 0xfe [0] reg_fdp_freeze
1349 status &= INTERN_DVBC_ReadReg(0x22fe, ®_frz);
1350 status &= INTERN_DVBC_WriteReg(0x22fe, reg_frz|0x01);
1351
1352 // bank 6 0xff [0] reg_fdp_load
1353 status &= INTERN_DVBC_ReadReg(0x22ff, ®);
1354
1355 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1356 status &= INTERN_DVBC_ReadReg(0x224d, ®);
1357 noise_power = reg & 0x07;
1358
1359 status &= INTERN_DVBC_ReadReg(0x224c, ®);
1360 noise_power = (noise_power << 8)|reg;
1361
1362 status &= INTERN_DVBC_ReadReg(0x224b, ®);
1363 noise_power = (noise_power << 8)|reg;
1364
1365 status &= INTERN_DVBC_ReadReg(0x224a, ®);
1366 noise_power = (noise_power << 8)|reg;
1367
1368 noise_power = noise_power/2;
1369
1370 // bank 6 0x26 [5:4] reg_transmission_mode
1371 status &= INTERN_DVBC_ReadReg(0x2226, ®);
1372
1373 // bank 6 0xfe [0] reg_fdp_freeze
1374 status &= INTERN_DVBC_WriteReg(0x22fe, reg_frz);
1375
1376 if ((reg&0x03)==0x00) //2K
1377 {
1378 if (noise_power<1512)
1379 snr = 0;
1380 else
1381 snr = 10*Log10Approx((float)noise_power/1512);
1382 }
1383 //else if ((reg&0x03)==0x01)//8K
1384 else
1385 {
1386 if (noise_power<6048)
1387 snr = 0;
1388 else
1389 snr = 10*Log10Approx((float)noise_power/6048);
1390 }
1391 /* ignore 4K
1392 else //4K
1393 {
1394 if (noise_power<3024)
1395 snr = 0;
1396 else
1397 snr = 10*Log10Approx(noise_power/3024);
1398 }
1399 */
1400
1401 if (status == true)
1402 return snr;
1403 else
1404 return -1;
1405
1406 }
1407
INTERN_DVBC_GetSignalStrength(WORD * strength)1408 FUNCTION_RESULT INTERN_DVBC_GetSignalStrength(WORD *strength)
1409 {
1410 *strength = 80;
1411 return E_RESULT_SUCCESS;
1412 }
1413
1414 /****************************************************************************
1415 Subject: To get the DVT Signal quility
1416 Function: INTERN_DVBC_GetSignalQuality
1417 Parmeter: Quility
1418 Return: E_RESULT_SUCCESS
1419 E_RESULT_FAILURE
1420 Remark: Here we have 4 level range
1421 <1>.First Range => Quility =100 (You can define it by INTERN_DVBC_SIGNAL_BASE_100)
1422 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBC_SIGNAL_BASE_60)
1423 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBC_SIGNAL_BASE_10)
1424 <4>.4th Range => Quality <10
1425 *****************************************************************************/
INTERN_DVBC_GetSignalQuality(WORD * quality)1426 FUNCTION_RESULT INTERN_DVBC_GetSignalQuality(WORD *quality)
1427 {
1428 float fber;
1429 float log_ber;
1430
1431 if (TRUE == INTERN_DVBC_Lock(QAM_FEC_LOCK) )
1432 {
1433 if (INTERN_DVBC_GetPostViterbiBer(&fber) == FALSE)
1434 {
1435 DBG_INTERN_DVBC(printf("GetPostViterbiBer Fail!\n"));
1436 return E_RESULT_FAILURE;
1437 }
1438
1439 log_ber = (-1)*Log10Approx(1/fber); // Log10Approx() provide 1~2^32 input range only
1440
1441 DBG_GET_SIGNAL(printf("Log(BER) = %f\n",log_ber));
1442
1443 if ( log_ber <= (-7.0) ) // PostVit BER < 1e-7
1444 {
1445 *quality = 100;
1446 }
1447 else if ( log_ber < (-3.7) ) // PostVit BER < 2e-4
1448 {
1449 *quality = 60 + (((-3.7) - log_ber) / ((-3.7)-(-7.0)) * (100-60));
1450 }
1451 else if ( log_ber < (-2.7) ) // PostVit BER < 2e-3
1452 {
1453 *quality = 10 + (((-2.7) - log_ber) / ((-2.7)-(-3.7)) * (60-10));
1454 }
1455 else
1456 {
1457 *quality = 10;
1458 }
1459
1460 }
1461 else
1462 {
1463 *quality = 0;
1464 }
1465
1466 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", (int)*quality));
1467
1468 return E_RESULT_SUCCESS;
1469
1470 }
1471
1472
1473 /****************************************************************************
1474 Subject: To get the DVBC Carrier Freq Offset
1475 Function: INTERN_DVBC_Get_FreqOffset
1476 Parmeter: Frequency offset (in KHz), bandwidth
1477 Return: E_RESULT_SUCCESS
1478 E_RESULT_FAILURE
1479 Remark:
1480 *****************************************************************************/
INTERN_DVBC_Get_FreqOffset(float * pFreqOff,U8 u8BW)1481 FUNCTION_RESULT INTERN_DVBC_Get_FreqOffset(float *pFreqOff, U8 u8BW)
1482 {
1483 float N, FreqB;
1484 float FreqCfoTd, FreqCfoFd, FreqIcfo;
1485 U32 RegCfoTd, RegCfoFd, RegIcfo;
1486 U8 reg_frz, reg;
1487 U8 status;
1488
1489 FreqB = (float)u8BW * 8 / 7;
1490
1491 status = INTERN_DVBC_ReadReg(0x2104+1, ®_frz);
1492
1493 status &= INTERN_DVBC_WriteReg(0x2104+1, reg_frz|0x80);
1494
1495 status &= INTERN_DVBC_ReadReg(0x24c6+2, ®);
1496 RegCfoTd = reg;
1497
1498 status &= INTERN_DVBC_ReadReg(0x24c6+1, ®);
1499 RegCfoTd = (RegCfoTd << 8)|reg;
1500
1501 status &= INTERN_DVBC_ReadReg(0x24c6, ®);
1502 RegCfoTd = (RegCfoTd << 8)|reg;
1503
1504 FreqCfoTd = (float)RegCfoTd;
1505
1506 if (RegCfoTd & 0x800000)
1507 FreqCfoTd = FreqCfoTd - (float)0x1000000;
1508
1509 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
1510
1511 status &= INTERN_DVBC_WriteReg(0x2104+1, reg_frz&(~0x80));
1512
1513 status &= INTERN_DVBC_ReadReg(0x22fe, ®_frz);
1514 status &= INTERN_DVBC_WriteReg(0x22fe, reg_frz|0x01);
1515
1516 //status &= INTERN_DVBC_WriteReg(0x22fe+1, 0x01);
1517 status &= INTERN_DVBC_WriteReg(0x22ff, 0x01);
1518
1519 status &= INTERN_DVBC_ReadReg(0x2230+3, ®);
1520 RegCfoFd = reg;
1521
1522 status &= INTERN_DVBC_ReadReg(0x2230+2, ®);
1523 RegCfoFd = (RegCfoFd << 8)|reg;
1524
1525 status &= INTERN_DVBC_ReadReg(0x2230+1, ®);
1526 RegCfoFd = (RegCfoFd << 8)|reg;
1527
1528 FreqCfoFd = (float)RegCfoFd;
1529
1530 if (RegCfoFd & 0x800000)
1531 FreqCfoFd = FreqCfoFd - (float)0x1000000;
1532
1533 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
1534
1535 status &= INTERN_DVBC_ReadReg(0x2218+1, ®);
1536 RegIcfo = reg & 0x07;
1537
1538 status &= INTERN_DVBC_ReadReg(0x2218, ®);
1539 RegIcfo = (RegIcfo << 8)|reg;
1540
1541 FreqIcfo = (float)RegIcfo;
1542
1543 if (RegIcfo & 0x400)
1544 FreqIcfo = FreqIcfo - (float)0x800;
1545
1546 status &= INTERN_DVBC_ReadReg(0x2226, ®);
1547 reg = reg & 0x30;
1548
1549 switch (reg)
1550 {
1551 case 0x00: N = 2048; break;
1552 case 0x20: N = 4096; break;
1553 case 0x10:
1554 default: N = 8192; break;
1555 }
1556
1557 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
1558 status &= INTERN_DVBC_WriteReg(0x22fe, reg_frz&(~0x01));
1559 //status &= INTERN_DVBC_WriteReg(0x22fe+1, 0x01);
1560 status &= INTERN_DVBC_WriteReg(0x22ff, 0x01);
1561 *pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
1562
1563 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
1564 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
1565 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
1566 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
1567
1568 if (status == TRUE)
1569 return E_RESULT_SUCCESS;
1570 else
1571 return E_RESULT_FAILURE;
1572 }
1573
1574
INTERN_DVBC_Power_ON_OFF(U8 bPowerOn)1575 void INTERN_DVBC_Power_ON_OFF(U8 bPowerOn)
1576 {
1577
1578 bPowerOn = bPowerOn;
1579 }
1580
INTERN_DVBC_Power_Save(void)1581 BOOLEAN INTERN_DVBC_Power_Save(void)
1582 {
1583
1584 return TRUE;
1585 }
1586
1587 /****************************************************************************
1588 Subject: To get the DVBC constellation parameter
1589 Function: INTERN_DVBC_Get_TPS_Parameter_Const
1590 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
1591 Return: TRUE
1592 FALSE
1593 Remark: The TPS parameters will be available after TPS lock
1594 *****************************************************************************/
INTERN_DVBC_Get_TPS_Parameter_Const(WORD * TPS_parameter)1595 BOOLEAN INTERN_DVBC_Get_TPS_Parameter_Const( WORD * TPS_parameter)
1596 {
1597 U8 tps_param;
1598
1599 if ( INTERN_DVBC_ReadReg(0x2224, &tps_param) == FALSE )
1600 return FALSE;
1601
1602 *TPS_parameter = tps_param & (BIT0|BIT1) ;
1603 return TRUE;
1604 }
1605
1606 /***********************************************************************************
1607 Subject: read register
1608 Function: MDrv_1210_IIC_Bypass_Mode
1609 Parmeter:
1610 Return:
1611 Remark:
1612 ************************************************************************************/
1613 //void MDrv_1210_IIC_Bypass_Mode(BOOLEAN enable)
1614 //{
1615 // UNUSED(enable);
1616 // if (enable)
1617 // INTERN_DVBC_WriteReg(0x8010, 0x10); // IIC by-pass mode on
1618 // else
1619 // INTERN_DVBC_WriteReg(0x8010, 0x00); // IIC by-pass mode off
1620 //}
1621
1622