1ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK 2 3Required properties (phy (parent) node): 4 - compatible: should be one of the listed compatibles: 5 * "rockchip,rk3328-u3phy" 6 * "rockchip,rk322xh-u3phy" 7 - reg : the base address of USB 3.0 PHY. 8 - rockchip,u3phygrf : phandle to the syscon managing the 9 "USB 3.0 PHY general register files". 10 - interrupts : specify an interrupt for each entry in interrupt-names. 11 - interrupt-names : a list which shall be the following entries: 12 * "linestate" : for the host/otg linestate interrupt 13 - clocks : phandle + clock specifier for the phy clocks. 14 - clock-names : 15 * "u3phy-otg" for USB 3.0 PHY utmi 16 * "u3phy-pipe" for USB 3.0 PHY pipe 17 - resets : a list of phandle + reset specifier pairs 18 - reset-names : 19 * "u3phy-u2-por" for the USB 2.0 logic of USB 3.0 PHY 20 * "u3phy-u3-por" for the USB 3.0 logic of USB 3.0 PHY 21 * "u3phy-pipe-mac" for the USB 3.0 PHY pipe MAC 22 * "u3phy-utmi-mac" for the USB 3.0 PHY utmi MAC 23 * "u3phy-utmi-apb" for the USB 3.0 PHY utmi apb 24 * "u3phy-pipe-apb" for the USB 3.0 PHY pipe apb 25 26Optional properties: 27 - vbus-supply: regulator phandle for vbus power source. 28 29Required nodes : a sub-node is required for USB 3.0 or USB 2.0 the phy provides. 30 The sub-node name is used to identify phy type, and shall be 31 the following entries: 32 * "u3phy_utmi" : USB 2.0 utmi phy. 33 * "u3phy_pipe" : USB 3.0 pipe phy. 34 35Required properties (port (child) node): 36 - reg : address and length of the register set for the port. 37 - #phy-cells : must be 0. See ./phy-bindings.txt for details. 38 39Optional properties for utmi node: 40 - rockchip,odt-val-tuning : specify 45ohm ODT tuning value. 41 42Optional properties for pipe node: 43 - rockchip,refclk-25m-quirk : phy reference clock changed to 25m quirk. 44 45Example: 46 47usb3phy_grf: syscon@ff460000 { 48 compatible = "rockchip,usb3phy-grf", "syscon"; 49 reg = <0x0 0xff460000 0x0 0x1000>; 50}; 51 52... 53 54u3phy: usb3-phy@ff470000 { 55 compatible = "rockchip,rk3328-u3phy"; 56 reg = <0x0 0xff470000 0x0 0x0>; 57 rockchip,u3phygrf = <&usb3phy_grf>; 58 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 59 interrupt-names = "linestate"; 60 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; 61 clock-names = "u3phy-otg", "u3phy-pipe"; 62 resets = <&cru SRST_USB3PHY_U2>, 63 <&cru SRST_USB3PHY_U3>, 64 <&cru SRST_USB3PHY_PIPE>, 65 <&cru SRST_USB3OTG_UTMI>, 66 <&cru SRST_USB3PHY_OTG_P>, 67 <&cru SRST_USB3PHY_PIPE_P>; 68 reset-names = "u3phy-u2-por", "u3phy-u3-por", 69 "u3phy-pipe-mac", "u3phy-utmi-mac", 70 "u3phy-utmi-apb", "u3phy-pipe-apb"; 71 #address-cells = <2>; 72 #size-cells = <2>; 73 ranges; 74 75 u3phy_utmi: utmi@ff470000 { 76 reg = <0x0 0xff470000 0x0 0x8000>; 77 #phy-cells = <0>; 78 }; 79 80 u3phy_pipe: pipe@ff478000 { 81 reg = <0x0 0xff478000 0x0 0x8000>; 82 #phy-cells = <0>; 83 }; 84}; 85