1From 2dc8450e80b82c481904570dce789843b031db13 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:13 +0100
4Subject: [PATCH 18/21] target/ppc: Implement Vector Extract Mask
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Implement the following PowerISA v3.1 instructions:
10vextractbm: Vector Extract Byte Mask
11vextracthm: Vector Extract Halfword Mask
12vextractwm: Vector Extract Word Mask
13vextractdm: Vector Extract Doubleword Mask
14vextractqm: Vector Extract Quadword Mask
15
16Upstream-Status: Backport
17[https://git.qemu.org/?p=qemu.git;a=commit;h=17868d81e0074905b2c1e414af6618570e8059eb]
18
19Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
20Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br>
22Signed-off-by: Cédric Le Goater <clg@kaod.org>
23Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
24---
25 target/ppc/insn32.decode            |  6 +++
26 target/ppc/translate/vmx-impl.c.inc | 82 +++++++++++++++++++++++++++++
27 2 files changed, 88 insertions(+)
28
29diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
30index e032251c74..b0568b1356 100644
31--- a/target/ppc/insn32.decode
32+++ b/target/ppc/insn32.decode
33@@ -423,6 +423,12 @@ VEXPANDWM       000100 ..... 00010 ..... 11001000010    @VX_tb
34 VEXPANDDM       000100 ..... 00011 ..... 11001000010    @VX_tb
35 VEXPANDQM       000100 ..... 00100 ..... 11001000010    @VX_tb
36
37+VEXTRACTBM      000100 ..... 01000 ..... 11001000010    @VX_tb
38+VEXTRACTHM      000100 ..... 01001 ..... 11001000010    @VX_tb
39+VEXTRACTWM      000100 ..... 01010 ..... 11001000010    @VX_tb
40+VEXTRACTDM      000100 ..... 01011 ..... 11001000010    @VX_tb
41+VEXTRACTQM      000100 ..... 01100 ..... 11001000010    @VX_tb
42+
43 # VSX Load/Store Instructions
44
45 LXV             111101 ..... ..... ............ . 001   @DQ_TSX
46diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
47index ebb0484323..96c97bf6e7 100644
48--- a/target/ppc/translate/vmx-impl.c.inc
49+++ b/target/ppc/translate/vmx-impl.c.inc
50@@ -1525,6 +1525,88 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
51     return true;
52 }
53
54+static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
55+{
56+    const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
57+                   mask = dup_const(vece, 1 << (elem_width - 1));
58+    uint64_t i, j;
59+    TCGv_i64 lo, hi, t0, t1;
60+
61+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
62+    REQUIRE_VECTOR(ctx);
63+
64+    hi = tcg_temp_new_i64();
65+    lo = tcg_temp_new_i64();
66+    t0 = tcg_temp_new_i64();
67+    t1 = tcg_temp_new_i64();
68+
69+    get_avr64(lo, a->vrb, false);
70+    get_avr64(hi, a->vrb, true);
71+
72+    tcg_gen_andi_i64(lo, lo, mask);
73+    tcg_gen_andi_i64(hi, hi, mask);
74+
75+    /*
76+     * Gather the most significant bit of each element in the highest element
77+     * element. E.g. for bytes:
78+     * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
79+     *     & dup(1 << (elem_width - 1))
80+     * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
81+     *     << 32 - 4
82+     * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
83+     *     |
84+     * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
85+     *     << 16 - 2
86+     * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
87+     *     |
88+     * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
89+     *     << 8 - 1
90+     * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
91+     *     |
92+     * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
93+     */
94+    for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
95+        tcg_gen_shli_i64(t0, hi, j - i);
96+        tcg_gen_shli_i64(t1, lo, j - i);
97+        tcg_gen_or_i64(hi, hi, t0);
98+        tcg_gen_or_i64(lo, lo, t1);
99+    }
100+
101+    tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
102+    tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
103+    tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
104+
105+    tcg_temp_free_i64(hi);
106+    tcg_temp_free_i64(lo);
107+    tcg_temp_free_i64(t0);
108+    tcg_temp_free_i64(t1);
109+
110+    return true;
111+}
112+
113+TRANS(VEXTRACTBM, do_vextractm, MO_8)
114+TRANS(VEXTRACTHM, do_vextractm, MO_16)
115+TRANS(VEXTRACTWM, do_vextractm, MO_32)
116+TRANS(VEXTRACTDM, do_vextractm, MO_64)
117+
118+static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
119+{
120+    TCGv_i64 tmp;
121+
122+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
123+    REQUIRE_VECTOR(ctx);
124+
125+    tmp = tcg_temp_new_i64();
126+
127+    get_avr64(tmp, a->vrb, true);
128+    tcg_gen_shri_i64(tmp, tmp, 63);
129+    tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
130+
131+    tcg_temp_free_i64(tmp);
132+
133+    return true;
134+}
135+
136 #define GEN_VAFORM_PAIRED(name0, name1, opc2)                           \
137 static void glue(gen_, name0##_##name1)(DisasContext *ctx)              \
138     {                                                                   \
139--
1402.17.1
141
142