1From 232f979babccd6dfac40a54ee33521e652a0577c Mon Sep 17 00:00:00 2001 2From: Luis Pires <luis.pires@eldorado.org.br> 3Date: Wed, 2 Mar 2022 06:51:36 +0100 4Subject: [PATCH 16/21] target/ppc: Introduce TRANS*FLAGS macros 5MIME-Version: 1.0 6Content-Type: text/plain; charset=UTF-8 7Content-Transfer-Encoding: 8bit 8 9New macros that add FLAGS and FLAGS2 checking were added for 10both TRANS and TRANS64. 11 12Upstream-Status: Backport 13[https://git.qemu.org/?p=qemu.git;a=commit;h=19f0862dd8fa6510b2f5b3aff4859363602cd0cf] 14 15Reviewed-by: Richard Henderson <richard.henderson@linaro.org> 16Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> 17[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E 18 - Use the new macros in load/store vector insns ] 19Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> 20Message-Id: <20220225210936.1749575-2-matheus.ferst@eldorado.org.br> 21Signed-off-by: Cédric Le Goater <clg@kaod.org> 22Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com> 23--- 24 target/ppc/translate.c | 19 +++++++++++++++ 25 target/ppc/translate/vsx-impl.c.inc | 37 ++++++++++------------------- 26 2 files changed, 31 insertions(+), 25 deletions(-) 27 28diff --git a/target/ppc/translate.c b/target/ppc/translate.c 29index 9960df6e18..c12abc32f6 100644 30--- a/target/ppc/translate.c 31+++ b/target/ppc/translate.c 32@@ -7377,10 +7377,29 @@ static int times_16(DisasContext *ctx, int x) 33 #define TRANS(NAME, FUNC, ...) \ 34 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 35 { return FUNC(ctx, a, __VA_ARGS__); } 36+#define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 37+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 38+ { \ 39+ REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 40+ return FUNC(ctx, a, __VA_ARGS__); \ 41+ } 42+#define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 43+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 44+ { \ 45+ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 46+ return FUNC(ctx, a, __VA_ARGS__); \ 47+ } 48 49 #define TRANS64(NAME, FUNC, ...) \ 50 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 51 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 52+#define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 53+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 54+ { \ 55+ REQUIRE_64BIT(ctx); \ 56+ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 57+ return FUNC(ctx, a, __VA_ARGS__); \ 58+ } 59 60 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 61 62diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc 63index c08185e857..99c8a57e50 100644 64--- a/target/ppc/translate/vsx-impl.c.inc 65+++ b/target/ppc/translate/vsx-impl.c.inc 66@@ -2070,12 +2070,6 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ, 67 68 static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired) 69 { 70- if (paired) { 71- REQUIRE_INSNS_FLAGS2(ctx, ISA310); 72- } else { 73- REQUIRE_INSNS_FLAGS2(ctx, ISA300); 74- } 75- 76 if (paired || a->rt >= 32) { 77 REQUIRE_VSX(ctx); 78 } else { 79@@ -2089,7 +2083,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a, 80 bool store, bool paired) 81 { 82 arg_D d; 83- REQUIRE_INSNS_FLAGS2(ctx, ISA310); 84 REQUIRE_VSX(ctx); 85 86 if (!resolve_PLS_D(ctx, &d, a)) { 87@@ -2101,12 +2094,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a, 88 89 static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired) 90 { 91- if (paired) { 92- REQUIRE_INSNS_FLAGS2(ctx, ISA310); 93- } else { 94- REQUIRE_INSNS_FLAGS2(ctx, ISA300); 95- } 96- 97 if (paired || a->rt >= 32) { 98 REQUIRE_VSX(ctx); 99 } else { 100@@ -2116,18 +2103,18 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired) 101 return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired); 102 } 103 104-TRANS(STXV, do_lstxv_D, true, false) 105-TRANS(LXV, do_lstxv_D, false, false) 106-TRANS(STXVP, do_lstxv_D, true, true) 107-TRANS(LXVP, do_lstxv_D, false, true) 108-TRANS(STXVX, do_lstxv_X, true, false) 109-TRANS(LXVX, do_lstxv_X, false, false) 110-TRANS(STXVPX, do_lstxv_X, true, true) 111-TRANS(LXVPX, do_lstxv_X, false, true) 112-TRANS64(PSTXV, do_lstxv_PLS_D, true, false) 113-TRANS64(PLXV, do_lstxv_PLS_D, false, false) 114-TRANS64(PSTXVP, do_lstxv_PLS_D, true, true) 115-TRANS64(PLXVP, do_lstxv_PLS_D, false, true) 116+TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false) 117+TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false) 118+TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true) 119+TRANS_FLAGS2(ISA310, LXVP, do_lstxv_D, false, true) 120+TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false) 121+TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false) 122+TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true) 123+TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true) 124+TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false) 125+TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false) 126+TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true) 127+TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true) 128 129 static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b, 130 TCGv_vec c) 131-- 1322.17.1 133 134