1From c76ea6322bd70c36c9b396cf356167b36928e811 Mon Sep 17 00:00:00 2001
2From: Matheus Ferst <matheus.ferst@eldorado.org.br>
3Date: Fri, 17 Dec 2021 17:57:18 +0100
4Subject: [PATCH 14/21] target/ppc: move xscvqpdp to decodetree
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Upstream-Status: Backport
10[https://git.qemu.org/?p=qemu.git;a=commit;h=caf6f9b568479bea6f6d97798be670f21641a006]
11
12Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
14Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br>
15Signed-off-by: Cédric Le Goater <clg@kaod.org>
16Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
17---
18 target/ppc/fpu_helper.c             | 10 +++-------
19 target/ppc/helper.h                 |  2 +-
20 target/ppc/insn32.decode            |  4 ++++
21 target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
22 target/ppc/translate/vsx-ops.c.inc  |  1 -
23 5 files changed, 21 insertions(+), 20 deletions(-)
24
25diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
26index ecdcd36a11..5cc7fb1dcb 100644
27--- a/target/ppc/fpu_helper.c
28+++ b/target/ppc/fpu_helper.c
29@@ -2631,18 +2631,14 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
30 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i  + 1), 0)
31 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
32
33-/*
34- * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
35- * added to this later.
36- */
37-void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
38-                     ppc_vsr_t *xt, ppc_vsr_t *xb)
39+void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
40+                     ppc_vsr_t *xb)
41 {
42     ppc_vsr_t t = { };
43     float_status tstat;
44
45     tstat = env->fp_status;
46-    if (unlikely(Rc(opcode) != 0)) {
47+    if (ro != 0) {
48         tstat.float_rounding_mode = float_round_to_odd;
49     }
50
51diff --git a/target/ppc/helper.h b/target/ppc/helper.h
52index 12a3d5f269..ef5bdd38a7 100644
53--- a/target/ppc/helper.h
54+++ b/target/ppc/helper.h
55@@ -400,7 +400,7 @@ DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
56 DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
57 DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
58 DEF_HELPER_2(xscvdpspn, i64, env, i64)
59-DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr)
60+DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr)
61 DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
62 DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
63 DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
64diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
65index 759b2a9aa5..fd6bb13fa0 100644
66--- a/target/ppc/insn32.decode
67+++ b/target/ppc/insn32.decode
68@@ -438,3 +438,7 @@ XSMAXCDP        111100 ..... ..... ..... 10000000 ...   @XX3
69 XSMINCDP        111100 ..... ..... ..... 10001000 ...   @XX3
70 XSMAXJDP        111100 ..... ..... ..... 10010000 ...   @XX3
71 XSMINJDP        111100 ..... ..... ..... 10011000 ...   @XX3
72+
73+## VSX Binary Floating-Point Convert Instructions
74+
75+XSCVQPDP        111111 ..... 10100 ..... 1101000100 .   @X_tb_rc
76diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
77index ab5cb21f13..c08185e857 100644
78--- a/target/ppc/translate/vsx-impl.c.inc
79+++ b/target/ppc/translate/vsx-impl.c.inc
80@@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
81 VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
82 VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
83
84-static void gen_xscvqpdp(DisasContext *ctx)
85+static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
86 {
87-    TCGv_i32 opc;
88+    TCGv_i32 ro;
89     TCGv_ptr xt, xb;
90-    if (unlikely(!ctx->vsx_enabled)) {
91-        gen_exception(ctx, POWERPC_EXCP_VSXU);
92-        return;
93-    }
94-    opc = tcg_const_i32(ctx->opcode);
95
96-    xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
97-    xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
98-    gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
99-    tcg_temp_free_i32(opc);
100+    REQUIRE_INSNS_FLAGS2(ctx, ISA300);
101+    REQUIRE_VSX(ctx);
102+
103+    ro = tcg_const_i32(a->rc);
104+
105+    xt = gen_avr_ptr(a->rt);
106+    xb = gen_avr_ptr(a->rb);
107+    gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
108+    tcg_temp_free_i32(ro);
109     tcg_temp_free_ptr(xt);
110     tcg_temp_free_ptr(xb);
111+
112+    return true;
113 }
114
115 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type)                         \
116diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
117index f980bc1bae..c974324c4c 100644
118--- a/target/ppc/translate/vsx-ops.c.inc
119+++ b/target/ppc/translate/vsx-ops.c.inc
120@@ -133,7 +133,6 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
121 GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
122 GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
123 GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
124-GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
125 GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
126 GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
127 GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
128--
1292.17.1
130
131