1From 613f373f0b652ab2fb2572633e7a23807096790b Mon Sep 17 00:00:00 2001
2From: Richard Henderson <richard.henderson@linaro.org>
3Date: Fri, 17 Dec 2021 17:57:14 +0100
4Subject: [PATCH 03/21] softfloat: Add flag specific to Inf * 0
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9PowerPC has this flag, and it's easier to compute it here
10than after the fact.
11
12Upstream-Status: Backport
13[https://git.qemu.org/?p=qemu.git;a=commit;h=bead3c9b0ff8efd652afb27923d8ab4458b3bbd9]
14
15Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
17Signed-off-by: Cédric Le Goater <clg@kaod.org>
18Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
19---
20 fpu/softfloat-parts.c.inc      |  4 ++--
21 fpu/softfloat-specialize.c.inc | 12 ++++++------
22 include/fpu/softfloat-types.h  |  1 +
23 3 files changed, 9 insertions(+), 8 deletions(-)
24
25diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
26index eb2b475ca4..3ed793347b 100644
27--- a/fpu/softfloat-parts.c.inc
28+++ b/fpu/softfloat-parts.c.inc
29@@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,
30
31     /* Inf * Zero == NaN */
32     if (unlikely(ab_mask == float_cmask_infzero)) {
33-        float_raise(float_flag_invalid, s);
34+        float_raise(float_flag_invalid | float_flag_invalid_imz, s);
35         parts_default_nan(a, s);
36         return a;
37     }
38@@ -489,6 +489,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
39
40     if (unlikely(ab_mask != float_cmask_normal)) {
41         if (unlikely(ab_mask == float_cmask_infzero)) {
42+            float_raise(float_flag_invalid | float_flag_invalid_imz, s);
43             goto d_nan;
44         }
45
46@@ -567,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
47     goto finish_sign;
48
49  d_nan:
50-    float_raise(float_flag_invalid, s);
51     parts_default_nan(a, s);
52     return a;
53 }
54diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
55index f2ad0f335e..943e3301d2 100644
56--- a/fpu/softfloat-specialize.c.inc
57+++ b/fpu/softfloat-specialize.c.inc
58@@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
59      * the default NaN
60      */
61     if (infzero && is_qnan(c_cls)) {
62-        float_raise(float_flag_invalid, status);
63+        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
64         return 3;
65     }
66
67@@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
68          * case sets InvalidOp and returns the default NaN
69          */
70         if (infzero) {
71-            float_raise(float_flag_invalid, status);
72+            float_raise(float_flag_invalid | float_flag_invalid_imz, status);
73             return 3;
74         }
75         /* Prefer sNaN over qNaN, in the a, b, c order. */
76@@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
77          * case sets InvalidOp and returns the input value 'c'
78          */
79         if (infzero) {
80-            float_raise(float_flag_invalid, status);
81+            float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82             return 2;
83         }
84         /* Prefer sNaN over qNaN, in the c, a, b order. */
85@@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86      * a default NaN
87      */
88     if (infzero) {
89-        float_raise(float_flag_invalid, status);
90+        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
91         return 2;
92     }
93
94@@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
95 #elif defined(TARGET_RISCV)
96     /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
97     if (infzero) {
98-        float_raise(float_flag_invalid, status);
99+        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
100     }
101     return 3; /* default NaN */
102 #elif defined(TARGET_XTENSA)
103@@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
104      * an input NaN if we have one (ie c).
105      */
106     if (infzero) {
107-        float_raise(float_flag_invalid, status);
108+        float_raise(float_flag_invalid | float_flag_invalid_imz, status);
109         return 2;
110     }
111     if (status->use_first_nan) {
112diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
113index eaa12e1e00..56b4cf7835 100644
114--- a/include/fpu/softfloat-types.h
115+++ b/include/fpu/softfloat-types.h
116@@ -153,6 +153,7 @@ enum {
117     float_flag_input_denormal  = 0x0020,
118     float_flag_output_denormal = 0x0040,
119     float_flag_invalid_isi     = 0x0080,  /* inf - inf */
120+    float_flag_invalid_imz     = 0x0100,  /* inf * 0 */
121 };
122
123 /*
124--
1252.17.1
126
127