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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHVD.h 98 /// @brief HVD Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HVD_H_ 103 #define _REG_HVD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 115 //***************************************************************************** 116 // RIU macro 117 #define HVD_MACRO_START do { 118 #define HVD_MACRO_END } while (0) 119 #define HVD_RIU_BASE (u32HVDRegOSBase) 120 121 #define HVD_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 122 #define HVD_LOWBYTE(u16) ((MS_U8)(u16)) 123 #define HVD_RIU_READ_BYTE(addr) ( READ_BYTE( HVD_RIU_BASE + (addr) ) ) 124 #define HVD_RIU_READ_WORD(addr) ( READ_WORD( HVD_RIU_BASE + (addr) ) ) 125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } 126 #define HVD_RIU_WRITE_WORD(addr, val) { WRITE_WORD( HVD_RIU_BASE+(addr), val); } 127 128 129 #define _HVD_ReadByte( u32Reg ) HVD_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 130 131 #define _HVD_Read2Byte( u32Reg ) (HVD_RIU_READ_WORD((u32Reg)<<1)) 132 133 #define _HVD_Read4Byte( u32Reg ) ( (MS_U32)HVD_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)HVD_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 134 135 #define _HVD_ReadRegBit( u32Reg, u8Mask ) (HVD_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 136 137 #define _HVD_ReadWordBit( u32Reg, u16Mask ) (_HVD_Read2Byte( u32Reg ) & (u16Mask)) 138 139 #define _HVD_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 140 HVD_MACRO_START \ 141 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 142 (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 143 HVD_MACRO_END 144 145 #define _HVD_WriteByte( u32Reg, u8Val ) \ 146 HVD_MACRO_START \ 147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 148 HVD_MACRO_END 149 150 #define _HVD_Write2Byte( u32Reg, u16Val ) \ 151 HVD_MACRO_START \ 152 if ( ((u32Reg) & 0x01) ) \ 153 { \ 154 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 155 HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 156 } \ 157 else \ 158 { \ 159 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 160 } \ 161 HVD_MACRO_END 162 163 #define _HVD_Write3Byte( u32Reg, u32Val ) \ 164 if ((u32Reg) & 0x01) \ 165 { \ 166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 167 HVD_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 168 } \ 169 else \ 170 { \ 171 HVD_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 173 } 174 175 #define _HVD_Write4Byte( u32Reg, u32Val ) \ 176 HVD_MACRO_START \ 177 if ((u32Reg) & 0x01) \ 178 { \ 179 HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 180 HVD_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 182 } \ 183 else \ 184 { \ 185 HVD_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 186 HVD_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 187 } \ 188 HVD_MACRO_END 189 190 #define _HVD_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 191 HVD_MACRO_START \ 192 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 193 HVD_MACRO_END 194 195 #define _HVD_WriteWordMask( u32Reg, u16Val , u16Msk) \ 196 HVD_MACRO_START \ 197 if ( ((u32Reg) & 0x01) ) \ 198 { \ 199 _HVD_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 200 _HVD_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 201 } \ 202 else \ 203 { \ 204 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_HVD_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 205 } \ 206 HVD_MACRO_END 207 208 //------------------------------------------------------------------------------ 209 // MVD Reg 210 //------------------------------------------------------------------------------ 211 #define REG_MVD_BASE (0x1100) 212 213 #define MVD_REG_STAT_CTRL (REG_MVD_BASE) 214 #define MVD_REG_CTRL_RST BIT(0) 215 #define MVD_REG_CTRL_INIT BIT(2) 216 #define MVD_REG_DISCONNECT_MIU BIT(6) 217 218 #define MVD_REG_PAS1_SEL_HI_OR_HILITE (REG_MVD_BASE + (0x004c<<1)) 219 #define MVD_REG_PAS2_SEL_HI_OR_HILITE (REG_MVD_BASE + (0x005c<<1)) 220 #define MVD_REG_SEL_HILITE BIT(14) 221 222 #if 1//Note: this setting should be set according client table of each chip 223 #define MIU0_REG_BASE 0x1200 224 #define MIU1_REG_BASE 0x0600 225 226 #define MIU_CLIENT_SELECT_GP2 (MIU0_REG_BASE + (0x007A<<1)) 227 #define MIU_CLIENT_SELECT_GP2_MVD BIT(4) 228 #endif 229 230 231 232 //------------------------------------------------------------------------------ 233 // HVD Reg 234 //------------------------------------------------------------------------------ 235 // on kano, pHVDHalContext->_stCtx[0] for HWDEC_EVD and pHVDHalContext->_stCtx[1] for HWDEC_EVD_LITE 236 #define HWDEC_EVD 0 237 #define HWDEC_EVD_LITE 1 238 239 #define REG_HVD_BASE (0x1B00) 240 #define REG_EVD_BASE (0x1C00) 241 #define REG_EVD_LITE_BASE (0x1700) 242 #define REG_MIU_SOURCE_BASE (0x0600) 243 #define REG_G2VP9_BASE (0x60E00) 244 245 #define EVD_BASE(evd) ((evd==HWDEC_EVD)?(REG_EVD_BASE):(REG_EVD_LITE_BASE)) 246 247 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1)) 248 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1)) 249 #define HVD_REG_RESET_SWRST BIT(0) 250 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) 251 #define HVD_REG_RESET_SWRST_FIN BIT(2) 252 #define HVD_REG_RESET_STOP_BBU BIT(3) 253 #define HVD_REG_RESET_MIU_RDY BIT(4) 254 #define HVD_REG_RESET_MIU1_128 BIT(5) 255 #define HVD_REG_RESET_MIU1_256 BIT(6) 256 #define HVD_REG_MC_MIU_256 BIT(7) 257 #define HVD_REG_RESET_HK_AVS_MODE BIT(8) 258 #define HVD_REG_RESET_HK_RM_MODE BIT(9) 259 #define HVD_REG_RESET_HK_RV9_DEC_MODE BIT(10) 260 #define HVD_REG_RESET_MIU_128 BIT(11) 261 #define HVD_REG_RESET_CPUIF_SEL BIT(12) 262 #define HVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 263 #define HVD_REG_RESET_MIU_256 BIT(14) 264 #define HVD_REG_RESET_BOND_HD BIT(15) 265 266 #define HVD_REG_ESB_ST_ADDR_L(reg_base) (reg_base + ((0x0002) << 1)) 267 #define HVD_REG_ESB_ST_ADDR_H(reg_base) (reg_base + ((0x0003) << 1)) 268 269 #define HVD_REG_ESB_LENGTH_L(reg_base) (reg_base + ((0x0004) << 1)) 270 #define HVD_REG_ESB_LENGTH_H(reg_base) (reg_base + ((0x0005) << 1)) 271 272 #define HVD_REG_ESB_RPTR(reg_base) (reg_base + ((0x0006) << 1)) 273 #define HVD_REG_ESB_RPTR_POLL BIT(0) 274 275 #define HVD_REG_ESB_RPTR_H(reg_base) (reg_base + ((0x0007) << 1)) 276 277 #define HVD_REG_MIF_BBU(reg_base) (reg_base + ((0x0008) << 1)) 278 #define HVD_REG_MIF_OFFSET_L_BITS 7 279 #define HVD_REG_MIF_OFFSET_H BIT(12) 280 #define HVD_REG_BBU_TSP_INPUT BIT(8) 281 #define HVD_REG_BBU_PASER_MASK (BIT(10) | BIT(9)) 282 #define HVD_REG_BBU_PASER_DISABLE 0 283 #define HVD_REG_BBU_PASER_ENABLE_ALL BIT(9) 284 #define HVD_REG_BBU_PASER_ENABLE_03 (BIT(9) | BIT(10)) 285 #define HVD_REG_BBU_AUTO_NAL_TAB BIT(11) 286 287 #define HVD_REG_NAL_TBL_ST_ADDR_L(reg_base) (reg_base + ((0x0009) << 1)) 288 #define HVD_REG_NAL_TBL_ST_ADDR_H(reg_base) (reg_base + ((0x000A) << 1)) 289 290 #define HVD_REG_HI_MBOX0_L(reg_base) (reg_base + ((0x000B) << 1)) 291 #define HVD_REG_HI_MBOX0_H(reg_base) (reg_base + ((0x000C) << 1)) 292 #define HVD_REG_HI_MBOX1_L(reg_base) (reg_base + ((0x000D) << 1)) 293 #define HVD_REG_HI_MBOX1_H(reg_base) (reg_base + ((0x000E) << 1)) 294 #define HVD_REG_HI_MBOX_SET(reg_base) (reg_base + ((0x000F) << 1)) 295 #define HVD_REG_HI_MBOX0_SET BIT(0) 296 #define HVD_REG_HI_MBOX1_SET BIT(8) 297 298 #define HVD_REG_RISC_MBOX_CLR(reg_base) (reg_base + ((0x0010) << 1)) 299 #define HVD_REG_RISC_MBOX0_CLR BIT(0) 300 #define HVD_REG_RISC_MBOX1_CLR BIT(1) 301 #define HVD_REG_RISC_ISR_CLR BIT(2) 302 #define HVD_REG_NAL_WPTR_SYNC BIT(3) 303 #define HVD_REG_RISC_ISR_MSK BIT(6) 304 #define HVD_REG_RISC_ISR_FORCE BIT(10) 305 306 #define HVD_REG_RISC_MBOX_RDY(reg_base) (reg_base + ((0x0011) << 1)) 307 #define HVD_REG_RISC_MBOX0_RDY BIT(0) 308 #define HVD_REG_RISC_MBOX1_RDY BIT(4) 309 #define HVD_REG_RISC_ISR_VALID BIT(8) 310 311 #define HVD_REG_HI_MBOX_RDY(reg_base) (reg_base + ((0x0012) << 1)) 312 #define HVD_REG_HI_MBOX0_RDY BIT(0) 313 #define HVD_REG_HI_MBOX1_RDY BIT(8) 314 315 #define HVD_REG_RISC_MBOX0_L(reg_base) (reg_base + ((0x0013) << 1)) 316 #define HVD_REG_RISC_MBOX0_H(reg_base) (reg_base + ((0x0014) << 1)) 317 #define HVD_REG_RISC_MBOX1_L(reg_base) (reg_base + ((0x0015) << 1)) 318 #define HVD_REG_RISC_MBOX1_H(reg_base) (reg_base + ((0x0016) << 1)) 319 320 #define HVD_REG_POLL_NAL_RPTR(reg_base) (reg_base + ((0x0017) << 1)) 321 #define HVD_REG_POLL_NAL_RPTR_BIT BIT(0) 322 #define HVD_REG_NAL_RPTR_HI(reg_base) (reg_base + ((0x0018) << 1)) 323 #define HVD_REG_NAL_WPTR_HI(reg_base) (reg_base + ((0x0019) << 1)) 324 #define HVD_REG_NAL_TAB_LEN(reg_base) (reg_base + ((0x0020) << 1)) 325 326 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1)) 327 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1)) 328 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1)) 329 330 /* Second bitstream registers definition */ 331 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1)) 332 #define HVD_REG_MODE_HK_AVS_MODE_BS2 BIT(8) 333 #define HVD_REG_MODE_HK_RM_MODE_BS2 BIT(9) 334 #define HVD_REG_MODE_HK_RV9_DEC_MODE_BS2 BIT(10) 335 336 #define HVD_REG_ESB_ST_ADDR_L_BS2(reg_base) (reg_base + ((0x0032) << 1)) 337 #define HVD_REG_ESB_ST_ADDR_H_BS2(reg_base) (reg_base + ((0x0033) << 1)) 338 339 #define HVD_REG_ESB_LENGTH_L_BS2(reg_base) (reg_base + ((0x0034) << 1)) 340 #define HVD_REG_ESB_LENGTH_H_BS2(reg_base) (reg_base + ((0x0035) << 1)) 341 342 #define HVD_REG_ESB_RPTR_L_BS2(reg_base) (reg_base + ((0x0036) << 1)) 343 #define HVD_REG_ESB_RPTR_H_BS2(reg_base) (reg_base + ((0x0037) << 1)) 344 345 #define HVD_REG_MIF_BBU_BS2(reg_base) (reg_base + ((0x0038) << 1)) 346 #define HVD_REG_MIF_OFFSET_L_BITS_BS2 7 347 #define HVD_REG_MIF_OFFSET_H_BS2 BIT(12) 348 #define HVD_REG_BBU_TSP_INPUT_BS2 BIT(8) 349 #define HVD_REG_BBU_PASER_MASK_BS2 (BIT(10) | BIT(9)) 350 #define HVD_REG_BBU_PASER_DISABLE_BS2 0 351 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS2 BIT(9) 352 #define HVD_REG_BBU_PASER_ENABLE_03_BS2 (BIT(9) | BIT(10)) 353 #define HVD_REG_BBU_AUTO_NAL_TAB_BS2 BIT(11) 354 355 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS2(reg_base) (reg_base + ((0x0039) << 1)) 356 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS2(reg_base) (reg_base + ((0x003A) << 1)) 357 358 #define HVD_REG_NAL_RPTR_HI_BS2(reg_base) (reg_base + ((0x003B) << 1)) 359 #define HVD_REG_NAL_WPTR_HI_BS2(reg_base) (reg_base + ((0x003C) << 1)) 360 #define HVD_REG_NAL_TAB_LEN_BS2(reg_base) (reg_base + ((0x003D) << 1)) 361 362 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1)) 363 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1)) 364 365 /* VP8 Registers */ 366 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1)) 367 #define HVD_REG_HK_VP8_DEC_MODE BIT(0) 368 #define HVD_REG_HK_PLAYER_FM BIT(1) 369 370 #define HVD_REG_ESB_ST_ADR_L_BS34 (REG_HVD_BASE + ((0x0042) << 1)) 371 #define HVD_REG_ESB_ST_ADR_H_BS34 (REG_HVD_BASE + ((0x0043) << 1)) 372 #define HVD_REG_ESB_LENGTH_L_BS34 (REG_HVD_BASE + ((0x0044) << 1)) 373 #define HVD_REG_ESB_LENGTH_H_BS34 (REG_HVD_BASE + ((0x0045) << 1)) 374 375 #define EVD_REG_MIF_SOURCE_GROUP0 (REG_MIU_SOURCE_BASE + ((0x0078) << 1)) 376 #define EVD_REG_MIF_SOURCE_GROUP1 (REG_MIU_SOURCE_BASE + ((0x0079) << 1)) 377 #define EVD_REG_MIF_SOURCE_GROUP2 (REG_MIU_SOURCE_BASE + ((0x007A) << 1)) 378 #define EVD_REG_MIF_SOURCE_GROUP3 (REG_MIU_SOURCE_BASE + ((0x007B) << 1)) 379 #define EVD_REG_MIF_SOURCE_GROUP4 (REG_MIU_SOURCE_BASE + ((0x007C) << 1)) 380 #define EVD_REG_MIF_SOURCE_GROUP5 (REG_MIU_SOURCE_BASE + ((0x007B) << 1)) 381 382 #define HVD_REG_MIF_BS34 (REG_HVD_BASE + ((0x0048) << 1)) 383 #define HVD_REG_BS34_MIF_OFFSET_L_BITS 7 384 #define HVD_REG_BS34_MIF_OFFSET_H BIT(12) 385 #define HVD_REG_BS34_TSP_INPUT BIT(8) 386 #define HVD_REG_BS34_PASER_MASK (BIT(10) | BIT(9)) 387 #define HVD_REG_BS34_PASER_DISABLE 0 388 #define HVD_REG_BS34_PASER_ENABLE_ALL BIT(9) 389 #define HVD_REG_BS34_PASER_ENABLE_03 (BIT(9) | BIT(10)) 390 #define HVD_REG_BS34_AUTO_NAL_TAB BIT(11) 391 #define HVD_REG_BS34_NAL_BUF_SKIP BIT(13) 392 #define HVD_REG_BS34_NAL_BUF_SKIP_RDY BIT(14) 393 394 #define HVD_REG_NAL_TAB_ST_L_BS3 (REG_HVD_BASE + ((0x0049) << 1)) 395 #define HVD_REG_NAL_TAB_ST_H_BS3 (REG_HVD_BASE + ((0x004A) << 1)) 396 #define HVD_REG_NAL_RPTR_HI_BS3 (REG_HVD_BASE + ((0x004B) << 1)) 397 #define HVD_REG_NAL_WPTR_HI_BS3 (REG_HVD_BASE + ((0x004C) << 1)) 398 #define HVD_REG_NAL_TAB_LEN_BS3 (REG_HVD_BASE + ((0x004D) << 1)) 399 #define HVD_REG_NAL_TAB_ST_L_BS4 (REG_HVD_BASE + ((0x0059) << 1)) 400 #define HVD_REG_NAL_TAB_ST_H_BS4 (REG_HVD_BASE + ((0x005A) << 1)) 401 #define HVD_REG_NAL_RPTR_HI_BS4 (REG_HVD_BASE + ((0x005B) << 1)) 402 #define HVD_REG_NAL_WPTR_HI_BS4 (REG_HVD_BASE + ((0x005C) << 1)) 403 #define HVD_REG_NAL_TAB_LEN_BS4 (REG_HVD_BASE + ((0x005D) << 1)) 404 405 //------------------------------------------------------------------------------ 406 // EVD Reg 407 //------------------------------------------------------------------------------ 408 #define REG_EVDPLL_BASE (0x10B00) 409 #define REG_EVDPLL_PD (REG_EVDPLL_BASE + ((0x0041) << 1)) 410 #define REG_EVDPLL_PD_DIS BIT(8) 411 412 #define EVD_REG_RESET(evd) (EVD_BASE(evd) + ((0x0001) << 1)) 413 #define EVD_REG_RESET_SWRST BIT(0) 414 #define EVD_REG_RESET_SWRST_FIN BIT(2) 415 #define EVD_REG_RESET_STOP_BBU BIT(3) 416 #define EVD_REG_RESET_MIU_RDY BIT(4) 417 #define EVD_REG_RESET_MIU1_128 BIT(5) 418 #define EVD_REG_RESET_MIU1_256 BIT(6) 419 #define EVD_REG_RESET_USE_HVD_MIU_EN BIT(7) 420 #define EVD_REG_RESET_HK_HEVC_MODE BIT(8) 421 #define EVD_REG_RESET_HK_TSP2EVD_EN BIT(9) 422 #define EVD_REG_RESET_MIU0_256 BIT(10) 423 #define EVD_REG_RESET_MIU0_128 BIT(11) 424 #define EVD_REG_RESET_CPUIF_SEL BIT(12) 425 #define EVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 426 #define EVD_REG_RESET_BOND_UHD BIT(14) 427 #define EVD_REG_RESET_BOND_HD BIT(15) 428 429 //------------------------------------------------------------------------------ 430 // G2 VP9 Reg 431 //------------------------------------------------------------------------------ 432 #if SUPPORT_G2VP9 && defined(VDEC3) 433 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1)) 434 #define VP9_REG_RESET_SWRST BIT(0) 435 #define VP9_REG_RESET_SWRST_FIN BIT(2) 436 #define VP9_REG_RESET_MIU_RDY BIT(4) 437 #define VP9_REG_RESET_ALL_SRAM_SD_EN BIT(13) 438 #define VP9_REG_RESET_APB_SEL BIT(15) 439 #endif 440 441 #define EVD_REG_VP9_MODE(evd) (EVD_BASE(evd) + ((0x001b) << 1)) 442 #define EVD_REG_SET_VP9_MODE BIT(0) 443 444 445 //------------------------------------------------------------------------------ 446 // ChipTop Reg 447 //------------------------------------------------------------------------------ 448 449 #define CHIPTOP_REG_BASE (0x1E00) 450 #define CLKGEN0_REG_BASE (0x0B00) 451 #define CLKGEN2_REG_BASE (0x0A00) 452 453 #define REG_TOP_PSRAM0_1_MIUMUX (CHIPTOP_REG_BASE+(0x002D<<1)) //TODO 454 #define TOP_CKG_PSRAM0_MASK BMASK(1:0) 455 #define TOP_CKG_PSRAM0_DIS BIT(0) 456 #define TOP_CKG_PSRAM0_INV BIT(1) 457 #define TOP_CKG_PSRAM1_MASK BMASK(3:2) 458 #define TOP_CKG_PSRAM1_DIS BIT(0) 459 #define TOP_CKG_PSRAM1_INV BIT(1) 460 #define TOP_MIU_MUX_G07_MASK BMASK(7:6) 461 #define TOP_MIU_MUX_G07_OD_LSB_R BITS(7:6,0) 462 #define TOP_MIU_MUX_G07_GOP2_R BITS(7:6,1) 463 #define TOP_MIU_MUX_G08_MASK BMASK(9:8) 464 #define TOP_MIU_MUX_G08_OD_LSB_W BITS(9:8,0) 465 #define TOP_MIU_MUX_G08_VE_W BITS(9:8,1) 466 #define TOP_MIU_MUX_G15_MASK BMASK(11:10) 467 #define TOP_MIU_MUX_G15_GOP2_R BITS(11:10,0) 468 #define TOP_MIU_MUX_G15_OD_LSB_R BITS(11:10,1) 469 #define TOP_MIU_MUX_G1A_MASK BMASK(13:12) 470 #define TOP_MIU_MUX_G1A_VE_W BITS(13:12,0) 471 #define TOP_MIU_MUX_G1A_OD_LSB_W BITS(13:12,1) 472 #define TOP_MIU_MUX_G26_MASK BMASK(15:14) 473 #define TOP_MIU_MUX_G26_RVD_RW BITS(15:14,0) 474 #define TOP_MIU_MUX_G26_SVD_INTP_R BITS(15:14,1) 475 #define TOP_MIU_MUX_G26_MVD_R BITS(15:14,2) 476 477 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 478 #define TOP_CKG_VPU_MASK BMASK(6:0) 479 #define TOP_CKG_VPU_DIS BIT(0) 480 #define TOP_CKG_VPU_INV BIT(1) 481 #define TOP_CKG_VPU_CLK_MASK BMASK(6:2) 482 #define TOP_CKG_VPU_480MHZ BITS(6:2, 3) 483 #define TOP_CKG_VPU_432MHZ BITS(6:2, 6) 484 #define TOP_CKG_VPU_384MHZ BITS(6:2, 7) 485 #define TOP_CKG_VPU_ICG_EN BIT(8) 486 #define TOP_CKG_VPU_LITE_ICG_EN BIT(9) 487 488 #define REG_TOP_HVD (CLKGEN0_REG_BASE+(0x0034<<1)) 489 #define TOP_CKG_HVD_MASK BMASK(4:0) 490 #define TOP_CKG_HVD_DIS BIT(0) 491 #define TOP_CKG_HVD_INV BIT(1) 492 #define TOP_CKG_HVD_CLK_MASK BMASK(4:2) 493 #define TOP_CKG_HVD_384MHZ BITS(4:2, 0) // default use this 494 #define TOP_CKG_HVD_288MHZ BITS(4:2, 3) 495 #define TOP_CKG_HVD_432MHZ BITS(4:2, 7) // for overclocking 496 497 #if SUPPORT_G2VP9 && defined(VDEC3) 498 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) 499 #define TOP_CKG_VP9_MASK BMASK(8:4) 500 #define TOP_CKG_VP9_DIS BIT(4) 501 #define TOP_CKG_VP9_INV BIT(5) 502 #define TOP_CKG_VP9_CLK_MASK BMASK(8:6) 503 #define TOP_CKG_VP9_432MHZ BITS(8:6,0) 504 #define TOP_CKG_VP9_384MHZ BITS(8:6,1) 505 #define TOP_CKG_VP9_345MHZ BITS(8:6,2) 506 #define TOP_CKG_VP9_320MHZ BITS(8:6,3) 507 #define TOP_CKG_VP9_288MHZ BITS(8:6,4) 508 #define TOP_CKG_VP9_240MHZ BITS(8:6,5) 509 #define TOP_CKG_VP9_216MHZ BITS(8:6,6) 510 #define TOP_CKG_VP9_172MHZ BITS(8:6,7) 511 #endif 512 513 #define REG_TOP_MVD (CLKGEN0_REG_BASE+(0x0039<<1)) 514 #define TOP_CKG_MVD_MASK BMASK(3:0) 515 #define TOP_CKG_MHVD_DIS BIT(0) 516 #define TOP_CKG_MVD_INV BIT(1) 517 #define TOP_CKG_MVD_CLK_MASK BMASK(3:2) 518 #define TOP_CKG_MVD_144MHZ BITS(3:2, 0) 519 #define TOP_CKG_MVD_123MHZ BITS(3:2, 1) 520 #define TOP_CKG_MVD_MIU BITS(3:2, 2) 521 #define TOP_CKG_MVD_XTAL BITS(3:2, 3) 522 523 #define REG_TOP_MVD2 (CLKGEN0_REG_BASE+(0x0039<<1)) 524 #define TOP_CKG_MVD2_MASK BMASK(11:8) 525 #define TOP_CKG_MHVD2_DIS BIT(8) 526 #define TOP_CKG_MVD2_INV BIT(9) 527 #define TOP_CKG_MVD2_CLK_MASK BMASK(11:10) 528 #define TOP_CKG_MVD2_170MHZ BITS(11:10, 0) 529 #define TOP_CKG_MVD2_144MHZ BITS(11:10, 1) 530 #define TOP_CKG_MVD2_160MHZ BITS(11:10, 1) 531 #define TOP_CKG_MVD2_CLK_MIU_P BITS(11:10, 1) 532 533 #define REG_TOP_CKG_EVD_PPU (CLKGEN2_REG_BASE+(0x001c<<1)) 534 #define TOP_CKG_EVD_PPU_MASK BMASK(4:2) 535 #define TOP_CKG_EVD_PPU_DIS BIT(0) 536 #define TOP_CKG_EVD_PPU_INV BIT(1) 537 #define TOP_CKG_EVD_PPU_PLL_BUF BITS(4:2, 0) 538 #define TOP_CKG_EVD_PPU_MIU128PLL BITS(4:2, 1) 539 #define TOP_CKG_EVD_PPU_MIU256PLL BITS(4:2, 2) 540 #define TOP_CKG_EVD_PPU_480MHZ BITS(4:2, 3) 541 #define TOP_CKG_EVD_PPU_384MHZ BITS(4:2, 4) 542 #define TOP_CKG_EVD_PPU_320MHZ BITS(4:2, 5) 543 #define TOP_CKG_EVD_PPU_240MHZ BITS(4:2, 6) 544 #define TOP_CKG_EVD_PPU_192MHZ BITS(4:2, 7) 545 546 #define REG_TOP_CKG_EVD (CLKGEN0_REG_BASE+(0x003d<<1)) 547 #define TOP_CKG_EVD_MASK BMASK(4:2) 548 #define TOP_CKG_EVD_DIS BIT(0) 549 #define TOP_CKG_EVD_INV BIT(1) 550 #define TOP_CKG_EVD_PLL_BUF BITS(4:2, 0) 551 #define TOP_CKG_EVD_MIU128PLL BITS(4:2, 1) 552 #define TOP_CKG_EVD_MIU256PLL BITS(4:2, 2) 553 #define TOP_CKG_EVD_480MHZ BITS(4:2, 3) 554 #define TOP_CKG_EVD_384MHZ BITS(4:2, 4) 555 #define TOP_CKG_EVD_320MHZ BITS(4:2, 5) 556 #define TOP_CKG_EVD_240MHZ BITS(4:2, 6) 557 #define TOP_CKG_EVD_192MHZ BITS(4:2, 7) 558 559 #define REG_TOP_UART_SEL0 (CHIPTOP_REG_BASE+(0x0053<<1)) 560 #define REG_TOP_UART_SEL_0_MASK BMASK(3:0) 561 #define REG_TOP_UART_SEL_MHEG5 BITS(3:0, 1) 562 #define REG_TOP_UART_SEL_VD_MHEG5 BITS(3:0, 2) 563 #define REG_TOP_UART_SEL_TSP BITS(3:0, 3) 564 #define REG_TOP_UART_SEL_PIU_0 BITS(3:0, 4) 565 #define REG_TOP_UART_SEL_PIU_1 BITS(3:0, 5) 566 #define REG_TOP_UART_SEL_PIU_FAST BITS(3:0, 7) 567 #define REG_TOP_UART_SEL_VD_R2_LITE BITS(3:0, 8) 568 #define REG_TOP_UART_SEL_VD_MCU_51_TXD0 BITS(3:0, 10) 569 #define REG_TOP_UART_SEL_VD_MCU_51_TXD1 BITS(3:0, 11) 570 571 //------------------------------------------------------------------------------ 572 573 #define REG_TOP_CKG_EVD_LITE (CLKGEN2_REG_BASE+(0x0017<<1)) 574 #define TOP_CKG_EVD_LITE_MASK BMASK(4:2) 575 #define TOP_CKG_EVD_LITE_DIS BIT(0) 576 #define TOP_CKG_EVD_LITE_INV BIT(1) 577 #define TOP_CKG_EVD_LITE_PLL_BUF BITS(4:2, 0) 578 #define TOP_CKG_EVD_LITE_MIU128PLL BITS(4:2, 1) 579 #define TOP_CKG_EVD_LITE_MIU256PLL BITS(4:2, 2) 580 #define TOP_CKG_EVD_LITE_480MHZ BITS(4:2, 3) 581 #define TOP_CKG_EVD_LITE_384MHZ BITS(4:2, 4) 582 #define TOP_CKG_EVD_LITE_320MHZ BITS(4:2, 5) 583 #define TOP_CKG_EVD_LITE_240MHZ BITS(4:2, 6) 584 #define TOP_CKG_EVD_LITE_192MHZ BITS(4:2, 7) 585 586 #define REG_TOP_CKG_EVD_PPU_LITE (CLKGEN2_REG_BASE+(0x0017<<1)) 587 #define TOP_CKG_EVD_PPU_LITE_MASK BMASK(12:10) 588 #define TOP_CKG_EVD_PPU_LITE_DIS BIT(8) 589 #define TOP_CKG_EVD_PPU_LITE_INV BIT(9) 590 #define TOP_CKG_EVD_PPU_LITE_PLL_BUF BITS(12:10, 0) 591 #define TOP_CKG_EVD_PPU_LITE_MIU128PLL BITS(12:10, 1) 592 #define TOP_CKG_EVD_PPU_LITE_MIU256PLL BITS(12:10, 2) 593 #define TOP_CKG_EVD_PPU_LITE_480MHZ BITS(12:10, 3) 594 #define TOP_CKG_EVD_PPU_LITE_384MHZ BITS(12:10, 4) 595 #define TOP_CKG_EVD_PPU_LITE_320MHZ BITS(12:10, 5) 596 #define TOP_CKG_EVD_PPU_LITE_240MHZ BITS(12:10, 6) 597 #define TOP_CKG_EVD_PPU_LITE_192MHZ BITS(12:10, 7) 598 599 #define REG_TOP_HVD_AEC_LITE (CLKGEN2_REG_BASE+(0x0018<<1)) 600 #define TOP_CKG_HVD_AEC_LITE_MASK BMASK(4:0) 601 #define TOP_CKG_HVD_AEC_LITE_DIS BIT(0) 602 #define TOP_CKG_HVD_AEC_LITE_INV BIT(1) 603 #define TOP_CKG_HVD_AEC_LITE_CLK_MASK BMASK(3:2) 604 #define TOP_CKG_HVD_AEC_LITE_288MHZ BITS(3:2, 0) //default use this 605 #define TOP_CKG_HVD_AEC_LITE_240MHZ BITS(3:2, 1) 606 #define TOP_CKG_HVD_AEC_LITE_216MHZ BITS(3:2, 2) 607 #define TOP_CKG_HVD_AEC_LITE_320MHZ BITS(3:2, 3) 608 609 #define REG_TOP_HVD_IDB (CLKGEN2_REG_BASE+(0x001a<<1)) 610 #define TOP_CKG_HVD_IDB_CLK_MASK BMASK(2:0) 611 #define TOP_CKG_HVD_IDB_432MHZ BITS(2:0, 0) // default use this 612 #define TOP_CKG_HVD_IDB_384MHZ BITS(2:0, 1) 613 #define TOP_CKG_HVD_IDB_480MHZ BITS(2:0, 3) // for overclocking 614 615 #define REG_TOP_HVD_AEC (CLKGEN2_REG_BASE+(0x001b<<1)) 616 #define TOP_CKG_HVD_AEC_MASK BMASK(4:0) 617 #define TOP_CKG_HVD_AEC_DIS BIT(0) 618 #define TOP_CKG_HVD_AEC_INV BIT(1) 619 #define TOP_CKG_HVD_AEC_CLK_MASK BMASK(3:2) 620 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this 621 #define TOP_CKG_HVD_AEC_240MHZ BITS(3:2, 1) 622 #define TOP_CKG_HVD_AEC_216MHZ BITS(3:2, 2) 623 #define TOP_CKG_HVD_AEC_320MHZ BITS(3:2, 3) // for overclocking 624 625 #define REG_TOP_VP8 (CLKGEN2_REG_BASE+(0x001d<<1)) 626 #define TOP_CKG_VP8_MASK BMASK(3:0) 627 #define TOP_CKG_VP8_DIS BIT(0) 628 #define TOP_CKG_VP8_INV BIT(1) 629 #define TOP_CKG_VP8_CLK_MASK BMASK(3:2) 630 #define TOP_CKG_VP8_288MHZ BITS(3:2, 0) // default use this 631 #define TOP_CKG_VP8_240MHZ BITS(3:2, 1) 632 #define TOP_CKG_VP8_216MHZ BITS(3:2, 2) 633 #define TOP_CKG_VP8_320MHZ BITS(3:2, 3) // for overclocking 634 635 //------------------------------------------------------------------------------ 636 // MIU Reg 637 //------------------------------------------------------------------------------ 638 #define MIU0_REG_HVD_BASE (0x1200) 639 #define MIU0_REG_HVD_BASE2 (0x61500) 640 641 #define MIU1_REG_HVD_BASE (0x0600) 642 #define MIU1_REG_HVD_BASE2 (0x62200) 643 644 #define MIU2_REG_HVD_BASE (0x62000) 645 #define MIU2_REG_HVD_BASE2 (0x62300) 646 647 648 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1)) 649 #define MIU0_CLIENT_SELECT_GP4_HVD_MIF0 BIT(4) 650 #define MIU0_CLIENT_SELECT_GP4_HVD_MIF1 BIT(5) 651 652 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1)) 653 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF0 BIT(4) 654 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF1 BIT(5) 655 656 657 //#define MIU2_REG_HVD_BASE (0x62000) 658 //#define MIU2_REG_HVD_BASE2 (0x62300) 659 660 661 662 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 663 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 664 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 665 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 666 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) 667 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1)) 668 669 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 670 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 671 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 672 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 673 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1)) 674 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1)) 675 676 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) 677 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1)) 678 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) 679 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1)) 680 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) 681 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1)) 682 683 684 685 686 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 687 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 688 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 689 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 690 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) 691 #define MIU0_REG_SEL5 (MIU0_REG_HVD_BASE+(( 0x007D)<<1)) 692 693 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1)) 694 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1)) 695 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1)) 696 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1)) 697 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1)) 698 #define MIU2_REG_SEL5 (MIU2_REG_HVD_BASE+(( 0x007D)<<1)) 699 700 701 //#define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1)) 702 703 704 #define MIU_HVD_RW (BIT(10)|BIT(11)) 705 #define MIU_MVD_RW (BIT(5)|BIT(6)) 706 707 //------------------------------------------------------------------------------ 708 // SRAM Reg 709 //------------------------------------------------------------------------------ 710 711 #ifdef CONFIG_MSTAR_SRAMPD 712 #define REG_PATGEN_HI_BASE 0x71300 713 #define REG_PATGEN_VP9_BASE 0x71800 714 715 #define REG_HICODEC_SRAM_SD_EN (REG_PATGEN_HI_BASE+(( 0x0010)<<1)) 716 #define HICODEC_SRAM_HICODEC0 BIT(0) 717 #define HICODEC_SRAM_HICODEC1 BIT(1) 718 719 #define REG_HICODEC_LITE_SRAM_SD_EN (REG_PATGEN_VP9_BASE+(( 0x0010)<<1)) 720 #define HICODEC_LITE_SRAM_HICODEC0 BIT(0) 721 #define HICODEC_LITE_SRAM_HICODEC1 BIT(1) 722 #endif 723 724 //------------------------------------------------------------------------------------------------- 725 // Type and Structure 726 //------------------------------------------------------------------------------------------------- 727 728 729 #endif // _REG_HVD_H_ 730 731